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Revision 1.77 - (view) (annotate) - [select for diffs]
Sat Jun 16 02:16:40 2012 UTC (2 years, 3 months ago) by asvitkine
Branch: MAIN
CVS Tags: HEAD
Changes since 1.76: +31 -3 lines
Diff to previous 1.76 , to selected 1.26
Dump PPC disassembly on crash


Revision 1.76 - (view) (annotate) - [select for diffs]
Tue Aug 18 18:26:11 2009 UTC (5 years ago) by asvitkine
Branch: MAIN
Changes since 1.75: +9 -9 lines
Diff to previous 1.75 , to selected 1.26
[Michael Schmitt]
Attached is a patch to SheepShaver to fix memory allocation problems when OS X 10.5 is the host. It also relaxes the 512 MB RAM limit on OS X hosts.


Problem
-------
Some users have been unable to run SheepShaver on OS X 10.5 (Leopard) hosts. The symptom is error "ERROR: Cannot map RAM: File already exists".

SheepShaver allocates RAM at fixed addresses. If it is running in "Real" addressing mode, and can't allocate at address 0, then it was hard-coded to allocate the RAM area at 0x20000000. The ROM area as allocated at 0x40800000.

The normal configuration is for SheepShaver to run under SDL, which is a Cocoa wrapper. By the time SheepShaver does its memory allocations, the Cocoa application has already started. The result is the SheepShaver memory address space already contains libraries, fonts, Input Managers, and IOKit areas.

On Leopard hosts these areas can land on the same addresses SheepShaver needs, so SheepShaver's memory allocation fails.


Solution
--------
The approach is to change SheepShaver (on Unix & OS X hosts) to allocate the RAM area anywhere it can find the space, rather than at a fixed address.

This could result in the RAM allocated higher than the ROM area, which causes a crash. To prevent this from occurring, the RAM and ROM areas are allocated contiguously.

Previously the ROM starting address was a constant ROM_BASE, which was used throughout the source files. The ROM start address is now a variable ROMBase. ROMBase is allocated and set by main_*.cpp just like RAMBase.

A side-effect of this change is that it lifts the 512 MB RAM limit for OS X hosts. The limit was because the fixed RAM and ROM addresses were such that the RAM could only be 512 MB before it overlapped the ROM area.


Impact
------
The change to make ROMBase a variable is throughout all hosts & addressing modes.

The RAM and ROM areas will only shift when run on Unix & OS X hosts, otherwise the same fixed allocation address is used as before.

This change is limited to "Real" addressing mode. Unlike Basilisk II, SheepShaver *pre-calculates* the offset for "Direct" addressing mode; the offset is compiled into the program. If the RAM address were allowed to shift, it could result in the RAM area wrapping around address 0.


Changes to main_unix.cpp
------------------------
1. Real addressing mode no longer defines a RAM_BASE constant.

2. The base address of the Mac ROM (ROMBase) is defined and exported by this program.

3. Memory management helper vm_mac_acquire is renamed to vm_mac_acquire_fixed. Added a new memory management helper vm_mac_acquire, which allocates memory at any address.

4. Changed and rearranged the allocation of RAM and ROM areas.

Before it worked like this:

  - Allocate ROM area
  - If can, attempt to allocate RAM at address zero
  - If RAM not allocated at 0, allocate at fixed address

We still want to try allocating the RAM at zero, and if using DIRECT addressing we're still going to use the fixed addresses. So we don't know where the ROM should be until after we do the RAM. The new logic is:

  - If can, attempt to allocate RAM at address zero
  - If RAM not allocated at 0
      if REAL addressing
         allocate RAM and ROM together. The ROM address is aligned to a 1 MB boundary
      else (direct addressing)
         allocate RAM at fixed address
  - If ROM hasn't been allocated yet, allocate at fixed address

5. Calculate ROMBase and ROMBaseHost based on where the ROM was loaded.

6. There is a crash if the RAM is allocated too high. To try and catch this, check if it was allocated higher than the kernel data address.

7. Change subsequent code from using constant ROM_BASE to variable ROMBase.


Changes to Other Programs
-------------------------
emul_op.cpp, main.cpp, name_registery.cpp, rom_patches.cpp, rsrc_patches.cpp, emul_ppc.cpp, sheepshaver_glue.cpp, ppc-translate-cpp:
Change from constant ROM_BASE to variable ROMBase.

ppc_asm.S: It was setting register to a hard-coded literal address: 0x40b0d000. Changed to set it to ROMBase + 0x30d000.

ppc_asm.tmpl: It defined a macro ASM_LO16 but it assumed that the macro would always be used with operands that included a register specification. This is not true. Moved the register specification from the macro to the macro invocations.

main_beos.cpp, main_windows.cpp: Since the subprograms are all expecting a variable ROMBase, all the main_*.cpp pgrams have to define and export it. The ROM_BASE constant is moved here for consistency. The mains for beos and windows just allocate the ROM at the same fixed address as before, set ROMBaseHost and ROMBase to that address, and then use ROMBase for the subsequent code.

cpu_emulation.h: removed ROM_BASE constant. This value is moved to the main_*.cpp modules, to be consistent with RAM_BASE.

user_strings_unix.cpp, user_strings_unix.h: Added new error messages related to errors that occur when the RAM and ROM are allocated anywhere.


Revision 1.75 - (view) (annotate) - [select for diffs]
Tue Jan 1 09:47:39 2008 UTC (6 years, 8 months ago) by gbeauche
Branch: MAIN
Changes since 1.74: +1 -1 lines
Diff to previous 1.74 , to selected 1.26
Happy New Year!


Revision 1.74 - (view) (annotate) - [select for diffs]
Sun Dec 30 09:18:40 2007 UTC (6 years, 8 months ago) by gbeauche
Branch: MAIN
Changes since 1.73: +7 -7 lines
Diff to previous 1.73 , to selected 1.26
Sync with new SIGSEGV API.


Revision 1.73 - (view) (annotate) - [select for diffs]
Sun Jan 21 13:44:25 2007 UTC (7 years, 7 months ago) by gbeauche
Branch: MAIN
Changes since 1.72: +5 -7 lines
Diff to previous 1.72 , to selected 1.26
Enable JIT in non-constructor so that a user-defined value can be set later


Revision 1.72 - (view) (annotate) - [select for diffs]
Wed Jan 17 06:20:36 2007 UTC (7 years, 8 months ago) by gbeauche
Branch: MAIN
Changes since 1.71: +0 -1 lines
Diff to previous 1.71 , to selected 1.26
Remove specialised decoders. This will be done differently, if necessary.


Revision 1.71 - (view) (annotate) - [select for diffs]
Sun Jul 9 12:15:48 2006 UTC (8 years, 2 months ago) by gbeauche
Branch: MAIN
Changes since 1.70: +4 -4 lines
Diff to previous 1.70 , to selected 1.26
Remove use of global register A0 (now aliased to T0). This makes it possible
to cache the CPU context pointer to a register and thus rendering generated
code CPU context independent. Not useful to SheepShaver, but it is for
another project for threads emulation on plain x86-32.

Note: AltiVec performance may drop a little on x86 but this will be restored
(and even improved) in the future.


Revision 1.70 - (view) (annotate) - [select for diffs]
Sun May 14 07:21:10 2006 UTC (8 years, 4 months ago) by gbeauche
Branch: MAIN
Changes since 1.69: +28 -1 lines
Diff to previous 1.69 , to selected 1.26
Optimize generated code to NQD & CheckLoad functions. They don't call into
68k or MacOS code, so they don't need to be a termination point. i.e. don't
split into two basic blocks and thus avoid a full hash search.

Also add missing NQD_unknown_hook NativeOp from previous commit.


Revision 1.69 - (view) (annotate) - [select for diffs]
Sat May 13 17:12:18 2006 UTC (8 years, 4 months ago) by gbeauche
Branch: MAIN
Changes since 1.68: +9 -9 lines
Diff to previous 1.68 , to selected 1.26
NQD dirty boxes, generic code
+ while we are at it, also rename a few NQD related NativeOps.


Revision 1.68 - (view) (annotate) - [select for diffs]
Wed May 3 21:45:14 2006 UTC (8 years, 4 months ago) by gbeauche
Branch: MAIN
Changes since 1.67: +21 -46 lines
Diff to previous 1.67 , to selected 1.26
Add patches for native GetNamedResource() and Get1NamedResource(). This will
be useful to fix a bug in the AppleShare extension (see DRVR .AFPTranslator
in Basilisk II)

Unrelated improvement: call sheepshaver_cpu::get_resource() directly, don't
get it through another global function.


Revision 1.67 - (view) (annotate) - [select for diffs]
Sat Jan 21 17:18:53 2006 UTC (8 years, 7 months ago) by gbeauche
Branch: MAIN
Changes since 1.66: +1 -0 lines
Diff to previous 1.66 , to selected 1.26
don't trigger interrupt through deleted cpu object (XXX may need locks)


Revision 1.66 - (view) (annotate) - [select for diffs]
Tue Dec 6 22:25:13 2005 UTC (8 years, 9 months ago) by gbeauche
Branch: MAIN
Changes since 1.65: +0 -42 lines
Diff to previous 1.65 , to selected 1.26
Align PowerPC registers struct manually, i.e. don't depend on non-portable
compiler extensions (e.g. GCC __attribute__((aligned(N)))).


Revision 1.65 - (view) (annotate) - [select for diffs]
Sun Jul 3 22:02:01 2005 UTC (9 years, 2 months ago) by gbeauche
Branch: MAIN
Changes since 1.64: +12 -0 lines
Diff to previous 1.64 , to selected 1.26
Minor tweaks to support compilation of ether.cpp within MacOS. i.e. mostly
migrate the Ethernet driver to the MacOS side. This is enabled for
DIRECT_ADDRESSING cases. I didn't want to alter much of ether.cpp (as it
would have required to support that mode). Of course, in REAL_ADDRESSING
mode (the default) and for debugging purposes, the old driver is still
available.


Revision 1.64 - (view) (annotate) - [select for diffs]
Thu Jun 30 10:17:58 2005 UTC (9 years, 2 months ago) by gbeauche
Branch: MAIN
Changes since 1.63: +1 -0 lines
Diff to previous 1.63 , to selected 1.26
Improve idle wait mechanism. Now, the emulator thread can be suspended
(idle_wait) until events arrived and notified through TriggerInterrupt().
i.e. we no longer sleep a fixed amount of time on platforms that support
a thread wait/signal mechanism.


Revision 1.63 - (view) (annotate) - [select for diffs]
Thu Jun 30 09:09:59 2005 UTC (9 years, 2 months ago) by gbeauche
Branch: MAIN
Changes since 1.62: +2 -11 lines
Diff to previous 1.62 , to selected 1.26
Completely avoid any form of nested interrupt processing.


Revision 1.62 - (view) (annotate) - [select for diffs]
Thu Jun 30 07:34:17 2005 UTC (9 years, 2 months ago) by gbeauche
Branch: MAIN
Changes since 1.61: +1 -1 lines
Diff to previous 1.61 , to selected 1.26
Fix CR save/restore in EmulOp thunk. I don't know what it fixes for real
but that was definitely wrong to only preserve CR2 there.


Revision 1.61 - (view) (annotate) - [select for diffs]
Wed Jun 22 16:38:15 2005 UTC (9 years, 2 months ago) by gbeauche
Branch: MAIN
Changes since 1.60: +27 -21 lines
Diff to previous 1.60 , to selected 1.26
Rework sheepshaver_cpu object allocation and get rid of POSIX'ish functions.


Revision 1.60 - (view) (annotate) - [select for diffs]
Thu Mar 17 23:40:01 2005 UTC (9 years, 6 months ago) by gbeauche
Branch: MAIN
Changes since 1.59: +3 -3 lines
Diff to previous 1.59 , to selected 1.26
it makes more sense to dump the crash dump header to stderr


Revision 1.59 - (view) (annotate) - [select for diffs]
Sat Mar 5 18:33:30 2005 UTC (9 years, 6 months ago) by gbeauche
Branch: MAIN
Changes since 1.58: +11 -2 lines
Diff to previous 1.58 , to selected 1.26
Revert to no nested native ppc interrupt processing, also filter out cases
where InterruptFlags is 0.


Revision 1.58 - (view) (annotate) - [select for diffs]
Sat Mar 5 15:25:10 2005 UTC (9 years, 6 months ago) by gbeauche
Branch: MAIN
Changes since 1.57: +4 -96 lines
Diff to previous 1.57 , to selected 1.26
Preserve all necessary registers on interrupt, thus also permitting nested
interrupts to occur. SheepShaver locks should now be reduced.


Revision 1.57 - (view) (annotate) - [select for diffs]
Sun Jan 30 21:48:21 2005 UTC (9 years, 7 months ago) by gbeauche
Branch: MAIN
Changes since 1.56: +1 -1 lines
Diff to previous 1.56 , to selected 1.26
Happy New Year 2005!


Revision 1.56 - (view) (annotate) - [select for diffs]
Sun Jan 30 21:12:07 2005 UTC (9 years, 7 months ago) by gbeauche
Branch: MAIN
Changes since 1.55: +12 -0 lines
Diff to previous 1.55 , to selected 1.26
add FP regs & state to preserved context on interrupt


Revision 1.55 - (view) (annotate) - [select for diffs]
Sat Dec 18 18:40:04 2004 UTC (9 years, 9 months ago) by gbeauche
Branch: MAIN
Changes since 1.54: +0 -7 lines
Diff to previous 1.54 , to selected 1.26
ethernet seems to work with sheepnet, even on kernel 2.6/x86_64!


Revision 1.54 - (view) (annotate) - [select for diffs]
Thu Nov 25 00:21:09 2004 UTC (9 years, 9 months ago) by gbeauche
Branch: MAIN
Changes since 1.53: +6 -2 lines
Diff to previous 1.53 , to selected 1.26
16-byte aligned memory allocator only for sheepshaver_cpu


Revision 1.53 - (view) (annotate) - [select for diffs]
Mon Nov 22 22:04:38 2004 UTC (9 years, 9 months ago) by gbeauche
Branch: MAIN
Changes since 1.52: +10 -6 lines
Diff to previous 1.52 , to selected 1.26
Use BUILD_SHEEPSHAVER_PROCEDURE to allocate static procedures into the
SheepShaver globals. Fix build of sheepshaver_glue.cpp without JIT.


Revision 1.52 - (view) (annotate) - [select for diffs]
Sat Nov 13 14:09:16 2004 UTC (9 years, 10 months ago) by gbeauche
Branch: MAIN
Changes since 1.51: +8 -6 lines
Diff to previous 1.51 , to selected 1.26
Implement Direct Addressing mode similarly to Basilisk II. This is to get
SheepShaver working on OSes that don't support maipping of Low Memory globals
at 0x00000000, e.g. Windows.


Revision 1.51 - (view) (annotate) - [select for diffs]
Sun Jul 11 08:12:21 2004 UTC (10 years, 2 months ago) by gbeauche
Branch: MAIN
Changes since 1.50: +7 -0 lines
Diff to previous 1.50 , to selected 1.26
Revert last change until I can check myself...


Revision 1.50 - (view) (annotate) - [select for diffs]
Sun Jul 11 07:54:56 2004 UTC (10 years, 2 months ago) by gbeauche
Branch: MAIN
Changes since 1.49: +0 -7 lines
Diff to previous 1.49 , to selected 1.26
Enable ethernet everywhere, several users got it to work. Hangs may be
unrelated to ethernet code anyway and ethernet driver should be endian
safe nowadays.


Revision 1.49 - (view) (annotate) - [select for diffs]
Sun Jul 11 06:42:28 2004 UTC (10 years, 2 months ago) by gbeauche
Branch: MAIN
Changes since 1.48: +0 -80 lines
Diff to previous 1.48 , to selected 1.26
Remove "native" EmulOp stuff as it is useless and duplicates functionalities


Revision 1.48 - (view) (annotate) - [select for diffs]
Sat Jun 26 15:26:18 2004 UTC (10 years, 2 months ago) by gbeauche
Branch: MAIN
Changes since 1.47: +2 -5 lines
Diff to previous 1.47 , to selected 1.26
Performance of VOSF is heuristically determined at run-time, so have to
initialize SIGSEGV handlers early, as in Basilisk II. Besides, also add
missing call to vm_init() in case host system doesn't have MAP_ANON.


Revision 1.47 - (view) (annotate) - [select for diffs]
Thu Jun 24 15:37:26 2004 UTC (10 years, 2 months ago) by gbeauche
Branch: MAIN
Changes since 1.46: +9 -0 lines
Diff to previous 1.46 , to selected 1.26
SDL support in SheepShaver too, though it doesn't work in native mode
on Linux/ppc as libSDL is pulling in libpthread which conflicts with
our sheepthreads.


Revision 1.46 - (view) (annotate) - [select for diffs]
Tue Jun 22 17:10:08 2004 UTC (10 years, 2 months ago) by gbeauche
Branch: MAIN
Changes since 1.45: +1 -15 lines
Diff to previous 1.45 , to selected 1.26
Don't handle XLM_IRQ_NEST atomically in emulated mode. That's useless since
this variable is modified only within a single thread and interrupts are
not handled asynchronously.


Revision 1.45 - (view) (annotate) - [select for diffs]
Tue Jun 22 14:18:35 2004 UTC (10 years, 2 months ago) by gbeauche
Branch: MAIN
Changes since 1.44: +0 -4 lines
Diff to previous 1.44 , to selected 1.26
Always handle interrupt even if InterruptFlags == 0, though it should not
really happen in practise.


Revision 1.44 - (view) (annotate) - [select for diffs]
Sat Jun 5 07:09:38 2004 UTC (10 years, 3 months ago) by gbeauche
Branch: MAIN
Changes since 1.43: +16 -3 lines
Diff to previous 1.43 , to selected 1.26
STATS: Account for all interrupts, but still count native interrupts. It
turns out that for a regular bootup sequence to the Finder, less than 30%
interrupts triggered were in native mode.

Default EMUL_TIME_STATS to 0, end user probably doesn't want garbage to
be printed to his console.


Revision 1.43 - (view) (annotate) - [select for diffs]
Mon May 31 10:08:31 2004 UTC (10 years, 3 months ago) by gbeauche
Branch: MAIN
Changes since 1.42: +7 -1 lines
Diff to previous 1.42 , to selected 1.26
Check for SIGSEGVs from DR Cache code too.


Revision 1.42 - (view) (annotate) - [select for diffs]
Sun May 23 05:28:12 2004 UTC (10 years, 3 months ago) by gbeauche
Branch: MAIN
Changes since 1.41: +20 -13 lines
Diff to previous 1.41 , to selected 1.26
Fix NativeOp code generation, especially in PPC_REENTRANT_JIT mode


Revision 1.41 - (view) (annotate) - [select for diffs]
Thu May 20 12:33:58 2004 UTC (10 years, 3 months ago) by gbeauche
Branch: MAIN
Changes since 1.40: +31 -77 lines
Diff to previous 1.40 , to selected 1.26
Get rid of old (and broken) ASYNC_IRQ / MUTICORE code


Revision 1.40 - (view) (annotate) - [select for diffs]
Thu May 20 11:47:27 2004 UTC (10 years, 3 months ago) by gbeauche
Branch: MAIN
Changes since 1.39: +8 -1 lines
Diff to previous 1.39 , to selected 1.26
Don't allow "recursive" NanoKernel interrupts


Revision 1.39 - (view) (annotate) - [select for diffs]
Thu May 20 11:05:30 2004 UTC (10 years, 3 months ago) by gbeauche
Branch: MAIN
Changes since 1.38: +58 -8 lines
Diff to previous 1.38 , to selected 1.26
Better interrupt context checking code


Revision 1.38 - (view) (annotate) - [select for diffs]
Wed May 19 21:23:16 2004 UTC (10 years, 4 months ago) by gbeauche
Branch: MAIN
Changes since 1.37: +126 -57 lines
Diff to previous 1.37 , to selected 1.26
Make NativeOp() handler a sheepshaver_cpu handler, thus getting rid of ugly
GPR macro definition.

Make the JIT engine somewhat reentrant. This brings a massive performance
boost for applications that cause many Execute68k(). e.g. audio in PlayerPRO.


Revision 1.37 - (view) (annotate) - [select for diffs]
Sat May 15 17:26:28 2004 UTC (10 years, 4 months ago) by gbeauche
Branch: MAIN
Changes since 1.36: +83 -1 lines
Diff to previous 1.36 , to selected 1.26
Don't take an EMUL_OP mode switch for Microseconds() and SynchIdleTime()


Revision 1.36 - (view) (annotate) - [select for diffs]
Wed May 12 15:54:23 2004 UTC (10 years, 4 months ago) by gbeauche
Branch: MAIN
Changes since 1.35: +22 -0 lines
Diff to previous 1.35 , to selected 1.26
Handle SAFE_INTERRUPT_PPC to check possible nested calls (and this happens)


Revision 1.35 - (view) (annotate) - [select for diffs]
Thu Apr 22 22:54:47 2004 UTC (10 years, 4 months ago) by gbeauche
Branch: MAIN
Changes since 1.34: +21 -6 lines
Diff to previous 1.34 , to selected 1.26
Extend NativeOp count to 64 (6-bit value), aka fix NATIVE_FILLRECT opcpdes.
Translate NQD_{bitblt,fillrect,invrect} to direct native calls.
Use Mac2HostAddr() for converting Mac base address to native.


Revision 1.34 - (view) (annotate) - [select for diffs]
Thu Apr 22 21:45:18 2004 UTC (10 years, 4 months ago) by gbeauche
Branch: MAIN
Changes since 1.33: +6 -6 lines
Diff to previous 1.33 , to selected 1.26
NQD: use ReadMacInt*() and WriteMacInt*() accessors, i.e. code should now
be little-endian and 64-bit safe.


Revision 1.33 - (view) (annotate) - [select for diffs]
Thu Apr 22 20:57:31 2004 UTC (10 years, 4 months ago) by gbeauche
Branch: MAIN
Changes since 1.32: +2 -7 lines
Diff to previous 1.32 , to selected 1.26
Basic fillrect/invrect NQD. Code may need to be factored out somehow.
Verify that bitblt NQD transfer modes are really CopyBits() ones [MB5].


Revision 1.32 - (view) (annotate) - [select for diffs]
Sun Apr 18 23:03:53 2004 UTC (10 years, 5 months ago) by gbeauche
Branch: MAIN
Changes since 1.31: +23 -0 lines
Diff to previous 1.31 , to selected 1.26
Start Native QuickDraw acceleration


Revision 1.31 - (view) (annotate) - [select for diffs]
Tue Feb 24 14:09:12 2004 UTC (10 years, 6 months ago) by gbeauche
Branch: MAIN
Changes since 1.30: +17 -1 lines
Diff to previous 1.30 , to selected 1.26
16-byte aligned memory allocator will try the following functions in-order
(determined at compile-time): posix_memalign, memalign, valloc, malloc.


Revision 1.30 - (view) (annotate) - [select for diffs]
Tue Feb 24 11:12:54 2004 UTC (10 years, 6 months ago) by gbeauche
Branch: MAIN
Changes since 1.29: +4 -0 lines
Diff to previous 1.29 , to selected 1.26
Make SheepShaver work with OS 8.6 out-of-the-box with no extra patch for
the time being. i.e. ignore writes to the zero page when faking SCSIGlobals


Revision 1.29 - (view) (annotate) - [select for diffs]
Fri Feb 20 17:20:15 2004 UTC (10 years, 6 months ago) by gbeauche
Branch: MAIN
Changes since 1.28: +16 -13 lines
Diff to previous 1.28 , to selected 1.26
we have to 16-byte align sheepshaver_cpu object has it contains SSE values
that require this alignment.


Revision 1.28 - (view) (annotate) - [select for diffs]
Mon Feb 16 15:34:55 2004 UTC (10 years, 7 months ago) by gbeauche
Branch: MAIN
Changes since 1.27: +4 -1 lines
Diff to previous 1.27 , to selected 1.26
GCC 3.4 does not allow the lazy_allocator instantiation, the other form is
not supported by any GCC but ICC accepts it.


Revision 1.27 - (view) (annotate) - [select for diffs]
Sun Feb 15 17:17:36 2004 UTC (10 years, 7 months ago) by gbeauche
Branch: MAIN
Changes since 1.26: +0 -7 lines
Diff to previous 1.26
AltiVec emulation! ;-)


Revision 1.26 - (view) (annotate) - [selected]
Sat Jan 24 11:28:06 2004 UTC (10 years, 7 months ago) by gbeauche
Branch: MAIN
Changes since 1.25: +137 -22 lines
Diff to previous 1.25
Generate PowerPC code wrapping GetResource() replacements. That way, it's
a normal PPC function invocation that can be JIT compiled to native code
instead of nesting execute() calls which may lead to use the interpreter
(this took around 11% of total execution time on boot, downto 3%).

Also, optimize some SheepShaver EmulOps and actually report non-CTI.


Revision 1.25 - (view) (annotate) - [select for diffs]
Mon Jan 12 15:37:24 2004 UTC (10 years, 8 months ago) by cebix
Branch: MAIN
Changes since 1.24: +1 -1 lines
Diff to previous 1.24 , to selected 1.26
Happy New Year! :)


Revision 1.24 - (view) (annotate) - [select for diffs]
Thu Dec 25 23:54:36 2003 UTC (10 years, 8 months ago) by gbeauche
Branch: MAIN
Changes since 1.23: +9 -2 lines
Diff to previous 1.23 , to selected 1.26
Match Linux/ppc native version better: jump to ROM with EmulatorData in r4,
preserve CR & XER registers on EmulOp.


Revision 1.23 - (view) (annotate) - [select for diffs]
Fri Dec 5 13:37:56 2003 UTC (10 years, 9 months ago) by gbeauche
Branch: MAIN
Changes since 1.22: +4 -2 lines
Diff to previous 1.22 , to selected 1.26
Use an alternate stack base while servicing PowerPC interrupts.


Revision 1.22 - (view) (annotate) - [select for diffs]
Thu Dec 4 23:37:38 2003 UTC (10 years, 9 months ago) by gbeauche
Branch: MAIN
Changes since 1.21: +1 -12 lines
Diff to previous 1.21 , to selected 1.26
Use a unique ExecuteNative() interface in any case, i.e. native & emulated


Revision 1.21 - (view) (annotate) - [select for diffs]
Thu Dec 4 17:26:38 2003 UTC (10 years, 9 months ago) by gbeauche
Branch: MAIN
Changes since 1.20: +21 -54 lines
Diff to previous 1.20 , to selected 1.26
Add new thunking system for 64-bit fixes.


Revision 1.20 - (view) (annotate) - [select for diffs]
Wed Dec 3 10:52:49 2003 UTC (10 years, 9 months ago) by gbeauche
Branch: MAIN
Changes since 1.19: +7 -1 lines
Diff to previous 1.19 , to selected 1.26
Add "jit" prefs item. Fix PPC_DECODE_CACHE version to fill in new min_pc &
max_pc members of block info. Increase -finline-limit to 10000 for older gcc


Revision 1.19 - (view) (annotate) - [select for diffs]
Sun Nov 30 17:21:52 2003 UTC (10 years, 9 months ago) by gbeauche
Branch: MAIN
Changes since 1.18: +1 -10 lines
Diff to previous 1.18 , to selected 1.26
better handling of static translation cache allocation, handle nested
execution paths from the cpu core, cleanups for KPX_MAX_CPUS == 1.


Revision 1.18 - (view) (annotate) - [select for diffs]
Mon Nov 24 23:45:41 2003 UTC (10 years, 9 months ago) by gbeauche
Branch: MAIN
Changes since 1.17: +7 -0 lines
Diff to previous 1.17 , to selected 1.26
Merge in-progress PowerPC "JIT1" engine for AMD64, IA-32, PPC.

The merge probably got wrong as there are some problems probably due to the
experiment begining with CR deferred evaluation. With nbench/ppc, performance
improvement was around 2x. With nbench on x86, performance improvement was
around 4x on average.

Incompatible change: instr_info_t has a new field in the middle. But since
insertion of PPC_I(XXX) identifiers is auto-generated, there is no problem.


Revision 1.17 - (view) (annotate) - [select for diffs]
Mon Nov 10 16:23:58 2003 UTC (10 years, 10 months ago) by gbeauche
Branch: MAIN
Changes since 1.16: +36 -3 lines
Diff to previous 1.16 , to selected 1.26
Fix "ignoresegv" case to actually skip the faulty instruction. Merge
conditions to skip instruction on SIGSEGVfrom PowerPC native mode. The
instruction skipper takes care to set the output register to 0.


Revision 1.16 - (view) (annotate) - [select for diffs]
Mon Nov 10 15:11:44 2003 UTC (10 years, 10 months ago) by gbeauche
Branch: MAIN
Changes since 1.15: +41 -11 lines
Diff to previous 1.15 , to selected 1.26
- XLM_IRQ_NEST is always in native byte order format since any write to
  this variable go through {Enable,Disable}Interrupt().
- Add Ether thunks but only for WORDS_BIGENDIAN case since we do need more
complicated translation functions.


Revision 1.15 - (view) (annotate) - [select for diffs]
Tue Nov 4 20:48:29 2003 UTC (10 years, 10 months ago) by gbeauche
Branch: MAIN
Changes since 1.14: +79 -0 lines
Diff to previous 1.14 , to selected 1.26
Add some statistics for interrupt handling, Execute68k/Trap, MacOS & NativeOp


Revision 1.14 - (view) (annotate) - [select for diffs]
Mon Nov 3 21:28:29 2003 UTC (10 years, 10 months ago) by gbeauche
Branch: MAIN
Changes since 1.13: +12 -0 lines
Diff to previous 1.13 , to selected 1.26
Implement partial block cache invalidation. Rewrite core cached blocks
execution loop with a Duff's device. Gather some predecode time statistics.
This shows that only around 2% of total emulation time is spent for
predecoding the instructions.


Revision 1.13 - (view) (annotate) - [select for diffs]
Sun Nov 2 14:48:17 2003 UTC (10 years, 10 months ago) by gbeauche
Branch: MAIN
Changes since 1.12: +1 -1 lines
Diff to previous 1.12 , to selected 1.26
Optimized pointers to non virtual member functions. This reduces space
and overhead since runtime checks are eliminated. Actually, it yields
up to 10% performance improvement with specialized decoders.


Revision 1.12 - (view) (annotate) - [select for diffs]
Sat Nov 1 15:15:27 2003 UTC (10 years, 10 months ago) by gbeauche
Branch: MAIN
Changes since 1.11: +2 -18 lines
Diff to previous 1.11 , to selected 1.26
Integrate spcflags handling code to kpx_cpu core. We can also remove
oldish EXEC_RETURN handling with a throw/catch mechanism since we
do have a dependency on extra conditions (invalidated cache) that
prevents fast execution loops.


Revision 1.11 - (view) (annotate) - [select for diffs]
Sun Oct 26 14:16:39 2003 UTC (10 years, 10 months ago) by gbeauche
Branch: MAIN
Changes since 1.10: +6 -1 lines
Diff to previous 1.10 , to selected 1.26
Fix ASYNC_IRQ build but locks may still happen. Note that with a predecode
cache, checking for pending interrupts may not be the bottle neck nowadays.


Revision 1.10 - (view) (annotate) - [select for diffs]
Sun Oct 26 13:59:03 2003 UTC (10 years, 10 months ago) by gbeauche
Branch: MAIN
Changes since 1.9: +23 -39 lines
Diff to previous 1.9 , to selected 1.26
Rewrite interrupts handling code so that the emulator can work with a
predecode cache. This implies to run in interpreted mode only while
processing EmulOps or other native (nested) runs.

Note that the FLIGHT_RECORDER with a predecode cache gets slower than
without caching at all.


Revision 1.9 - (view) (annotate) - [select for diffs]
Sun Oct 26 09:14:14 2003 UTC (10 years, 10 months ago) by gbeauche
Branch: MAIN
Changes since 1.8: +1 -31 lines
Diff to previous 1.8 , to selected 1.26
- enable multicore cpu emulation with ASYNC_IRQ
- move atomic_* operations to main_unix so that they could use spinlocks or
  other platform-specific locking mechanisms


Revision 1.8 - (view) (annotate) - [select for diffs]
Sun Oct 19 21:37:43 2003 UTC (10 years, 11 months ago) by gbeauche
Branch: MAIN
Changes since 1.7: +5 -3 lines
Diff to previous 1.7 , to selected 1.26
Preserve CR in execute_68k(). This enables MacOS 8.6 to work. ;-)


Revision 1.7 - (view) (annotate) - [select for diffs]
Sun Oct 12 05:44:15 2003 UTC (10 years, 11 months ago) by gbeauche
Branch: MAIN
Changes since 1.6: +14 -1 lines
Diff to previous 1.6 , to selected 1.26
- Handle MakeExecutable() replacement
- Disable predecode cache in CVS for now
- Fix flight recorder ordering in predecode cache mode


Revision 1.6 - (view) (annotate) - [select for diffs]
Sat Oct 11 09:33:27 2003 UTC (10 years, 11 months ago) by gbeauche
Branch: MAIN
Changes since 1.5: +10 -12 lines
Diff to previous 1.5 , to selected 1.26
- Minor optimization to execute_ppc() as we apparently don't need to move
  target PC into CTR.
- Fix breakage introduced during little endian fixing. We now assume that
  MacOS doesn't rely on any PPC register that may have been saved on top
  of it stack. i.e. register state is saved onto native stack.


Revision 1.5 - (view) (annotate) - [select for diffs]
Mon Sep 29 22:50:31 2003 UTC (10 years, 11 months ago) by gbeauche
Branch: MAIN
Changes since 1.4: +19 -15 lines
Diff to previous 1.4 , to selected 1.26
little endian fixes, note that trampolines are still not 64-bit clean either


Revision 1.4 - (view) (annotate) - [select for diffs]
Mon Sep 29 15:46:09 2003 UTC (10 years, 11 months ago) by gbeauche
Branch: MAIN
Changes since 1.3: +16 -29 lines
Diff to previous 1.3 , to selected 1.26
- Share EmulatorData & KernelData struct definitions
- Introduce new SheepShaver data area for alternate stacks, thunks, etc.
- Experimental asynchronous interrupts handling. This improves performance
  by 30% but some (rare) lockups may occur. To be debugged!


Revision 1.3 - (view) (annotate) - [select for diffs]
Mon Sep 29 07:05:15 2003 UTC (10 years, 11 months ago) by gbeauche
Branch: MAIN
Changes since 1.2: +28 -40 lines
Diff to previous 1.2 , to selected 1.26
use B2 sigsegv API instead of rewriting yet another sigsegv handler for x86


Revision 1.2 - (view) (annotate) - [select for diffs]
Sun Sep 28 21:27:34 2003 UTC (10 years, 11 months ago) by gbeauche
Branch: MAIN
Changes since 1.1: +187 -59 lines
Diff to previous 1.1 , to selected 1.26
Try to handle XLM_IRQ_NEST atomically in emulated PPC views. Fix placement
of fake SCSIGlobals (disabled for now). Switch back to mono core emulation
until things are debugged enough. Implement get_resource() et al.


Revision 1.1 - (view) (annotate) - [select for diffs]
Sun Sep 7 14:25:01 2003 UTC (11 years ago) by gbeauche
Branch: MAIN
Diff to selected 1.26
Merge in old kpx_cpu snapshot for debugging


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