ViewVC Help
View File | Revision Log | Show Annotations | Revision Graph | Root Listing
root/cebix/SheepShaver/src/include/cpu_emulation.h
Revision: 1.5
Committed: 2003-10-12T05:44:13Z (20 years, 8 months ago) by gbeauche
Content type: text/plain
Branch: MAIN
Changes since 1.4: +1 -0 lines
Log Message: 
- Handle MakeExecutable() replacement
- Disable predecode cache in CVS for now
- Fix flight recorder ordering in predecode cache mode

File Contents

# User Rev Content
1 cebix 1.1 /*
2     * cpu_emulation.h - Definitions for CPU emulation and Mac memory access
3     *
4     * SheepShaver (C) 1997-2002 Christian Bauer and Marc Hellwig
5     *
6     * This program is free software; you can redistribute it and/or modify
7     * it under the terms of the GNU General Public License as published by
8     * the Free Software Foundation; either version 2 of the License, or
9     * (at your option) any later version.
10     *
11     * This program is distributed in the hope that it will be useful,
12     * but WITHOUT ANY WARRANTY; without even the implied warranty of
13     * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14     * GNU General Public License for more details.
15     *
16     * You should have received a copy of the GNU General Public License
17     * along with this program; if not, write to the Free Software
18     * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19     */
20    
21     #ifndef CPU_EMULATION_H
22     #define CPU_EMULATION_H
23    
24    
25     /*
26     * Memory system
27     */
28    
29     // Constants
30     const uint32 ROM_BASE = 0x40800000; // Base address of ROM
31     const uint32 ROM_SIZE = 0x00400000; // Size of ROM file
32 gbeauche 1.4 const uint32 ROM_AREA_SIZE = 0x500000; // Size of ROM area
33     const uint32 ROM_END = ROM_BASE + ROM_SIZE; // End of ROM
34 cebix 1.1 const uint32 DR_CACHE_BASE = 0x69000000; // Address of DR cache
35     const uint32 DR_CACHE_SIZE = 0x80000; // Size of DR Cache
36 gbeauche 1.4 const uint32 SHEEP_BASE = 0x60000000; // Address of SheepShaver data
37     const uint32 SHEEP_SIZE = 0x40000; // Size of SheepShaver data
38    
39     const uint32 KERNEL_DATA_BASE = 0x68ffe000; // Address of Kernel Data
40     const uint32 KERNEL_DATA2_BASE = 0x5fffe000;// Alternate address of Kernel Data
41     const uint32 KERNEL_AREA_SIZE = 0x2000; // Size of Kernel Data area
42    
43     // MacOS 68k Emulator Data
44     struct EmulatorData {
45     uint32 v[0x400];
46     };
47    
48     // MacOS Kernel Data
49     struct KernelData {
50     uint32 v[0x400];
51     EmulatorData ed;
52     };
53 cebix 1.1
54     // RAM and ROM pointers (allocated and set by main_*.cpp)
55     extern uint32 RAMBase; // Base address of Mac RAM
56     extern uint32 RAMSize; // Size address of Mac RAM
57 gbeauche 1.4 extern uint32 SheepStack1Base; // SheepShaver first alternate stack base
58     extern uint32 SheepStack2Base; // SheepShaver second alternate stack base
59     extern uint32 SheepThunksBase; // SheepShaver thunks base
60 cebix 1.1
61     // Mac memory access functions
62     static inline uint32 ReadMacInt8(uint32 addr) {return *(uint8 *)addr;}
63     static inline void WriteMacInt8(uint32 addr, uint32 b) {*(uint8 *)addr = b;}
64     #ifdef __i386__
65     static inline uint32 ReadMacInt16(uint32 addr) {uint32 retval; __asm__ ("movzwl %w1,%k0\n\tshll $16,%k0\n\tbswapl %k0\n" : "=&r" (retval) : "m" (*(uint16 *)addr) : "cc"); return retval;}
66     static inline uint32 ReadMacInt32(uint32 addr) {uint32 retval; __asm__ ("bswap %0" : "=r" (retval) : "0" (*(uint32 *)addr) : "cc"); return retval;}
67     static inline uint64 ReadMacInt64(uint32 addr) {return ((uint64)ReadMacInt32(addr) << 32) | ReadMacInt32(addr + 4);}
68     static inline void WriteMacInt16(uint32 addr, uint32 w) {__asm__ ("bswapl %0" : "=&r" (w) : "0" (w << 16) : "cc"); *(uint16 *)addr = w;}
69     static inline void WriteMacInt32(uint32 addr, uint32 l) {__asm__ ("bswap %0" : "=r" (l) : "0" (l) : "cc"); *(uint32 *)addr = l;}
70     static inline void WriteMacInt64(uint32 addr, uint64 ll) {WriteMacInt32(addr, ll >> 32); WriteMacInt32(addr, ll);}
71     #else
72     static inline uint32 ReadMacInt16(uint32 addr) {return *(uint16 *)addr;}
73     static inline uint32 ReadMacInt32(uint32 addr) {return *(uint32 *)addr;}
74     static inline uint64 ReadMacInt64(uint32 addr) {return *(uint64 *)addr;}
75     static inline void WriteMacInt16(uint32 addr, uint32 w) {*(uint16 *)addr = w;}
76     static inline void WriteMacInt32(uint32 addr, uint32 l) {*(uint32 *)addr = l;}
77     static inline void WriteMacInt64(uint32 addr, uint64 ll) {*(uint64 *)addr = ll;}
78     #endif
79     static inline uint8 *Mac2HostAddr(uint32 addr) {return (uint8 *)addr;}
80     static inline void *Mac_memset(uint32 addr, int c, size_t n) {return memset(Mac2HostAddr(addr), c, n);}
81     static inline void *Mac2Host_memcpy(void *dest, uint32 src, size_t n) {return memcpy(dest, Mac2HostAddr(src), n);}
82     static inline void *Host2Mac_memcpy(uint32 dest, const void *src, size_t n) {return memcpy(Mac2HostAddr(dest), src, n);}
83     static inline void *Mac2Mac_memcpy(uint32 dest, uint32 src, size_t n) {return memcpy(Mac2HostAddr(dest), Mac2HostAddr(src), n);}
84    
85    
86     /*
87     * 680x0 and PPC emulation
88     */
89    
90     struct M68kRegisters;
91     extern void Execute68k(uint32, M68kRegisters *r); // Execute 68k subroutine from EMUL_OP routine, must be ended with RTS
92     extern void Execute68kTrap(uint16 trap, M68kRegisters *r); // Execute 68k A-Trap from EMUL_OP routine
93 gbeauche 1.2 #if EMULATED_PPC
94 gbeauche 1.5 extern void FlushCodeCache(uintptr start, uintptr end); // Invalidate emulator caches
95 gbeauche 1.2 extern void ExecuteNative(int selector); // Execute native code from EMUL_OP routine (real mode switch)
96     #else
97     extern void ExecutePPC(void (*func)(void)); // Execute PPC code from EMUL_OP routine (real mode switch)
98     #endif
99 cebix 1.1
100     #endif