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root/cebix/SheepShaver/src/rom_patches.cpp
Revision: 1.10
Committed: 2003-09-29T22:49:23Z (20 years, 7 months ago) by gbeauche
Branch: MAIN
Changes since 1.9: +7 -7 lines
Log Message: 
Little endian fixes to Serial trampolines.

File Contents

# User Rev Content
1 cebix 1.1 /*
2     * rom_patches.cpp - ROM patches
3     *
4     * SheepShaver (C) 1997-2002 Christian Bauer and Marc Hellwig
5     *
6     * This program is free software; you can redistribute it and/or modify
7     * it under the terms of the GNU General Public License as published by
8     * the Free Software Foundation; either version 2 of the License, or
9     * (at your option) any later version.
10     *
11     * This program is distributed in the hope that it will be useful,
12     * but WITHOUT ANY WARRANTY; without even the implied warranty of
13     * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14     * GNU General Public License for more details.
15     *
16     * You should have received a copy of the GNU General Public License
17     * along with this program; if not, write to the Free Software
18     * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19     */
20    
21     /*
22     * TODO:
23     * IRQ_NEST must be handled atomically
24     * Don't use r1 in extra routines
25     */
26    
27     #include <string.h>
28    
29     #include "sysdeps.h"
30     #include "rom_patches.h"
31     #include "main.h"
32     #include "prefs.h"
33     #include "cpu_emulation.h"
34     #include "emul_op.h"
35     #include "xlowmem.h"
36     #include "sony.h"
37     #include "disk.h"
38     #include "cdrom.h"
39     #include "audio.h"
40     #include "audio_defs.h"
41     #include "serial.h"
42     #include "macos_util.h"
43    
44     #define DEBUG 0
45     #include "debug.h"
46    
47    
48     // 68k breakpoint address
49     //#define M68K_BREAK_POINT 0x29e0 // BootMe
50     //#define M68K_BREAK_POINT 0x2a1e // Boot block code returned
51     //#define M68K_BREAK_POINT 0x3150 // CritError
52     //#define M68K_BREAK_POINT 0x187ce // Unimplemented trap
53    
54     // PowerPC breakpoint address
55     //#define POWERPC_BREAK_POINT 0x36e6c0 // 68k emulator start
56    
57     #define DISABLE_SCSI 1
58    
59    
60     // Other ROM addresses
61     const uint32 CHECK_LOAD_PATCH_SPACE = 0x2f7f00;
62     const uint32 PUT_SCRAP_PATCH_SPACE = 0x2f7f80;
63     const uint32 GET_SCRAP_PATCH_SPACE = 0x2f7fc0;
64     const uint32 ADDR_MAP_PATCH_SPACE = 0x2f8000;
65    
66     // Global variables
67     int ROMType; // ROM type
68     static uint32 sony_offset; // Offset of .Sony driver resource
69    
70     // Prototypes
71     static bool patch_nanokernel_boot(void);
72     static bool patch_68k_emul(void);
73     static bool patch_nanokernel(void);
74     static bool patch_68k(void);
75    
76    
77 gbeauche 1.2 // Decode LZSS data
78     static void decode_lzss(const uint8 *src, uint8 *dest, int size)
79     {
80     char dict[0x1000];
81     int run_mask = 0, dict_idx = 0xfee;
82     for (;;) {
83     if (run_mask < 0x100) {
84     // Start new run
85     if (--size < 0)
86     break;
87     run_mask = *src++ | 0xff00;
88     }
89     bool bit = run_mask & 1;
90     run_mask >>= 1;
91     if (bit) {
92     // Verbatim copy
93     if (--size < 0)
94     break;
95     int c = *src++;
96     dict[dict_idx++] = c;
97     *dest++ = c;
98     dict_idx &= 0xfff;
99     } else {
100     // Copy from dictionary
101     if (--size < 0)
102     break;
103     int idx = *src++;
104     if (--size < 0)
105     break;
106     int cnt = *src++;
107     idx |= (cnt << 4) & 0xf00;
108     cnt = (cnt & 0x0f) + 3;
109     while (cnt--) {
110     char c = dict[idx++];
111     dict[dict_idx++] = c;
112     *dest++ = c;
113     idx &= 0xfff;
114     dict_idx &= 0xfff;
115     }
116     }
117     }
118     }
119    
120     // Decode parcels of ROM image (MacOS 9.X and even earlier)
121     void decode_parcels(const uint8 *src, uint8 *dest, int size)
122     {
123     uint32 parcel_offset = 0x14;
124     D(bug("Offset Type Name\n"));
125     while (parcel_offset != 0) {
126     const uint32 *parcel_data = (uint32 *)(src + parcel_offset);
127 gbeauche 1.3 uint32 next_offset = ntohl(parcel_data[0]);
128 gbeauche 1.2 uint32 parcel_type = ntohl(parcel_data[1]);
129     D(bug("%08x %c%c%c%c %s\n", parcel_offset,
130     (parcel_type >> 24) & 0xff, (parcel_type >> 16) & 0xff,
131     (parcel_type >> 8) & 0xff, parcel_type & 0xff, &parcel_data[6]));
132     if (parcel_type == FOURCC('r','o','m',' ')) {
133     uint32 lzss_offset = ntohl(parcel_data[2]);
134     uint32 lzss_size = ((uint32)src + parcel_offset) - ((uint32)parcel_data + lzss_offset);
135     decode_lzss((uint8 *)parcel_data + lzss_offset, dest, lzss_size);
136     }
137 gbeauche 1.3 parcel_offset = next_offset;
138 gbeauche 1.2 }
139     }
140    
141    
142     /*
143     * Decode ROM image, 4 MB plain images or NewWorld images
144     */
145    
146     bool DecodeROM(uint8 *data, uint32 size)
147     {
148     if (size == ROM_SIZE) {
149     // Plain ROM image
150     memcpy((void *)ROM_BASE, data, ROM_SIZE);
151     return true;
152     }
153     else if (strncmp((char *)data, "<CHRP-BOOT>", 11) == 0) {
154     // CHRP compressed ROM image
155     uint32 image_offset, image_size;
156     bool decode_info_ok = false;
157    
158     char *s = strstr((char *)data, "constant lzss-offset");
159     if (s != NULL) {
160     // Probably a plain LZSS compressed ROM image
161     if (sscanf(s - 7, "%06x", &image_offset) == 1) {
162     s = strstr((char *)data, "constant lzss-size");
163     if (s != NULL && (sscanf(s - 7, "%06x", &image_size) == 1))
164     decode_info_ok = true;
165     }
166     }
167     else {
168     // Probably a MacOS 9.2.x ROM image
169     s = strstr((char *)data, "constant parcels-offset");
170     if (s != NULL) {
171     if (sscanf(s - 7, "%06x", &image_offset) == 1) {
172     s = strstr((char *)data, "constant parcels-size");
173     if (s != NULL && (sscanf(s - 7, "%06x", &image_size) == 1))
174     decode_info_ok = true;
175     }
176     }
177     }
178    
179     // No valid information to decode the ROM found?
180     if (!decode_info_ok)
181     return false;
182    
183     // Check signature, this could be a parcels-based ROM image
184     uint32 rom_signature = ntohl(*(uint32 *)(data + image_offset));
185     if (rom_signature == FOURCC('p','r','c','l')) {
186     D(bug("Offset of parcels data: %08x\n", image_offset));
187     D(bug("Size of parcels data: %08x\n", image_size));
188     decode_parcels(data + image_offset, (uint8 *)ROM_BASE, image_size);
189     }
190     else {
191     D(bug("Offset of compressed data: %08x\n", image_offset));
192     D(bug("Size of compressed data: %08x\n", image_size));
193     decode_lzss(data + image_offset, (uint8 *)ROM_BASE, image_size);
194     }
195     return true;
196     }
197     return false;
198     }
199    
200    
201 cebix 1.1 /*
202     * Search ROM for byte string, return ROM offset (or 0)
203     */
204    
205     static uint32 find_rom_data(uint32 start, uint32 end, const uint8 *data, uint32 data_len)
206     {
207     uint32 ofs = start;
208     while (ofs < end) {
209     if (!memcmp((void *)(ROM_BASE + ofs), data, data_len))
210     return ofs;
211     ofs++;
212     }
213     return 0;
214     }
215    
216    
217     /*
218     * Search ROM resource by type/ID, return ROM offset of resource data
219     */
220    
221     static uint32 rsrc_ptr = 0;
222    
223     // id = 4711 means "find any ID"
224     static uint32 find_rom_resource(uint32 s_type, int16 s_id = 4711, bool cont = false)
225     {
226     uint32 *lp = (uint32 *)(ROM_BASE + 0x1a);
227     uint32 x = ntohl(*lp);
228     uint8 *bp = (uint8 *)(ROM_BASE + x + 5);
229     uint32 header_size = *bp;
230    
231     if (!cont)
232     rsrc_ptr = x;
233     else if (rsrc_ptr == 0)
234     return 0;
235    
236     for (;;) {
237     lp = (uint32 *)(ROM_BASE + rsrc_ptr);
238     rsrc_ptr = ntohl(*lp);
239     if (rsrc_ptr == 0)
240     break;
241    
242     rsrc_ptr += header_size;
243    
244     lp = (uint32 *)(ROM_BASE + rsrc_ptr + 4);
245     uint32 data = ntohl(*lp); lp++;
246     uint32 type = ntohl(*lp); lp++;
247     int16 id = ntohs(*(int16 *)lp);
248     if (type == s_type && (id == s_id || s_id == 4711))
249     return data;
250     }
251     return 0;
252     }
253    
254    
255     /*
256     * Search offset of A-Trap routine in ROM
257     */
258    
259     static uint32 find_rom_trap(uint16 trap)
260     {
261     uint32 *lp = (uint32 *)(ROM_BASE + 0x22);
262     lp = (uint32 *)(ROM_BASE + ntohl(*lp));
263    
264     if (trap > 0xa800)
265     return ntohl(lp[trap & 0x3ff]);
266     else
267     return ntohl(lp[(trap & 0xff) + 0x400]);
268     }
269    
270    
271     /*
272     * List of audio sifters installed in ROM and System file
273     */
274    
275     struct sift_entry {
276     uint32 type;
277     int16 id;
278     };
279     static sift_entry sifter_list[32];
280     static int num_sifters;
281    
282     void AddSifter(uint32 type, int16 id)
283     {
284     if (FindSifter(type, id))
285     return;
286     D(bug(" adding sifter type %c%c%c%c (%08x), id %d\n", type >> 24, (type >> 16) & 0xff, (type >> 8) & 0xff, type & 0xff, type, id));
287     sifter_list[num_sifters].type = type;
288     sifter_list[num_sifters].id = id;
289     num_sifters++;
290     }
291    
292     bool FindSifter(uint32 type, int16 id)
293     {
294     for (int i=0; i<num_sifters; i++) {
295     if (sifter_list[i].type == type && sifter_list[i].id == id)
296     return true;
297     }
298     return false;
299     }
300    
301    
302     /*
303     * Driver stubs
304     */
305    
306     static const uint8 sony_driver[] = { // Replacement for .Sony driver
307     // Driver header
308     SonyDriverFlags >> 8, SonyDriverFlags & 0xff, 0, 0, 0, 0, 0, 0,
309     0x00, 0x18, // Open() offset
310     0x00, 0x1c, // Prime() offset
311     0x00, 0x20, // Control() offset
312     0x00, 0x2c, // Status() offset
313     0x00, 0x52, // Close() offset
314     0x05, 0x2e, 0x53, 0x6f, 0x6e, 0x79, // ".Sony"
315    
316     // Open()
317     M68K_EMUL_OP_SONY_OPEN >> 8, M68K_EMUL_OP_SONY_OPEN & 0xff,
318     0x4e, 0x75, // rts
319    
320     // Prime()
321     M68K_EMUL_OP_SONY_PRIME >> 8, M68K_EMUL_OP_SONY_PRIME & 0xff,
322     0x60, 0x0e, // bra IOReturn
323    
324     // Control()
325     M68K_EMUL_OP_SONY_CONTROL >> 8, M68K_EMUL_OP_SONY_CONTROL & 0xff,
326     0x0c, 0x68, 0x00, 0x01, 0x00, 0x1a, // cmp.w #1,$1a(a0)
327     0x66, 0x04, // bne IOReturn
328     0x4e, 0x75, // rts
329    
330     // Status()
331     M68K_EMUL_OP_SONY_STATUS >> 8, M68K_EMUL_OP_SONY_STATUS & 0xff,
332    
333     // IOReturn
334     0x32, 0x28, 0x00, 0x06, // move.w 6(a0),d1
335     0x08, 0x01, 0x00, 0x09, // btst #9,d1
336     0x67, 0x0c, // beq 1
337     0x4a, 0x40, // tst.w d0
338     0x6f, 0x02, // ble 2
339     0x42, 0x40, // clr.w d0
340     0x31, 0x40, 0x00, 0x10, //2 move.w d0,$10(a0)
341     0x4e, 0x75, // rts
342     0x4a, 0x40, //1 tst.w d0
343     0x6f, 0x04, // ble 3
344     0x42, 0x40, // clr.w d0
345     0x4e, 0x75, // rts
346     0x2f, 0x38, 0x08, 0xfc, //3 move.l $8fc,-(sp)
347     0x4e, 0x75, // rts
348    
349     // Close()
350     0x70, 0xe8, // moveq #-24,d0
351     0x4e, 0x75 // rts
352     };
353    
354     static const uint8 disk_driver[] = { // Generic disk driver
355     // Driver header
356     DiskDriverFlags >> 8, DiskDriverFlags & 0xff, 0, 0, 0, 0, 0, 0,
357     0x00, 0x18, // Open() offset
358     0x00, 0x1c, // Prime() offset
359     0x00, 0x20, // Control() offset
360     0x00, 0x2c, // Status() offset
361     0x00, 0x52, // Close() offset
362     0x05, 0x2e, 0x44, 0x69, 0x73, 0x6b, // ".Disk"
363    
364     // Open()
365     M68K_EMUL_OP_DISK_OPEN >> 8, M68K_EMUL_OP_DISK_OPEN & 0xff,
366     0x4e, 0x75, // rts
367    
368     // Prime()
369     M68K_EMUL_OP_DISK_PRIME >> 8, M68K_EMUL_OP_DISK_PRIME & 0xff,
370     0x60, 0x0e, // bra IOReturn
371    
372     // Control()
373     M68K_EMUL_OP_DISK_CONTROL >> 8, M68K_EMUL_OP_DISK_CONTROL & 0xff,
374     0x0c, 0x68, 0x00, 0x01, 0x00, 0x1a, // cmp.w #1,$1a(a0)
375     0x66, 0x04, // bne IOReturn
376     0x4e, 0x75, // rts
377    
378     // Status()
379     M68K_EMUL_OP_DISK_STATUS >> 8, M68K_EMUL_OP_DISK_STATUS & 0xff,
380    
381     // IOReturn
382     0x32, 0x28, 0x00, 0x06, // move.w 6(a0),d1
383     0x08, 0x01, 0x00, 0x09, // btst #9,d1
384     0x67, 0x0c, // beq 1
385     0x4a, 0x40, // tst.w d0
386     0x6f, 0x02, // ble 2
387     0x42, 0x40, // clr.w d0
388     0x31, 0x40, 0x00, 0x10, //2 move.w d0,$10(a0)
389     0x4e, 0x75, // rts
390     0x4a, 0x40, //1 tst.w d0
391     0x6f, 0x04, // ble 3
392     0x42, 0x40, // clr.w d0
393     0x4e, 0x75, // rts
394     0x2f, 0x38, 0x08, 0xfc, //3 move.l $8fc,-(sp)
395     0x4e, 0x75, // rts
396    
397     // Close()
398     0x70, 0xe8, // moveq #-24,d0
399     0x4e, 0x75 // rts
400     };
401    
402     static const uint8 cdrom_driver[] = { // CD-ROM driver
403     // Driver header
404     CDROMDriverFlags >> 8, CDROMDriverFlags & 0xff, 0, 0, 0, 0, 0, 0,
405     0x00, 0x1c, // Open() offset
406     0x00, 0x20, // Prime() offset
407     0x00, 0x24, // Control() offset
408     0x00, 0x30, // Status() offset
409     0x00, 0x56, // Close() offset
410     0x08, 0x2e, 0x41, 0x70, 0x70, 0x6c, 0x65, 0x43, 0x44, 0x00, // ".AppleCD"
411    
412     // Open()
413     M68K_EMUL_OP_CDROM_OPEN >> 8, M68K_EMUL_OP_CDROM_OPEN & 0xff,
414     0x4e, 0x75, // rts
415    
416     // Prime()
417     M68K_EMUL_OP_CDROM_PRIME >> 8, M68K_EMUL_OP_CDROM_PRIME & 0xff,
418     0x60, 0x0e, // bra IOReturn
419    
420     // Control()
421     M68K_EMUL_OP_CDROM_CONTROL >> 8, M68K_EMUL_OP_CDROM_CONTROL & 0xff,
422     0x0c, 0x68, 0x00, 0x01, 0x00, 0x1a, // cmp.w #1,$1a(a0)
423     0x66, 0x04, // bne IOReturn
424     0x4e, 0x75, // rts
425    
426     // Status()
427     M68K_EMUL_OP_CDROM_STATUS >> 8, M68K_EMUL_OP_CDROM_STATUS & 0xff,
428    
429     // IOReturn
430     0x32, 0x28, 0x00, 0x06, // move.w 6(a0),d1
431     0x08, 0x01, 0x00, 0x09, // btst #9,d1
432     0x67, 0x0c, // beq 1
433     0x4a, 0x40, // tst.w d0
434     0x6f, 0x02, // ble 2
435     0x42, 0x40, // clr.w d0
436     0x31, 0x40, 0x00, 0x10, //2 move.w d0,$10(a0)
437     0x4e, 0x75, // rts
438     0x4a, 0x40, //1 tst.w d0
439     0x6f, 0x04, // ble 3
440     0x42, 0x40, // clr.w d0
441     0x4e, 0x75, // rts
442     0x2f, 0x38, 0x08, 0xfc, //3 move.l $8fc,-(sp)
443     0x4e, 0x75, // rts
444    
445     // Close()
446     0x70, 0xe8, // moveq #-24,d0
447     0x4e, 0x75 // rts
448     };
449    
450 gbeauche 1.7 #if EMULATED_PPC
451     #define SERIAL_TRAMPOLINES 1
452 gbeauche 1.10 static uint32 serial_nothing_tvect[2] = {tswap32(POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_NOTHING)), 0};
453     static uint32 serial_open_tvect[2] = {tswap32(POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_OPEN)), 0};
454     static uint32 serial_prime_in_tvect[2] = {tswap32(POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_PRIME_IN)), 0};
455     static uint32 serial_prime_out_tvect[2] = {tswap32(POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_PRIME_OUT)), 0};
456     static uint32 serial_control_tvect[2] = {tswap32(POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_CONTROL)), 0};
457     static uint32 serial_status_tvect[2] = {tswap32(POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_STATUS)), 0};
458     static uint32 serial_close_tvect[2] = {tswap32(POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_CLOSE)), 0};
459 gbeauche 1.7 #elif defined(__linux__)
460     #define SERIAL_TRAMPOLINES 1
461 cebix 1.1 static uint32 serial_nothing_tvect[2] = {(uint32)SerialNothing, 0};
462     static uint32 serial_open_tvect[2] = {(uint32)SerialOpen, 0};
463     static uint32 serial_prime_in_tvect[2] = {(uint32)SerialPrimeIn, 0};
464     static uint32 serial_prime_out_tvect[2] = {(uint32)SerialPrimeOut, 0};
465     static uint32 serial_control_tvect[2] = {(uint32)SerialControl, 0};
466     static uint32 serial_status_tvect[2] = {(uint32)SerialStatus, 0};
467     static uint32 serial_close_tvect[2] = {(uint32)SerialClose, 0};
468     #endif
469    
470     static const uint32 ain_driver[] = { // .AIn driver header
471     0x4d000000, 0x00000000,
472     0x00200040, 0x00600080,
473     0x00a0042e, 0x41496e00,
474     0x00000000, 0x00000000,
475     0xaafe0700, 0x00000000,
476     0x00000000, 0x00179822,
477 gbeauche 1.7 #ifdef SERIAL_TRAMPOLINES
478 cebix 1.1 0x00010004, (uint32)serial_nothing_tvect,
479     #else
480     0x00010004, (uint32)SerialNothing,
481     #endif
482     0x00000000, 0x00000000,
483     0xaafe0700, 0x00000000,
484     0x00000000, 0x00179822,
485 gbeauche 1.7 #ifdef SERIAL_TRAMPOLINES
486 cebix 1.1 0x00010004, (uint32)serial_prime_in_tvect,
487     #else
488     0x00010004, (uint32)SerialPrimeIn,
489     #endif
490     0x00000000, 0x00000000,
491     0xaafe0700, 0x00000000,
492     0x00000000, 0x00179822,
493 gbeauche 1.7 #ifdef SERIAL_TRAMPOLINES
494 cebix 1.1 0x00010004, (uint32)serial_control_tvect,
495     #else
496     0x00010004, (uint32)SerialControl,
497     #endif
498     0x00000000, 0x00000000,
499     0xaafe0700, 0x00000000,
500     0x00000000, 0x00179822,
501 gbeauche 1.7 #ifdef SERIAL_TRAMPOLINES
502 cebix 1.1 0x00010004, (uint32)serial_status_tvect,
503     #else
504     0x00010004, (uint32)SerialStatus,
505     #endif
506     0x00000000, 0x00000000,
507     0xaafe0700, 0x00000000,
508     0x00000000, 0x00179822,
509 gbeauche 1.7 #ifdef SERIAL_TRAMPOLINES
510 cebix 1.1 0x00010004, (uint32)serial_nothing_tvect,
511     #else
512     0x00010004, (uint32)SerialNothing,
513     #endif
514     0x00000000, 0x00000000,
515     };
516    
517     static const uint32 aout_driver[] = { // .AOut driver header
518     0x4d000000, 0x00000000,
519     0x00200040, 0x00600080,
520     0x00a0052e, 0x414f7574,
521     0x00000000, 0x00000000,
522     0xaafe0700, 0x00000000,
523     0x00000000, 0x00179822,
524 gbeauche 1.7 #ifdef SERIAL_TRAMPOLINES
525 cebix 1.1 0x00010004, (uint32)serial_open_tvect,
526     #else
527     0x00010004, (uint32)SerialOpen,
528     #endif
529     0x00000000, 0x00000000,
530     0xaafe0700, 0x00000000,
531     0x00000000, 0x00179822,
532 gbeauche 1.7 #ifdef SERIAL_TRAMPOLINES
533 cebix 1.1 0x00010004, (uint32)serial_prime_out_tvect,
534     #else
535     0x00010004, (uint32)SerialPrimeOut,
536     #endif
537     0x00000000, 0x00000000,
538     0xaafe0700, 0x00000000,
539     0x00000000, 0x00179822,
540 gbeauche 1.7 #ifdef SERIAL_TRAMPOLINES
541 cebix 1.1 0x00010004, (uint32)serial_control_tvect,
542     #else
543     0x00010004, (uint32)SerialControl,
544     #endif
545     0x00000000, 0x00000000,
546     0xaafe0700, 0x00000000,
547     0x00000000, 0x00179822,
548 gbeauche 1.7 #ifdef SERIAL_TRAMPOLINES
549 cebix 1.1 0x00010004, (uint32)serial_status_tvect,
550     #else
551     0x00010004, (uint32)SerialStatus,
552     #endif
553     0x00000000, 0x00000000,
554     0xaafe0700, 0x00000000,
555     0x00000000, 0x00179822,
556 gbeauche 1.7 #ifdef SERIAL_TRAMPOLINES
557 cebix 1.1 0x00010004, (uint32)serial_close_tvect,
558     #else
559     0x00010004, (uint32)SerialClose,
560     #endif
561     0x00000000, 0x00000000,
562     };
563    
564     static const uint32 bin_driver[] = { // .BIn driver header
565     0x4d000000, 0x00000000,
566     0x00200040, 0x00600080,
567     0x00a0042e, 0x42496e00,
568     0x00000000, 0x00000000,
569     0xaafe0700, 0x00000000,
570     0x00000000, 0x00179822,
571 gbeauche 1.7 #ifdef SERIAL_TRAMPOLINES
572 cebix 1.1 0x00010004, (uint32)serial_nothing_tvect,
573     #else
574     0x00010004, (uint32)SerialNothing,
575     #endif
576     0x00000000, 0x00000000,
577     0xaafe0700, 0x00000000,
578     0x00000000, 0x00179822,
579 gbeauche 1.7 #ifdef SERIAL_TRAMPOLINES
580 cebix 1.1 0x00010004, (uint32)serial_prime_in_tvect,
581     #else
582     0x00010004, (uint32)SerialPrimeIn,
583     #endif
584     0x00000000, 0x00000000,
585     0xaafe0700, 0x00000000,
586     0x00000000, 0x00179822,
587 gbeauche 1.7 #ifdef SERIAL_TRAMPOLINES
588 cebix 1.1 0x00010004, (uint32)serial_control_tvect,
589     #else
590     0x00010004, (uint32)SerialControl,
591     #endif
592     0x00000000, 0x00000000,
593     0xaafe0700, 0x00000000,
594     0x00000000, 0x00179822,
595 gbeauche 1.7 #ifdef SERIAL_TRAMPOLINES
596 cebix 1.1 0x00010004, (uint32)serial_status_tvect,
597     #else
598     0x00010004, (uint32)SerialStatus,
599     #endif
600     0x00000000, 0x00000000,
601     0xaafe0700, 0x00000000,
602     0x00000000, 0x00179822,
603 gbeauche 1.7 #ifdef SERIAL_TRAMPOLINES
604 cebix 1.1 0x00010004, (uint32)serial_nothing_tvect,
605     #else
606     0x00010004, (uint32)SerialNothing,
607     #endif
608     0x00000000, 0x00000000,
609     };
610    
611     static const uint32 bout_driver[] = { // .BOut driver header
612     0x4d000000, 0x00000000,
613     0x00200040, 0x00600080,
614     0x00a0052e, 0x424f7574,
615     0x00000000, 0x00000000,
616     0xaafe0700, 0x00000000,
617     0x00000000, 0x00179822,
618 gbeauche 1.7 #ifdef SERIAL_TRAMPOLINES
619 cebix 1.1 0x00010004, (uint32)serial_open_tvect,
620     #else
621     0x00010004, (uint32)SerialOpen,
622     #endif
623     0x00000000, 0x00000000,
624     0xaafe0700, 0x00000000,
625     0x00000000, 0x00179822,
626 gbeauche 1.7 #ifdef SERIAL_TRAMPOLINES
627 cebix 1.1 0x00010004, (uint32)serial_prime_out_tvect,
628     #else
629     0x00010004, (uint32)SerialPrimeOut,
630     #endif
631     0x00000000, 0x00000000,
632     0xaafe0700, 0x00000000,
633     0x00000000, 0x00179822,
634 gbeauche 1.7 #ifdef SERIAL_TRAMPOLINES
635 cebix 1.1 0x00010004, (uint32)serial_control_tvect,
636     #else
637     0x00010004, (uint32)SerialControl,
638     #endif
639     0x00000000, 0x00000000,
640     0xaafe0700, 0x00000000,
641     0x00000000, 0x00179822,
642 gbeauche 1.7 #ifdef SERIAL_TRAMPOLINES
643 cebix 1.1 0x00010004, (uint32)serial_status_tvect,
644     #else
645     0x00010004, (uint32)SerialStatus,
646     #endif
647     0x00000000, 0x00000000,
648     0xaafe0700, 0x00000000,
649     0x00000000, 0x00179822,
650 gbeauche 1.7 #ifdef SERIAL_TRAMPOLINES
651 cebix 1.1 0x00010004, (uint32)serial_close_tvect,
652     #else
653     0x00010004, (uint32)SerialClose,
654     #endif
655     0x00000000, 0x00000000,
656     };
657    
658     static const uint8 adbop_patch[] = { // Call ADBOp() completion procedure
659     // The completion procedure may call ADBOp() again!
660     0x40, 0xe7, // move sr,-(sp)
661     0x00, 0x7c, 0x07, 0x00, // ori #$0700,sr
662     M68K_EMUL_OP_ADBOP >> 8, M68K_EMUL_OP_ADBOP & 0xff,
663     0x48, 0xe7, 0x70, 0xf0, // movem.l d1-d3/a0-a3,-(sp)
664     0x26, 0x48, // move.l a0,a3
665     0x4a, 0xab, 0x00, 0x04, // tst.l 4(a3)
666     0x67, 0x00, 0x00, 0x18, // beq 1
667     0x20, 0x53, // move.l (a3),a0
668     0x22, 0x6b, 0x00, 0x04, // move.l 4(a3),a1
669     0x24, 0x6b, 0x00, 0x08, // move.l 8(a3),a2
670     0x26, 0x78, 0x0c, 0xf8, // move.l $cf8,a3
671     0x4e, 0x91, // jsr (a1)
672     0x70, 0x00, // moveq #0,d0
673     0x60, 0x00, 0x00, 0x04, // bra 2
674     0x70, 0xff, //1 moveq #-1,d0
675     0x4c, 0xdf, 0x0f, 0x0e, //2 movem.l (sp)+,d1-d3/a0-a3
676     0x46, 0xdf, // move (sp)+,sr
677     0x4e, 0x75 // rts
678     };
679    
680    
681     /*
682 gbeauche 1.9 * Copy PowerPC code to ROM image and reverse bytes if necessary
683     */
684    
685     static inline void memcpy_powerpc_code(void *dst, const void *src, size_t len)
686     {
687     #ifdef WORDS_BIGENDIAN
688     (void)memcpy(dst, src, len);
689     #else
690     uint32 *d = (uint32 *)dst;
691     uint32 *s = (uint32 *)src;
692     for (int i = 0; i < len/4; i++)
693     d[i] = htonl(s[i]);
694     #endif
695     }
696    
697    
698     /*
699 cebix 1.1 * Install ROM patches (RAMBase and KernelDataAddr must be set)
700     */
701    
702     bool PatchROM(void)
703     {
704     // Print ROM info
705     D(bug("Checksum: %08lx\n", ntohl(*(uint32 *)ROM_BASE)));
706     D(bug("Version: %04x\n", ntohs(*(uint16 *)(ROM_BASE + 8))));
707     D(bug("Sub Version: %04x\n", ntohs(*(uint16 *)(ROM_BASE + 18))));
708     D(bug("Nanokernel ID: %s\n", (char *)ROM_BASE + 0x30d064));
709     D(bug("Resource Map at %08lx\n", ntohl(*(uint32 *)(ROM_BASE + 26))));
710     D(bug("Trap Tables at %08lx\n\n", ntohl(*(uint32 *)(ROM_BASE + 34))));
711    
712     // Detect ROM type
713     if (!memcmp((void *)(ROM_BASE + 0x30d064), "Boot TNT", 8))
714     ROMType = ROMTYPE_TNT;
715     else if (!memcmp((void *)(ROM_BASE + 0x30d064), "Boot Alchemy", 12))
716     ROMType = ROMTYPE_ALCHEMY;
717     else if (!memcmp((void *)(ROM_BASE + 0x30d064), "Boot Zanzibar", 13))
718     ROMType = ROMTYPE_ZANZIBAR;
719     else if (!memcmp((void *)(ROM_BASE + 0x30d064), "Boot Gazelle", 12))
720     ROMType = ROMTYPE_GAZELLE;
721     else if (!memcmp((void *)(ROM_BASE + 0x30d064), "NewWorld", 8))
722     ROMType = ROMTYPE_NEWWORLD;
723     else
724     return false;
725    
726     // Apply patches
727     if (!patch_nanokernel_boot()) return false;
728     if (!patch_68k_emul()) return false;
729     if (!patch_nanokernel()) return false;
730     if (!patch_68k()) return false;
731    
732     #ifdef M68K_BREAK_POINT
733     // Install 68k breakpoint
734     uint16 *wp = (uint16 *)(ROM_BASE + M68K_BREAK_POINT);
735     *wp++ = htons(M68K_EMUL_BREAK);
736     *wp = htons(M68K_EMUL_RETURN);
737     #endif
738    
739     #ifdef POWERPC_BREAK_POINT
740     // Install PowerPC breakpoint
741     uint32 *lp = (uint32 *)(ROM_BASE + POWERPC_BREAK_POINT);
742     *lp = htonl(0);
743     #endif
744    
745     // Copy 68k emulator to 2MB boundary
746     memcpy((void *)(ROM_BASE + ROM_SIZE), (void *)(ROM_BASE + ROM_SIZE - 0x100000), 0x100000);
747     return true;
748     }
749    
750    
751     /*
752     * Nanokernel boot routine patches
753     */
754    
755     static bool patch_nanokernel_boot(void)
756     {
757     uint32 *lp;
758    
759     // ROM boot structure patches
760     lp = (uint32 *)(ROM_BASE + 0x30d000);
761     lp[0x9c >> 2] = htonl(KernelDataAddr); // LA_InfoRecord
762     lp[0xa0 >> 2] = htonl(KernelDataAddr); // LA_KernelData
763     lp[0xa4 >> 2] = htonl(KernelDataAddr + 0x1000); // LA_EmulatorData
764     lp[0xa8 >> 2] = htonl(ROM_BASE + 0x480000); // LA_DispatchTable
765     lp[0xac >> 2] = htonl(ROM_BASE + 0x460000); // LA_EmulatorCode
766     lp[0x360 >> 2] = htonl(0); // Physical RAM base (? on NewWorld ROM, this contains -1)
767     lp[0xfd8 >> 2] = htonl(ROM_BASE + 0x2a); // 68k reset vector
768    
769     // Skip SR/BAT/SDR init
770     if (ROMType == ROMTYPE_GAZELLE || ROMType == ROMTYPE_NEWWORLD) {
771     lp = (uint32 *)(ROM_BASE + 0x310000);
772     *lp++ = htonl(POWERPC_NOP);
773     *lp = htonl(0x38000000);
774     }
775     static const uint32 sr_init_loc[] = {0x3101b0, 0x3101b0, 0x3101b0, 0x3101ec, 0x310200};
776     lp = (uint32 *)(ROM_BASE + 0x310008);
777     *lp = htonl(0x48000000 | (sr_init_loc[ROMType] - 8) & 0xffff); // b ROM_BASE+0x3101b0
778     lp = (uint32 *)(ROM_BASE + sr_init_loc[ROMType]);
779     *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA); // lwz r1,(pointer to Kernel Data)
780     *lp++ = htonl(0x3da0dead); // lis r13,0xdead (start of kernel memory)
781     *lp++ = htonl(0x3dc00010); // lis r14,0x0010 (size of page table)
782     *lp = htonl(0x3de00010); // lis r15,0x0010 (size of kernel memory)
783    
784     // Don't read PVR
785     static const uint32 pvr_loc[] = {0x3103b0, 0x3103b4, 0x3103b4, 0x310400, 0x310438};
786     lp = (uint32 *)(ROM_BASE + pvr_loc[ROMType]);
787     *lp = htonl(0x81800000 + XLM_PVR); // lwz r12,(theoretical PVR)
788    
789     // Set CPU specific data (even if ROM doesn't have support for that CPU)
790     lp = (uint32 *)(ROM_BASE + pvr_loc[ROMType]);
791     if (ntohl(lp[6]) != 0x2c0c0001)
792     return false;
793     uint32 ofs = ntohl(lp[7]) & 0xffff;
794     D(bug("ofs %08lx\n", ofs));
795     lp[8] = htonl((ntohl(lp[8]) & 0xffff) | 0x48000000); // beq -> b
796     uint32 loc = (ntohl(lp[8]) & 0xffff) + (uint32)(lp+8) - ROM_BASE;
797     D(bug("loc %08lx\n", loc));
798     lp = (uint32 *)(ROM_BASE + ofs + 0x310000);
799     switch (PVR >> 16) {
800     case 1: // 601
801     lp[0] = htonl(0x1000); // Page size
802     lp[1] = htonl(0x8000); // Data cache size
803     lp[2] = htonl(0x8000); // Inst cache size
804     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
805     lp[4] = htonl(0x00010040); // Unified caches/Inst cache line size
806     lp[5] = htonl(0x00400020); // Data cache line size/Data cache block size touch
807     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
808     lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc
809     lp[8] = htonl(0x01000002); // TLB total size/TLB assoc
810     break;
811     case 3: // 603
812     lp[0] = htonl(0x1000); // Page size
813     lp[1] = htonl(0x2000); // Data cache size
814     lp[2] = htonl(0x2000); // Inst cache size
815     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
816     lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
817     lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
818     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
819     lp[7] = htonl(0x00020002); // Inst cache assoc/Data cache assoc
820     lp[8] = htonl(0x00400002); // TLB total size/TLB assoc
821     break;
822     case 4: // 604
823     lp[0] = htonl(0x1000); // Page size
824     lp[1] = htonl(0x4000); // Data cache size
825     lp[2] = htonl(0x4000); // Inst cache size
826     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
827     lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
828     lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
829     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
830     lp[7] = htonl(0x00040004); // Inst cache assoc/Data cache assoc
831     lp[8] = htonl(0x00800002); // TLB total size/TLB assoc
832     break;
833     // case 5: // 740?
834     case 6: // 603e
835     case 7: // 603ev
836     lp[0] = htonl(0x1000); // Page size
837     lp[1] = htonl(0x4000); // Data cache size
838     lp[2] = htonl(0x4000); // Inst cache size
839     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
840     lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
841     lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
842     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
843     lp[7] = htonl(0x00040004); // Inst cache assoc/Data cache assoc
844     lp[8] = htonl(0x00400002); // TLB total size/TLB assoc
845     break;
846     case 8: // 750
847     lp[0] = htonl(0x1000); // Page size
848     lp[1] = htonl(0x8000); // Data cache size
849     lp[2] = htonl(0x8000); // Inst cache size
850     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
851     lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
852     lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
853     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
854     lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc
855     lp[8] = htonl(0x00800002); // TLB total size/TLB assoc
856     break;
857     case 9: // 604e
858     case 10: // 604ev5
859     lp[0] = htonl(0x1000); // Page size
860     lp[1] = htonl(0x8000); // Data cache size
861     lp[2] = htonl(0x8000); // Inst cache size
862     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
863     lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
864     lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
865     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
866     lp[7] = htonl(0x00040004); // Inst cache assoc/Data cache assoc
867     lp[8] = htonl(0x00800002); // TLB total size/TLB assoc
868     break;
869     // case 11: // X704?
870     case 12: // ???
871     lp[0] = htonl(0x1000); // Page size
872     lp[1] = htonl(0x8000); // Data cache size
873     lp[2] = htonl(0x8000); // Inst cache size
874     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
875     lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
876     lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
877     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
878     lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc
879     lp[8] = htonl(0x00800002); // TLB total size/TLB assoc
880     break;
881     case 13: // ???
882     lp[0] = htonl(0x1000); // Page size
883     lp[1] = htonl(0x8000); // Data cache size
884     lp[2] = htonl(0x8000); // Inst cache size
885     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
886     lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
887     lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
888     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
889     lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc
890     lp[8] = htonl(0x01000004); // TLB total size/TLB assoc
891     break;
892     // case 50: // 821
893     // case 80: // 860
894     case 96: // ???
895     lp[0] = htonl(0x1000); // Page size
896     lp[1] = htonl(0x8000); // Data cache size
897     lp[2] = htonl(0x8000); // Inst cache size
898     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
899     lp[4] = htonl(0x00010020); // Unified caches/Inst cache line size
900     lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
901     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
902     lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc
903     lp[8] = htonl(0x00800004); // TLB total size/TLB assoc
904     break;
905     default:
906     printf("WARNING: Unknown CPU type\n");
907     break;
908     }
909    
910     // Don't set SPRG3, don't test MQ
911     lp = (uint32 *)(ROM_BASE + loc + 0x20);
912     *lp++ = htonl(POWERPC_NOP);
913     lp++;
914     *lp++ = htonl(POWERPC_NOP);
915     lp++;
916     *lp = htonl(POWERPC_NOP);
917    
918     // Don't read MSR
919     lp = (uint32 *)(ROM_BASE + loc + 0x40);
920     *lp = htonl(0x39c00000); // li r14,0
921    
922     // Don't write to DEC
923     lp = (uint32 *)(ROM_BASE + loc + 0x70);
924     *lp++ = htonl(POWERPC_NOP);
925     loc = (ntohl(lp[0]) & 0xffff) + (uint32)lp - ROM_BASE;
926     D(bug("loc %08lx\n", loc));
927    
928     // Don't set SPRG3
929     lp = (uint32 *)(ROM_BASE + loc + 0x2c);
930     *lp = htonl(POWERPC_NOP);
931    
932     // Don't read PVR
933     static const uint32 pvr_ofs[] = {0x138, 0x138, 0x138, 0x140, 0x148};
934     lp = (uint32 *)(ROM_BASE + loc + pvr_ofs[ROMType]);
935     *lp = htonl(0x82e00000 + XLM_PVR); // lwz r23,(theoretical PVR)
936     lp = (uint32 *)(ROM_BASE + loc + 0x170);
937     if (ntohl(*lp) == 0x7eff42a6) // NewWorld ROM
938     *lp = htonl(0x82e00000 + XLM_PVR); // lwz r23,(theoretical PVR)
939     lp = (uint32 *)(ROM_BASE + 0x313134);
940     if (ntohl(*lp) == 0x7e5f42a6)
941     *lp = htonl(0x82400000 + XLM_PVR); // lwz r18,(theoretical PVR)
942     lp = (uint32 *)(ROM_BASE + 0x3131f4);
943     if (ntohl(*lp) == 0x7e5f42a6) // NewWorld ROM
944     *lp = htonl(0x82400000 + XLM_PVR); // lwz r18,(theoretical PVR)
945 gbeauche 1.4 lp = (uint32 *)(ROM_BASE + 0x314600);
946     if (ntohl(*lp) == 0x7d3f42a6)
947     *lp = htonl(0x81200000 + XLM_PVR); // lzw r9,(theoritical PVR)
948 cebix 1.1
949     // Don't read SDR1
950     static const uint32 sdr1_ofs[] = {0x174, 0x174, 0x174, 0x17c, 0x19c};
951     lp = (uint32 *)(ROM_BASE + loc + sdr1_ofs[ROMType]);
952     *lp++ = htonl(0x3d00dead); // lis r8,0xdead (pointer to page table)
953     *lp++ = htonl(0x3ec0001f); // lis r22,0x001f (size of page table)
954     *lp = htonl(POWERPC_NOP);
955    
956     // Don't clear page table
957     static const uint32 pgtb_ofs[] = {0x198, 0x198, 0x198, 0x1a0, 0x1c4};
958     lp = (uint32 *)(ROM_BASE + loc + pgtb_ofs[ROMType]);
959     *lp = htonl(POWERPC_NOP);
960    
961     // Don't invalidate TLB
962     static const uint32 tlb_ofs[] = {0x1a0, 0x1a0, 0x1a0, 0x1a8, 0x1cc};
963     lp = (uint32 *)(ROM_BASE + loc + tlb_ofs[ROMType]);
964     *lp = htonl(POWERPC_NOP);
965    
966     // Don't create RAM descriptor table
967     static const uint32 desc_ofs[] = {0x350, 0x350, 0x350, 0x358, 0x37c};
968     lp = (uint32 *)(ROM_BASE + loc + desc_ofs[ROMType]);
969     *lp = htonl(POWERPC_NOP);
970    
971     // Don't load SRs and BATs
972     static const uint32 sr_ofs[] = {0x3d8, 0x3d8, 0x3d8, 0x3e0, 0x404};
973     lp = (uint32 *)(ROM_BASE + loc + sr_ofs[ROMType]);
974     *lp = htonl(POWERPC_NOP);
975    
976     // Don't mess with SRs
977     static const uint32 sr2_ofs[] = {0x312118, 0x312118, 0x312118, 0x312118, 0x3121b4};
978     lp = (uint32 *)(ROM_BASE + sr2_ofs[ROMType]);
979     *lp = htonl(POWERPC_BLR);
980    
981     // Don't check performance monitor
982     static const uint32 pm_ofs[] = {0x313148, 0x313148, 0x313148, 0x313148, 0x313218};
983     lp = (uint32 *)(ROM_BASE + pm_ofs[ROMType]);
984     while (ntohl(*lp) != 0x7e58eba6) lp++;
985     *lp++ = htonl(POWERPC_NOP);
986     while (ntohl(*lp) != 0x7e78eaa6) lp++;
987     *lp++ = htonl(POWERPC_NOP);
988     while (ntohl(*lp) != 0x7e59eba6) lp++;
989     *lp++ = htonl(POWERPC_NOP);
990     while (ntohl(*lp) != 0x7e79eaa6) lp++;
991     *lp++ = htonl(POWERPC_NOP);
992     while (ntohl(*lp) != 0x7e5aeba6) lp++;
993     *lp++ = htonl(POWERPC_NOP);
994     while (ntohl(*lp) != 0x7e7aeaa6) lp++;
995     *lp++ = htonl(POWERPC_NOP);
996     while (ntohl(*lp) != 0x7e5beba6) lp++;
997     *lp++ = htonl(POWERPC_NOP);
998     while (ntohl(*lp) != 0x7e7beaa6) lp++;
999     *lp++ = htonl(POWERPC_NOP);
1000     while (ntohl(*lp) != 0x7e5feba6) lp++;
1001     *lp++ = htonl(POWERPC_NOP);
1002     while (ntohl(*lp) != 0x7e7feaa6) lp++;
1003     *lp++ = htonl(POWERPC_NOP);
1004     while (ntohl(*lp) != 0x7e5ceba6) lp++;
1005     *lp++ = htonl(POWERPC_NOP);
1006     while (ntohl(*lp) != 0x7e7ceaa6) lp++;
1007     *lp++ = htonl(POWERPC_NOP);
1008     while (ntohl(*lp) != 0x7e5deba6) lp++;
1009     *lp++ = htonl(POWERPC_NOP);
1010     while (ntohl(*lp) != 0x7e7deaa6) lp++;
1011     *lp++ = htonl(POWERPC_NOP);
1012     while (ntohl(*lp) != 0x7e5eeba6) lp++;
1013     *lp++ = htonl(POWERPC_NOP);
1014     while (ntohl(*lp) != 0x7e7eeaa6) lp++;
1015     *lp++ = htonl(POWERPC_NOP);
1016    
1017     // Jump to 68k emulator
1018     static const uint32 jump68k_ofs[] = {0x40c, 0x40c, 0x40c, 0x414, 0x438};
1019     lp = (uint32 *)(ROM_BASE + loc + jump68k_ofs[ROMType]);
1020     *lp++ = htonl(0x80610634); // lwz r3,0x0634(r1) (pointer to Emulator Data)
1021     *lp++ = htonl(0x8081119c); // lwz r4,0x119c(r1) (pointer to opcode table)
1022     *lp++ = htonl(0x80011184); // lwz r0,0x1184(r1) (pointer to emulator init routine)
1023     *lp++ = htonl(0x7c0903a6); // mtctr r0
1024     *lp = htonl(POWERPC_BCTR);
1025     return true;
1026     }
1027    
1028    
1029     /*
1030     * 68k emulator patches
1031     */
1032    
1033     static bool patch_68k_emul(void)
1034     {
1035     uint32 *lp;
1036     uint32 base;
1037    
1038     // Overwrite twi instructions
1039     static const uint32 twi_loc[] = {0x36e680, 0x36e6c0, 0x36e6c0, 0x36e6c0, 0x36e740};
1040     base = twi_loc[ROMType];
1041     lp = (uint32 *)(ROM_BASE + base);
1042     *lp++ = htonl(0x48000000 + 0x36f900 - base); // b 0x36f900 (Emulator start)
1043     *lp++ = htonl(0x48000000 + 0x36fa00 - base - 4); // b 0x36fa00 (Mixed mode)
1044     *lp++ = htonl(0x48000000 + 0x36fb00 - base - 8); // b 0x36fb00 (Reset/FC1E opcode)
1045     *lp++ = htonl(0x48000000 + 0x36fc00 - base - 12); // FE0A opcode
1046     *lp++ = htonl(POWERPC_ILLEGAL); // Interrupt
1047     *lp++ = htonl(POWERPC_ILLEGAL); // ?
1048     *lp++ = htonl(POWERPC_ILLEGAL);
1049     *lp++ = htonl(POWERPC_ILLEGAL);
1050     *lp++ = htonl(POWERPC_ILLEGAL);
1051     *lp++ = htonl(POWERPC_ILLEGAL);
1052     *lp++ = htonl(POWERPC_ILLEGAL);
1053     *lp++ = htonl(POWERPC_ILLEGAL);
1054     *lp++ = htonl(POWERPC_ILLEGAL);
1055     *lp++ = htonl(POWERPC_ILLEGAL);
1056     *lp++ = htonl(POWERPC_ILLEGAL);
1057     *lp = htonl(POWERPC_ILLEGAL);
1058    
1059     #if EMULATED_PPC
1060 gbeauche 1.7 // Install EMUL_RETURN, EXEC_RETURN, EXEC_NATIVE and EMUL_OP opcodes
1061 cebix 1.1 lp = (uint32 *)(ROM_BASE + 0x380000 + (M68K_EMUL_RETURN << 3));
1062     *lp++ = htonl(POWERPC_EMUL_OP);
1063     *lp++ = htonl(0x4bf66e80); // b 0x366084
1064     *lp++ = htonl(POWERPC_EMUL_OP | 1);
1065     *lp++ = htonl(0x4bf66e78); // b 0x366084
1066 gbeauche 1.7 *lp++ = htonl(POWERPC_EMUL_OP | 2);
1067     *lp++ = htonl(0x4bf66e70); // b 0x366084
1068 cebix 1.1 for (int i=0; i<OP_MAX; i++) {
1069 gbeauche 1.7 *lp++ = htonl(POWERPC_EMUL_OP | (i + 3));
1070     *lp++ = htonl(0x4bf66e68 - i*8); // b 0x366084
1071 cebix 1.1 }
1072     #else
1073     // Install EMUL_RETURN, EXEC_RETURN and EMUL_OP opcodes
1074     lp = (uint32 *)(ROM_BASE + 0x380000 + (M68K_EMUL_RETURN << 3));
1075     *lp++ = htonl(0x80000000 + XLM_EMUL_RETURN_PROC); // lwz r0,XLM_EMUL_RETURN_PROC
1076     *lp++ = htonl(0x4bf705fc); // b 0x36f800
1077     *lp++ = htonl(0x80000000 + XLM_EXEC_RETURN_PROC); // lwz r0,XLM_EXEC_RETURN_PROC
1078     *lp++ = htonl(0x4bf705f4); // b 0x36f800
1079 gbeauche 1.7 *lp++ = htonl(0x00dead00); // Let SheepShaver crash, since
1080     *lp++ = htonl(0x00beef00); // no native opcode is available
1081 cebix 1.1 for (int i=0; i<OP_MAX; i++) {
1082     *lp++ = htonl(0x38a00000 + i); // li r5,OP_*
1083 gbeauche 1.7 *lp++ = htonl(0x4bf705ec - i*8); // b 0x36f808
1084 cebix 1.1 }
1085    
1086     // Extra routines for EMUL_RETURN/EXEC_RETURN/EMUL_OP
1087     lp = (uint32 *)(ROM_BASE + 0x36f800);
1088     *lp++ = htonl(0x7c0803a6); // mtlr r0
1089     *lp++ = htonl(0x4e800020); // blr
1090    
1091     *lp++ = htonl(0x80000000 + XLM_EMUL_OP_PROC); // lwz r0,XLM_EMUL_OP_PROC
1092     *lp++ = htonl(0x7c0803a6); // mtlr r0
1093     *lp = htonl(0x4e800020); // blr
1094     #endif
1095    
1096     // Extra routine for 68k emulator start
1097     lp = (uint32 *)(ROM_BASE + 0x36f900);
1098     *lp++ = htonl(0x7c2903a6); // mtctr r1
1099 gbeauche 1.8 #if EMULATED_PPC
1100     *lp++ = POWERPC_NATIVE_OP(NATIVE_DISABLE_INTERRUPT);
1101     #else
1102 cebix 1.1 *lp++ = htonl(0x80200000 + XLM_IRQ_NEST); // lwz r1,XLM_IRQ_NEST
1103     *lp++ = htonl(0x38210001); // addi r1,r1,1
1104     *lp++ = htonl(0x90200000 + XLM_IRQ_NEST); // stw r1,XLM_IRQ_NEST
1105 gbeauche 1.8 #endif
1106 cebix 1.1 *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz r1,XLM_KERNEL_DATA
1107     *lp++ = htonl(0x90c10018); // stw r6,0x18(r1)
1108     *lp++ = htonl(0x7cc902a6); // mfctr r6
1109     *lp++ = htonl(0x90c10004); // stw r6,$0004(r1)
1110     *lp++ = htonl(0x80c1065c); // lwz r6,$065c(r1)
1111     *lp++ = htonl(0x90e6013c); // stw r7,$013c(r6)
1112     *lp++ = htonl(0x91060144); // stw r8,$0144(r6)
1113     *lp++ = htonl(0x9126014c); // stw r9,$014c(r6)
1114     *lp++ = htonl(0x91460154); // stw r10,$0154(r6)
1115     *lp++ = htonl(0x9166015c); // stw r11,$015c(r6)
1116     *lp++ = htonl(0x91860164); // stw r12,$0164(r6)
1117     *lp++ = htonl(0x91a6016c); // stw r13,$016c(r6)
1118     *lp++ = htonl(0x7da00026); // mfcr r13
1119     *lp++ = htonl(0x80e10660); // lwz r7,$0660(r1)
1120     *lp++ = htonl(0x7d8802a6); // mflr r12
1121     *lp++ = htonl(0x50e74001); // rlwimi. r7,r7,8,$80000000
1122     *lp++ = htonl(0x814105f0); // lwz r10,0x05f0(r1)
1123     *lp++ = htonl(0x7d4803a6); // mtlr r10
1124     *lp++ = htonl(0x7d8a6378); // mr r10,r12
1125     *lp++ = htonl(0x3d600002); // lis r11,0x0002
1126     *lp++ = htonl(0x616bf072); // ori r11,r11,0xf072 (MSR)
1127     *lp++ = htonl(0x50e7deb4); // rlwimi r7,r7,27,$00000020
1128     *lp = htonl(0x4e800020); // blr
1129    
1130     // Extra routine for Mixed Mode
1131     lp = (uint32 *)(ROM_BASE + 0x36fa00);
1132     *lp++ = htonl(0x7c2903a6); // mtctr r1
1133 gbeauche 1.8 #if EMULATED_PPC
1134     *lp++ = POWERPC_NATIVE_OP(NATIVE_DISABLE_INTERRUPT);
1135     #else
1136 cebix 1.1 *lp++ = htonl(0x80200000 + XLM_IRQ_NEST); // lwz r1,XLM_IRQ_NEST
1137     *lp++ = htonl(0x38210001); // addi r1,r1,1
1138     *lp++ = htonl(0x90200000 + XLM_IRQ_NEST); // stw r1,XLM_IRQ_NEST
1139 gbeauche 1.8 #endif
1140 cebix 1.1 *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz r1,XLM_KERNEL_DATA
1141     *lp++ = htonl(0x90c10018); // stw r6,0x18(r1)
1142     *lp++ = htonl(0x7cc902a6); // mfctr r6
1143     *lp++ = htonl(0x90c10004); // stw r6,$0004(r1)
1144     *lp++ = htonl(0x80c1065c); // lwz r6,$065c(r1)
1145     *lp++ = htonl(0x90e6013c); // stw r7,$013c(r6)
1146     *lp++ = htonl(0x91060144); // stw r8,$0144(r6)
1147     *lp++ = htonl(0x9126014c); // stw r9,$014c(r6)
1148     *lp++ = htonl(0x91460154); // stw r10,$0154(r6)
1149     *lp++ = htonl(0x9166015c); // stw r11,$015c(r6)
1150     *lp++ = htonl(0x91860164); // stw r12,$0164(r6)
1151     *lp++ = htonl(0x91a6016c); // stw r13,$016c(r6)
1152     *lp++ = htonl(0x7da00026); // mfcr r13
1153     *lp++ = htonl(0x80e10660); // lwz r7,$0660(r1)
1154     *lp++ = htonl(0x7d8802a6); // mflr r12
1155     *lp++ = htonl(0x50e74001); // rlwimi. r7,r7,8,$80000000
1156     *lp++ = htonl(0x814105f4); // lwz r10,0x05f4(r1)
1157     *lp++ = htonl(0x7d4803a6); // mtlr r10
1158     *lp++ = htonl(0x7d8a6378); // mr r10,r12
1159     *lp++ = htonl(0x3d600002); // lis r11,0x0002
1160     *lp++ = htonl(0x616bf072); // ori r11,r11,0xf072 (MSR)
1161     *lp++ = htonl(0x50e7deb4); // rlwimi r7,r7,27,$00000020
1162     *lp = htonl(0x4e800020); // blr
1163    
1164     // Extra routine for Reset/FC1E opcode
1165 gbeauche 1.4 lp = (uint32 *)(ROM_BASE + 0x36fb00);
1166 cebix 1.1 *lp++ = htonl(0x7c2903a6); // mtctr r1
1167 gbeauche 1.8 #if EMULATED_PPC
1168     *lp++ = POWERPC_NATIVE_OP(NATIVE_DISABLE_INTERRUPT);
1169     #else
1170 cebix 1.1 *lp++ = htonl(0x80200000 + XLM_IRQ_NEST); // lwz r1,XLM_IRQ_NEST
1171     *lp++ = htonl(0x38210001); // addi r1,r1,1
1172     *lp++ = htonl(0x90200000 + XLM_IRQ_NEST); // stw r1,XLM_IRQ_NEST
1173 gbeauche 1.8 #endif
1174 cebix 1.1 *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz r1,XLM_KERNEL_DATA
1175     *lp++ = htonl(0x90c10018); // stw r6,0x18(r1)
1176     *lp++ = htonl(0x7cc902a6); // mfctr r6
1177     *lp++ = htonl(0x90c10004); // stw r6,$0004(r1)
1178     *lp++ = htonl(0x80c1065c); // lwz r6,$065c(r1)
1179     *lp++ = htonl(0x90e6013c); // stw r7,$013c(r6)
1180     *lp++ = htonl(0x91060144); // stw r8,$0144(r6)
1181     *lp++ = htonl(0x9126014c); // stw r9,$014c(r6)
1182     *lp++ = htonl(0x91460154); // stw r10,$0154(r6)
1183     *lp++ = htonl(0x9166015c); // stw r11,$015c(r6)
1184     *lp++ = htonl(0x91860164); // stw r12,$0164(r6)
1185     *lp++ = htonl(0x91a6016c); // stw r13,$016c(r6)
1186     *lp++ = htonl(0x7da00026); // mfcr r13
1187     *lp++ = htonl(0x80e10660); // lwz r7,$0660(r1)
1188     *lp++ = htonl(0x7d8802a6); // mflr r12
1189     *lp++ = htonl(0x50e74001); // rlwimi. r7,r7,8,$80000000
1190 gbeauche 1.4 *lp++ = htonl(0x814105f8); // lwz r10,0x05f8(r1)
1191 cebix 1.1 *lp++ = htonl(0x7d4803a6); // mtlr r10
1192     *lp++ = htonl(0x7d8a6378); // mr r10,r12
1193     *lp++ = htonl(0x3d600002); // lis r11,0x0002
1194     *lp++ = htonl(0x616bf072); // ori r11,r11,0xf072 (MSR)
1195     *lp++ = htonl(0x50e7deb4); // rlwimi r7,r7,27,$00000020
1196     *lp = htonl(0x4e800020); // blr
1197    
1198     // Extra routine for FE0A opcode (QuickDraw 3D needs this)
1199     lp = (uint32 *)(ROM_BASE + 0x36fc00);
1200     *lp++ = htonl(0x7c2903a6); // mtctr r1
1201 gbeauche 1.8 #if EMULATED_PPC
1202     *lp++ = POWERPC_NATIVE_OP(NATIVE_DISABLE_INTERRUPT);
1203     #else
1204 cebix 1.1 *lp++ = htonl(0x80200000 + XLM_IRQ_NEST); // lwz r1,XLM_IRQ_NEST
1205     *lp++ = htonl(0x38210001); // addi r1,r1,1
1206     *lp++ = htonl(0x90200000 + XLM_IRQ_NEST); // stw r1,XLM_IRQ_NEST
1207 gbeauche 1.8 #endif
1208 cebix 1.1 *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz r1,XLM_KERNEL_DATA
1209     *lp++ = htonl(0x90c10018); // stw r6,0x18(r1)
1210     *lp++ = htonl(0x7cc902a6); // mfctr r6
1211     *lp++ = htonl(0x90c10004); // stw r6,$0004(r1)
1212     *lp++ = htonl(0x80c1065c); // lwz r6,$065c(r1)
1213     *lp++ = htonl(0x90e6013c); // stw r7,$013c(r6)
1214     *lp++ = htonl(0x91060144); // stw r8,$0144(r6)
1215     *lp++ = htonl(0x9126014c); // stw r9,$014c(r6)
1216     *lp++ = htonl(0x91460154); // stw r10,$0154(r6)
1217     *lp++ = htonl(0x9166015c); // stw r11,$015c(r6)
1218     *lp++ = htonl(0x91860164); // stw r12,$0164(r6)
1219     *lp++ = htonl(0x91a6016c); // stw r13,$016c(r6)
1220     *lp++ = htonl(0x7da00026); // mfcr r13
1221     *lp++ = htonl(0x80e10660); // lwz r7,$0660(r1)
1222     *lp++ = htonl(0x7d8802a6); // mflr r12
1223     *lp++ = htonl(0x50e74001); // rlwimi. r7,r7,8,$80000000
1224 gbeauche 1.4 *lp++ = htonl(0x814105fc); // lwz r10,0x05fc(r1)
1225 cebix 1.1 *lp++ = htonl(0x7d4803a6); // mtlr r10
1226     *lp++ = htonl(0x7d8a6378); // mr r10,r12
1227     *lp++ = htonl(0x3d600002); // lis r11,0x0002
1228     *lp++ = htonl(0x616bf072); // ori r11,r11,0xf072 (MSR)
1229     *lp++ = htonl(0x50e7deb4); // rlwimi r7,r7,27,$00000020
1230     *lp = htonl(0x4e800020); // blr
1231    
1232     // Patch DR emulator to jump to right address when an interrupt occurs
1233     lp = (uint32 *)(ROM_BASE + 0x370000);
1234     while (lp < (uint32 *)(ROM_BASE + 0x380000)) {
1235     if (ntohl(*lp) == 0x4ca80020) // bclr 5,8
1236     goto dr_found;
1237     lp++;
1238     }
1239     D(bug("DR emulator patch location not found\n"));
1240     return false;
1241     dr_found:
1242     lp++;
1243     *lp = htonl(0x48000000 + 0xf000 - (((uint32)lp - ROM_BASE) & 0xffff)); // b DR_CACHE_BASE+0x1f000
1244     lp = (uint32 *)(ROM_BASE + 0x37f000);
1245     *lp++ = htonl(0x3c000000 + ((ROM_BASE + 0x46d0a4) >> 16)); // lis r0,xxx
1246     *lp++ = htonl(0x60000000 + ((ROM_BASE + 0x46d0a4) & 0xffff)); // ori r0,r0,xxx
1247     *lp++ = htonl(0x7c0903a6); // mtctr r0
1248     *lp = htonl(POWERPC_BCTR); // bctr
1249     return true;
1250     }
1251    
1252    
1253     /*
1254     * Nanokernel patches
1255     */
1256    
1257     static bool patch_nanokernel(void)
1258     {
1259     uint32 *lp;
1260    
1261     // Patch Mixed Mode trap
1262     lp = (uint32 *)(ROM_BASE + 0x313c90); // Don't translate virtual->physical
1263     while (ntohl(*lp) != 0x3ba10320) lp++;
1264     lp++;
1265     *lp++ = htonl(0x7f7fdb78); // mr r31,r27
1266     lp++;
1267     *lp = htonl(POWERPC_NOP);
1268    
1269     lp = (uint32 *)(ROM_BASE + 0x313c3c); // Don't activate PPC exception table
1270     while (ntohl(*lp) != 0x39010420) lp++;
1271     *lp++ = htonl(0x39000000 + MODE_NATIVE); // li r8,MODE_NATIVE
1272     *lp = htonl(0x91000000 + XLM_RUN_MODE); // stw r8,XLM_RUN_MODE
1273    
1274     lp = (uint32 *)(ROM_BASE + 0x312e88); // Don't modify MSR to turn on FPU
1275     while (ntohl(*lp) != 0x556b04e2) lp++;
1276     lp -= 4;
1277     *lp++ = htonl(POWERPC_NOP);
1278     lp++;
1279     *lp++ = htonl(POWERPC_NOP);
1280     lp++;
1281     *lp = htonl(POWERPC_NOP);
1282    
1283     lp = (uint32 *)(ROM_BASE + 0x312b3c); // Always save FPU state
1284     while (ntohl(*lp) != 0x81010668) lp++;
1285     lp--;
1286     *lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff)); // bl 0x00312e88
1287    
1288     lp = (uint32 *)(ROM_BASE + 0x312b44); // Don't read DEC
1289     while (ntohl(*lp) != 0x7ff602a6) lp++;
1290     *lp = htonl(0x3be00000); // li r31,0
1291    
1292     lp = (uint32 *)(ROM_BASE + 0x312b50); // Don't write DEC
1293     while (ntohl(*lp) != 0x7d1603a6) lp++;
1294     #if 1
1295     *lp++ = htonl(POWERPC_NOP);
1296     *lp = htonl(POWERPC_NOP);
1297     #else
1298     *lp++ = htonl(0x39000040); // li r8,0x40
1299     *lp = htonl(0x990600e4); // stb r8,0xe4(r6)
1300     #endif
1301    
1302     lp = (uint32 *)(ROM_BASE + 0x312b9c); // Always restore FPU state
1303     while (ntohl(*lp) != 0x7c00092d) lp++;
1304     lp--;
1305     *lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff)); // bl 0x00312ddc
1306    
1307     lp = (uint32 *)(ROM_BASE + 0x312a68); // Don't activate 68k exception table
1308     while (ntohl(*lp) != 0x39010360) lp++;
1309     *lp++ = htonl(0x39000000 + MODE_68K); // li r8,MODE_68K
1310     *lp = htonl(0x91000000 + XLM_RUN_MODE); // stw r8,XLM_RUN_MODE
1311    
1312     // Patch 68k emulator trap routine
1313     lp = (uint32 *)(ROM_BASE + 0x312994); // Always restore FPU state
1314     while (ntohl(*lp) != 0x39260040) lp++;
1315     lp--;
1316     *lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff)); // bl 0x00312dd4
1317    
1318     lp = (uint32 *)(ROM_BASE + 0x312dd8); // Don't modify MSR to turn on FPU
1319     while (ntohl(*lp) != 0x810600e4) lp++;
1320     lp--;
1321     *lp++ = htonl(POWERPC_NOP);
1322     lp += 2;
1323     *lp++ = htonl(POWERPC_NOP);
1324     lp++;
1325     *lp++ = htonl(POWERPC_NOP);
1326     *lp++ = htonl(POWERPC_NOP);
1327     *lp = htonl(POWERPC_NOP);
1328    
1329     // Patch trap return routine
1330     lp = (uint32 *)(ROM_BASE + 0x312c20);
1331     while (ntohl(*lp) != 0x7d5a03a6) lp++;
1332     *lp++ = htonl(0x7d4903a6); // mtctr r10
1333     *lp++ = htonl(0x7daff120); // mtcr r13
1334     *lp = htonl(0x48000000 + 0x8000 - (((uint32)lp - ROM_BASE) & 0xffff)); // b ROM_BASE+0x318000
1335     uint32 xlp = ((uint32)(lp+1) - ROM_BASE) & 0xffff;
1336    
1337     lp = (uint32 *)(ROM_BASE + 0x312c50); // Replace rfi
1338     while (ntohl(*lp) != 0x4c000064) lp++;
1339     *lp = htonl(POWERPC_BCTR);
1340    
1341     lp = (uint32 *)(ROM_BASE + 0x318000);
1342 gbeauche 1.8 #if EMULATED_PPC
1343     *lp++ = POWERPC_NATIVE_OP(NATIVE_ENABLE_INTERRUPT);
1344     *lp = htonl(0x48000000 + ((xlp - 0x8004) & 0x03fffffc)); // b ROM_BASE+0x312c2c
1345     #else
1346 cebix 1.1 *lp++ = htonl(0x81400000 + XLM_IRQ_NEST); // lwz r10,XLM_IRQ_NEST
1347     *lp++ = htonl(0x394affff); // subi r10,r10,1
1348     *lp++ = htonl(0x91400000 + XLM_IRQ_NEST); // stw r10,XLM_IRQ_NEST
1349     *lp = htonl(0x48000000 + ((xlp - 0x800c) & 0x03fffffc)); // b ROM_BASE+0x312c2c
1350 gbeauche 1.8 #endif
1351    
1352 cebix 1.1 /*
1353     // Disable FE0A/FE06 opcodes
1354     lp = (uint32 *)(ROM_BASE + 0x3144ac);
1355     *lp++ = htonl(POWERPC_NOP);
1356     *lp += 8;
1357     */
1358     return true;
1359     }
1360    
1361    
1362     /*
1363     * 68k boot routine patches
1364     */
1365    
1366     static bool patch_68k(void)
1367     {
1368     uint32 *lp;
1369     uint16 *wp;
1370     uint8 *bp;
1371     uint32 base;
1372    
1373     // Remove 68k RESET instruction
1374     static const uint8 reset_dat[] = {0x4e, 0x70};
1375     if ((base = find_rom_data(0xc8, 0x120, reset_dat, sizeof(reset_dat))) == 0) return false;
1376     D(bug("reset %08lx\n", base));
1377     wp = (uint16 *)(ROM_BASE + base);
1378     *wp = htons(M68K_NOP);
1379    
1380     // Fake reading PowerMac ID (via Universal)
1381     static const uint8 powermac_id_dat[] = {0x45, 0xf9, 0x5f, 0xff, 0xff, 0xfc, 0x20, 0x12, 0x72, 0x00};
1382     if ((base = find_rom_data(0xe000, 0x15000, powermac_id_dat, sizeof(powermac_id_dat))) == 0) return false;
1383     D(bug("powermac_id %08lx\n", base));
1384     wp = (uint16 *)(ROM_BASE + base);
1385     *wp++ = htons(0x203c); // move.l #id,d0
1386     *wp++ = htons(0);
1387     // if (ROMType == ROMTYPE_NEWWORLD)
1388     // *wp++ = htons(0x3035); // (PowerMac 9500 ID)
1389     // else
1390     *wp++ = htons(0x3020); // (PowerMac 9500 ID)
1391     *wp++ = htons(0xb040); // cmp.w d0,d0
1392     *wp = htons(0x4ed6); // jmp (a6)
1393    
1394     // Patch UniversalInfo
1395     if (ROMType == ROMTYPE_NEWWORLD) {
1396     static const uint8 univ_info_dat[] = {0x3f, 0xff, 0x04, 0x00};
1397 gbeauche 1.4 if ((base = find_rom_data(0x14000, 0x18000, univ_info_dat, sizeof(univ_info_dat))) == 0) return false;
1398 cebix 1.1 D(bug("universal_info %08lx\n", base));
1399     lp = (uint32 *)(ROM_BASE + base - 0x14);
1400     lp[0x00 >> 2] = htonl(ADDR_MAP_PATCH_SPACE - (base - 0x14));
1401     lp[0x10 >> 2] = htonl(0xcc003d11); // Make it like the PowerMac 9500 UniversalInfo
1402     lp[0x14 >> 2] = htonl(0x3fff0401);
1403     lp[0x18 >> 2] = htonl(0x0300001c);
1404     lp[0x1c >> 2] = htonl(0x000108c4);
1405     lp[0x24 >> 2] = htonl(0xc301bf26);
1406     lp[0x28 >> 2] = htonl(0x00000861);
1407     lp[0x58 >> 2] = htonl(0x30200000);
1408     lp[0x60 >> 2] = htonl(0x0000003d);
1409     } else if (ROMType == ROMTYPE_ZANZIBAR) {
1410     base = 0x12b70;
1411     lp = (uint32 *)(ROM_BASE + base - 0x14);
1412     lp[0x00 >> 2] = htonl(ADDR_MAP_PATCH_SPACE - (base - 0x14));
1413     lp[0x10 >> 2] = htonl(0xcc003d11); // Make it like the PowerMac 9500 UniversalInfo
1414     lp[0x14 >> 2] = htonl(0x3fff0401);
1415     lp[0x18 >> 2] = htonl(0x0300001c);
1416     lp[0x1c >> 2] = htonl(0x000108c4);
1417     lp[0x24 >> 2] = htonl(0xc301bf26);
1418     lp[0x28 >> 2] = htonl(0x00000861);
1419     lp[0x58 >> 2] = htonl(0x30200000);
1420     lp[0x60 >> 2] = htonl(0x0000003d);
1421     }
1422    
1423     // Construct AddrMap for NewWorld ROM
1424     if (ROMType == ROMTYPE_NEWWORLD || ROMType == ROMTYPE_ZANZIBAR) {
1425     lp = (uint32 *)(ROM_BASE + ADDR_MAP_PATCH_SPACE);
1426     memset(lp - 10, 0, 0x128);
1427     lp[-10] = htonl(0x0300001c);
1428     lp[-9] = htonl(0x000108c4);
1429     lp[-4] = htonl(0x00300000);
1430     lp[-2] = htonl(0x11010000);
1431     lp[-1] = htonl(0xf8000000);
1432     lp[0] = htonl(0xffc00000);
1433     lp[2] = htonl(0xf3016000);
1434     lp[3] = htonl(0xf3012000);
1435     lp[4] = htonl(0xf3012000);
1436     lp[24] = htonl(0xf3018000);
1437     lp[25] = htonl(0xf3010000);
1438     lp[34] = htonl(0xf3011000);
1439     lp[38] = htonl(0xf3015000);
1440     lp[39] = htonl(0xf3014000);
1441     lp[43] = htonl(0xf3000000);
1442     lp[48] = htonl(0xf8000000);
1443     }
1444    
1445     // Don't initialize VIA (via Universal)
1446     static const uint8 via_init_dat[] = {0x08, 0x00, 0x00, 0x02, 0x67, 0x00, 0x00, 0x2c, 0x24, 0x68, 0x00, 0x08};
1447     if ((base = find_rom_data(0xe000, 0x15000, via_init_dat, sizeof(via_init_dat))) == 0) return false;
1448     D(bug("via_init %08lx\n", base));
1449     wp = (uint16 *)(ROM_BASE + base + 4);
1450     *wp = htons(0x6000); // bra
1451    
1452     static const uint8 via_init2_dat[] = {0x24, 0x68, 0x00, 0x08, 0x00, 0x12, 0x00, 0x30, 0x4e, 0x71};
1453     if ((base = find_rom_data(0xa000, 0x10000, via_init2_dat, sizeof(via_init2_dat))) == 0) return false;
1454     D(bug("via_init2 %08lx\n", base));
1455     wp = (uint16 *)(ROM_BASE + base);
1456     *wp = htons(0x4ed6); // jmp (a6)
1457    
1458     static const uint8 via_init3_dat[] = {0x22, 0x68, 0x00, 0x08, 0x28, 0x3c, 0x20, 0x00, 0x01, 0x00};
1459     if ((base = find_rom_data(0xa000, 0x10000, via_init3_dat, sizeof(via_init3_dat))) == 0) return false;
1460     D(bug("via_init3 %08lx\n", base));
1461     wp = (uint16 *)(ROM_BASE + base);
1462     *wp = htons(0x4ed6); // jmp (a6)
1463    
1464     // Don't RunDiags, get BootGlobs pointer directly
1465     if (ROMType == ROMTYPE_NEWWORLD) {
1466     static const uint8 run_diags_dat[] = {0x60, 0xff, 0x00, 0x0c};
1467     if ((base = find_rom_data(0x110, 0x128, run_diags_dat, sizeof(run_diags_dat))) == 0) return false;
1468     D(bug("run_diags %08lx\n", base));
1469     wp = (uint16 *)(ROM_BASE + base);
1470     *wp++ = htons(0x4df9); // lea xxx,a6
1471     *wp++ = htons((RAMBase + RAMSize - 0x1c) >> 16);
1472     *wp = htons((RAMBase + RAMSize - 0x1c) & 0xffff);
1473     } else {
1474     static const uint8 run_diags_dat[] = {0x74, 0x00, 0x2f, 0x0e};
1475     if ((base = find_rom_data(0xd0, 0xf0, run_diags_dat, sizeof(run_diags_dat))) == 0) return false;
1476     D(bug("run_diags %08lx\n", base));
1477     wp = (uint16 *)(ROM_BASE + base - 6);
1478     *wp++ = htons(0x4df9); // lea xxx,a6
1479     *wp++ = htons((RAMBase + RAMSize - 0x1c) >> 16);
1480     *wp = htons((RAMBase + RAMSize - 0x1c) & 0xffff);
1481     }
1482    
1483     // Replace NVRAM routines
1484     static const uint8 nvram1_dat[] = {0x48, 0xe7, 0x01, 0x0e, 0x24, 0x68, 0x00, 0x08, 0x08, 0x83, 0x00, 0x1f};
1485     if ((base = find_rom_data(0x7000, 0xc000, nvram1_dat, sizeof(nvram1_dat))) == 0) return false;
1486     D(bug("nvram1 %08lx\n", base));
1487     wp = (uint16 *)(ROM_BASE + base);
1488     *wp++ = htons(M68K_EMUL_OP_XPRAM1);
1489     *wp = htons(M68K_RTS);
1490    
1491     if (ROMType == ROMTYPE_NEWWORLD) {
1492     static const uint8 nvram2_dat[] = {0x48, 0xe7, 0x1c, 0xe0, 0x4f, 0xef, 0xff, 0xb4};
1493     if ((base = find_rom_data(0xa000, 0xd000, nvram2_dat, sizeof(nvram2_dat))) == 0) return false;
1494     D(bug("nvram2 %08lx\n", base));
1495     wp = (uint16 *)(ROM_BASE + base);
1496     *wp++ = htons(M68K_EMUL_OP_XPRAM2);
1497     *wp = htons(0x4ed3); // jmp (a3)
1498    
1499     static const uint8 nvram3_dat[] = {0x48, 0xe7, 0xdc, 0xe0, 0x4f, 0xef, 0xff, 0xb4};
1500     if ((base = find_rom_data(0xa000, 0xd000, nvram3_dat, sizeof(nvram3_dat))) == 0) return false;
1501     D(bug("nvram3 %08lx\n", base));
1502     wp = (uint16 *)(ROM_BASE + base);
1503     *wp++ = htons(M68K_EMUL_OP_XPRAM3);
1504     *wp = htons(0x4ed3); // jmp (a3)
1505    
1506     static const uint8 nvram4_dat[] = {0x4e, 0x56, 0xff, 0xa8, 0x48, 0xe7, 0x1f, 0x38, 0x16, 0x2e, 0x00, 0x13};
1507     if ((base = find_rom_data(0xa000, 0xd000, nvram4_dat, sizeof(nvram4_dat))) == 0) return false;
1508     D(bug("nvram4 %08lx\n", base));
1509     wp = (uint16 *)(ROM_BASE + base + 16);
1510     *wp++ = htons(0x1a2e); // move.b ($000f,a6),d5
1511     *wp++ = htons(0x000f);
1512     *wp++ = htons(M68K_EMUL_OP_NVRAM3);
1513     *wp++ = htons(0x4cee); // movem.l ($ff88,a6),d3-d7/a2-a4
1514     *wp++ = htons(0x1cf8);
1515     *wp++ = htons(0xff88);
1516     *wp++ = htons(0x4e5e); // unlk a6
1517     *wp = htons(M68K_RTS);
1518    
1519     static const uint8 nvram5_dat[] = {0x0c, 0x80, 0x03, 0x00, 0x00, 0x00, 0x66, 0x0a, 0x70, 0x00, 0x21, 0xf8, 0x02, 0x0c, 0x01, 0xe4};
1520     if ((base = find_rom_data(0xa000, 0xd000, nvram5_dat, sizeof(nvram5_dat))) == 0) return false;
1521     D(bug("nvram5 %08lx\n", base));
1522     wp = (uint16 *)(ROM_BASE + base + 6);
1523     *wp = htons(M68K_NOP);
1524    
1525     static const uint8 nvram6_dat[] = {0x2f, 0x0a, 0x24, 0x48, 0x4f, 0xef, 0xff, 0xa0, 0x20, 0x0f};
1526     if ((base = find_rom_data(0x9000, 0xb000, nvram6_dat, sizeof(nvram6_dat))) == 0) return false;
1527     D(bug("nvram6 %08lx\n", base));
1528     wp = (uint16 *)(ROM_BASE + base);
1529     *wp++ = htons(0x7000); // moveq #0,d0
1530     *wp++ = htons(0x2080); // move.l d0,(a0)
1531     *wp++ = htons(0x4228); // clr.b 4(a0)
1532     *wp++ = htons(0x0004);
1533     *wp = htons(M68K_RTS);
1534    
1535     static const uint8 nvram7_dat[] = {0x42, 0x2a, 0x00, 0x04, 0x4f, 0xef, 0x00, 0x60, 0x24, 0x5f, 0x4e, 0x75, 0x4f, 0xef, 0xff, 0xa0, 0x20, 0x0f};
1536     base = find_rom_data(0x9000, 0xb000, nvram7_dat, sizeof(nvram7_dat));
1537     if (base) {
1538     D(bug("nvram7 %08lx\n", base));
1539     wp = (uint16 *)(ROM_BASE + base + 12);
1540     *wp = htons(M68K_RTS);
1541     }
1542     } else {
1543     static const uint8 nvram2_dat[] = {0x4e, 0xd6, 0x06, 0x41, 0x13, 0x00};
1544     if ((base = find_rom_data(0x7000, 0xb000, nvram2_dat, sizeof(nvram2_dat))) == 0) return false;
1545     D(bug("nvram2 %08lx\n", base));
1546     wp = (uint16 *)(ROM_BASE + base + 2);
1547     *wp++ = htons(M68K_EMUL_OP_XPRAM2);
1548     *wp = htons(0x4ed3); // jmp (a3)
1549    
1550     static const uint32 nvram3_loc[] = {0x582f0, 0xa0a0, 0x7e50, 0xa1d0, 0};
1551     wp = (uint16 *)(ROM_BASE + nvram3_loc[ROMType]);
1552     *wp++ = htons(0x202f); // move.l 4(sp),d0
1553     *wp++ = htons(0x0004);
1554     *wp++ = htons(M68K_EMUL_OP_NVRAM1);
1555     if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_GAZELLE)
1556     *wp = htons(M68K_RTS);
1557     else {
1558     *wp++ = htons(0x1f40); // move.b d0,8(sp)
1559     *wp++ = htons(0x0008);
1560     *wp++ = htons(0x4e74); // rtd #4
1561     *wp = htons(0x0004);
1562     }
1563    
1564     static const uint32 nvram4_loc[] = {0x58460, 0xa0f0, 0x7f40, 0xa220, 0};
1565     wp = (uint16 *)(ROM_BASE + nvram4_loc[ROMType]);
1566     if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_GAZELLE) {
1567     *wp++ = htons(0x202f); // move.l 4(sp),d0
1568     *wp++ = htons(0x0004);
1569     *wp++ = htons(0x122f); // move.b 11(sp),d1
1570     *wp++ = htons(0x000b);
1571     *wp++ = htons(M68K_EMUL_OP_NVRAM2);
1572     *wp = htons(M68K_RTS);
1573     } else {
1574     *wp++ = htons(0x202f); // move.l 6(sp),d0
1575     *wp++ = htons(0x0006);
1576     *wp++ = htons(0x122f); // move.b 4(sp),d1
1577     *wp++ = htons(0x0004);
1578     *wp++ = htons(M68K_EMUL_OP_NVRAM2);
1579     *wp++ = htons(0x4e74); // rtd #6
1580     *wp = htons(0x0006);
1581     }
1582     }
1583    
1584     // Fix MemTop/BootGlobs during system startup
1585     static const uint8 mem_top_dat[] = {0x2c, 0x6c, 0xff, 0xec, 0x2a, 0x4c, 0xdb, 0xec, 0xff, 0xf4};
1586     if ((base = find_rom_data(0x120, 0x180, mem_top_dat, sizeof(mem_top_dat))) == 0) return false;
1587     D(bug("mem_top %08lx\n", base));
1588     wp = (uint16 *)(ROM_BASE + base);
1589     *wp++ = htons(M68K_EMUL_OP_FIX_MEMTOP);
1590     *wp = htons(M68K_NOP);
1591    
1592     // Don't initialize SCC (via 0x1ac)
1593     static const uint8 scc_init_dat[] = {0x48, 0xe7, 0x38, 0xfe};
1594     if ((base = find_rom_data(0x190, 0x1f0, scc_init_dat, sizeof(scc_init_dat))) == 0) return false;
1595     D(bug("scc_init %08lx\n", base));
1596     wp = (uint16 *)(ROM_BASE + base - 2);
1597     wp = (uint16 *)(ROM_BASE + ntohs(*wp) + base - 2);
1598     *wp++ = htons(M68K_EMUL_OP_RESET);
1599     *wp = htons(M68K_RTS);
1600    
1601     // Don't EnableExtCache (via 0x1f6) and don't DisableIntSources(via 0x1fc)
1602     static const uint8 ext_cache_dat[] = {0x4e, 0x7b, 0x00, 0x02};
1603     if ((base = find_rom_data(0x1d0, 0x230, ext_cache_dat, sizeof(ext_cache_dat))) == 0) return false;
1604     D(bug("ext_cache %08lx\n", base));
1605     lp = (uint32 *)(ROM_BASE + base + 6);
1606     wp = (uint16 *)(ROM_BASE + ntohl(*lp) + base + 6);
1607     *wp = htons(M68K_RTS);
1608     lp = (uint32 *)(ROM_BASE + base + 12);
1609     wp = (uint16 *)(ROM_BASE + ntohl(*lp) + base + 12);
1610     *wp = htons(M68K_RTS);
1611    
1612     // Fake CPU speed test (SetupTimeK)
1613     static const uint8 timek_dat[] = {0x0c, 0x38, 0x00, 0x04, 0x01, 0x2f, 0x6d, 0x3c};
1614     if ((base = find_rom_data(0x400, 0x500, timek_dat, sizeof(timek_dat))) == 0) return false;
1615     D(bug("timek %08lx\n", base));
1616     wp = (uint16 *)(ROM_BASE + base);
1617     *wp++ = htons(0x31fc); // move.w #xxx,TimeDBRA
1618     *wp++ = htons(100);
1619     *wp++ = htons(0x0d00);
1620     *wp++ = htons(0x31fc); // move.w #xxx,TimeSCCDBRA
1621     *wp++ = htons(100);
1622     *wp++ = htons(0x0d02);
1623     *wp++ = htons(0x31fc); // move.w #xxx,TimeSCSIDBRA
1624     *wp++ = htons(100);
1625     *wp++ = htons(0x0b24);
1626     *wp++ = htons(0x31fc); // move.w #xxx,TimeRAMDBRA
1627     *wp++ = htons(100);
1628     *wp++ = htons(0x0cea);
1629     *wp = htons(M68K_RTS);
1630    
1631     // Relocate jump tables ($2000..)
1632     static const uint8 jump_tab_dat[] = {0x41, 0xfa, 0x00, 0x0e, 0x21, 0xc8, 0x20, 0x10, 0x4e, 0x75};
1633     if ((base = find_rom_data(0x3000, 0x6000, jump_tab_dat, sizeof(jump_tab_dat))) == 0) return false;
1634     D(bug("jump_tab %08lx\n", base));
1635     lp = (uint32 *)(ROM_BASE + base + 16);
1636     for (;;) {
1637     D(bug(" %08lx\n", (uint32)lp - ROM_BASE));
1638     while ((ntohl(*lp) & 0xff000000) == 0xff000000) {
1639     *lp = htonl((ntohl(*lp) & (ROM_SIZE-1)) + ROM_BASE);
1640     lp++;
1641     }
1642     while (!ntohl(*lp)) lp++;
1643     if (ntohl(*lp) != 0x41fa000e)
1644     break;
1645     lp += 4;
1646     }
1647    
1648     // Create SysZone at start of Mac RAM (SetSysAppZone, via 0x22a)
1649     static const uint8 sys_zone_dat[] = {0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x40, 0x00};
1650     if ((base = find_rom_data(0x600, 0x900, sys_zone_dat, sizeof(sys_zone_dat))) == 0) return false;
1651     D(bug("sys_zone %08lx\n", base));
1652     lp = (uint32 *)(ROM_BASE + base);
1653     *lp++ = htonl(RAMBase ? RAMBase : 0x3000);
1654     *lp = htonl(RAMBase ? RAMBase + 0x1800 : 0x4800);
1655    
1656     // Set boot stack at RAMBase+4MB and fix logical/physical RAM size (CompBootStack)
1657     // The RAM size fix must be done after InitMemMgr!
1658     static const uint8 boot_stack_dat[] = {0x08, 0x38, 0x00, 0x06, 0x24, 0x0b};
1659     if ((base = find_rom_data(0x580, 0x800, boot_stack_dat, sizeof(boot_stack_dat))) == 0) return false;
1660     D(bug("boot_stack %08lx\n", base));
1661     wp = (uint16 *)(ROM_BASE + base);
1662     *wp++ = htons(0x207c); // move.l #RAMBase+0x3ffffe,a0
1663     *wp++ = htons((RAMBase + 0x3ffffe) >> 16);
1664     *wp++ = htons((RAMBase + 0x3ffffe) & 0xffff);
1665     *wp++ = htons(M68K_EMUL_OP_FIX_MEMSIZE);
1666     *wp = htons(M68K_RTS);
1667    
1668     // Get PowerPC page size (InitVMemMgr, via 0x240)
1669     static const uint8 page_size_dat[] = {0x20, 0x30, 0x81, 0xf2, 0x5f, 0xff, 0xef, 0xd8, 0x00, 0x10};
1670     if ((base = find_rom_data(0xb000, 0x12000, page_size_dat, sizeof(page_size_dat))) == 0) return false;
1671     D(bug("page_size %08lx\n", base));
1672     wp = (uint16 *)(ROM_BASE + base);
1673     *wp++ = htons(0x203c); // move.l #$1000,d0
1674     *wp++ = htons(0);
1675     *wp++ = htons(0x1000);
1676     *wp++ = htons(M68K_NOP);
1677     *wp = htons(M68K_NOP);
1678    
1679     // Gestalt PowerPC page size, RAM size (InitGestalt, via 0x25c)
1680     static const uint8 page_size2_dat[] = {0x26, 0x79, 0x5f, 0xff, 0xef, 0xd8, 0x25, 0x6b, 0x00, 0x10, 0x00, 0x1e};
1681     if ((base = find_rom_data(0x50000, 0x70000, page_size2_dat, sizeof(page_size2_dat))) == 0) return false;
1682     D(bug("page_size2 %08lx\n", base));
1683     wp = (uint16 *)(ROM_BASE + base);
1684     *wp++ = htons(0x257c); // move.l #$1000,$1e(a2)
1685     *wp++ = htons(0);
1686     *wp++ = htons(0x1000);
1687     *wp++ = htons(0x001e);
1688     *wp++ = htons(0x157c); // move.b #PVR,$1d(a2)
1689     *wp++ = htons(PVR >> 16);
1690     *wp++ = htons(0x001d);
1691     *wp++ = htons(0x263c); // move.l #RAMSize,d3
1692     *wp++ = htons(RAMSize >> 16);
1693     *wp++ = htons(RAMSize & 0xffff);
1694     *wp++ = htons(M68K_NOP);
1695     *wp++ = htons(M68K_NOP);
1696     *wp = htons(M68K_NOP);
1697     if (ROMType == ROMTYPE_NEWWORLD)
1698     wp = (uint16 *)(ROM_BASE + base + 0x4a);
1699     else
1700     wp = (uint16 *)(ROM_BASE + base + 0x28);
1701     *wp++ = htons(M68K_NOP);
1702     *wp = htons(M68K_NOP);
1703    
1704     // Gestalt CPU/bus clock speed (InitGestalt, via 0x25c)
1705     if (ROMType == ROMTYPE_ZANZIBAR) {
1706     wp = (uint16 *)(ROM_BASE + 0x5d87a);
1707     *wp++ = htons(0x203c); // move.l #Hz,d0
1708     *wp++ = htons(BusClockSpeed >> 16);
1709     *wp++ = htons(BusClockSpeed & 0xffff);
1710     *wp++ = htons(M68K_NOP);
1711     *wp = htons(M68K_NOP);
1712     wp = (uint16 *)(ROM_BASE + 0x5d888);
1713     *wp++ = htons(0x203c); // move.l #Hz,d0
1714     *wp++ = htons(CPUClockSpeed >> 16);
1715     *wp++ = htons(CPUClockSpeed & 0xffff);
1716     *wp++ = htons(M68K_NOP);
1717     *wp = htons(M68K_NOP);
1718     }
1719    
1720     // Don't write to GC interrupt mask register (via 0x262)
1721     if (ROMType != ROMTYPE_NEWWORLD) {
1722     static const uint8 gc_mask_dat[] = {0x83, 0xa8, 0x00, 0x24, 0x4e, 0x71};
1723     if ((base = find_rom_data(0x13000, 0x20000, gc_mask_dat, sizeof(gc_mask_dat))) == 0) return false;
1724     D(bug("gc_mask %08lx\n", base));
1725     wp = (uint16 *)(ROM_BASE + base);
1726     *wp++ = htons(M68K_NOP);
1727     *wp = htons(M68K_NOP);
1728     wp = (uint16 *)(ROM_BASE + base + 0x40);
1729     *wp++ = htons(M68K_NOP);
1730     *wp = htons(M68K_NOP);
1731     wp = (uint16 *)(ROM_BASE + base + 0x78);
1732     *wp++ = htons(M68K_NOP);
1733     *wp = htons(M68K_NOP);
1734     wp = (uint16 *)(ROM_BASE + base + 0x96);
1735     *wp++ = htons(M68K_NOP);
1736     *wp = htons(M68K_NOP);
1737    
1738     static const uint8 gc_mask2_dat[] = {0x02, 0xa8, 0x00, 0x00, 0x00, 0x80, 0x00, 0x24};
1739     if ((base = find_rom_data(0x13000, 0x20000, gc_mask2_dat, sizeof(gc_mask2_dat))) == 0) return false;
1740     D(bug("gc_mask2 %08lx\n", base));
1741     wp = (uint16 *)(ROM_BASE + base);
1742     for (int i=0; i<5; i++) {
1743     *wp++ = htons(M68K_NOP);
1744     *wp++ = htons(M68K_NOP);
1745     *wp++ = htons(M68K_NOP);
1746     *wp++ = htons(M68K_NOP);
1747     wp += 2;
1748     }
1749     if (ROMType == ROMTYPE_ZANZIBAR) {
1750     for (int i=0; i<6; i++) {
1751     *wp++ = htons(M68K_NOP);
1752     *wp++ = htons(M68K_NOP);
1753     *wp++ = htons(M68K_NOP);
1754     *wp++ = htons(M68K_NOP);
1755     wp += 2;
1756     }
1757     }
1758     }
1759    
1760     // Don't initialize Cuda (via 0x274)
1761     static const uint8 cuda_init_dat[] = {0x08, 0xa9, 0x00, 0x04, 0x16, 0x00, 0x4e, 0x71, 0x13, 0x7c, 0x00, 0x84, 0x1c, 0x00, 0x4e, 0x71};
1762     if ((base = find_rom_data(0xa000, 0x12000, cuda_init_dat, sizeof(cuda_init_dat))) == 0) return false;
1763     D(bug("cuda_init %08lx\n", base));
1764     wp = (uint16 *)(ROM_BASE + base);
1765     *wp++ = htons(M68K_NOP);
1766     *wp++ = htons(M68K_NOP);
1767     *wp++ = htons(M68K_NOP);
1768     *wp++ = htons(M68K_NOP);
1769     *wp++ = htons(M68K_NOP);
1770     *wp++ = htons(M68K_NOP);
1771     *wp = htons(M68K_NOP);
1772    
1773     // Patch GetCPUSpeed (via 0x27a) (some ROMs have two of them)
1774     static const uint8 cpu_speed_dat[] = {0x20, 0x30, 0x81, 0xf2, 0x5f, 0xff, 0xef, 0xd8, 0x00, 0x04, 0x4c, 0x7c};
1775 gbeauche 1.4 if ((base = find_rom_data(0x6000, 0xa000, cpu_speed_dat, sizeof(cpu_speed_dat))) == 0) return false;
1776 cebix 1.1 D(bug("cpu_speed %08lx\n", base));
1777     wp = (uint16 *)(ROM_BASE + base);
1778     *wp++ = htons(0x203c); // move.l #(MHz<<16)|MHz,d0
1779     *wp++ = htons(CPUClockSpeed / 1000000);
1780     *wp++ = htons(CPUClockSpeed / 1000000);
1781     *wp = htons(M68K_RTS);
1782 gbeauche 1.4 if ((base = find_rom_data(base, 0xa000, cpu_speed_dat, sizeof(cpu_speed_dat))) != 0) {
1783 cebix 1.1 D(bug("cpu_speed2 %08lx\n", base));
1784     wp = (uint16 *)(ROM_BASE + base);
1785     *wp++ = htons(0x203c); // move.l #(MHz<<16)|MHz,d0
1786     *wp++ = htons(CPUClockSpeed / 1000000);
1787     *wp++ = htons(CPUClockSpeed / 1000000);
1788     *wp = htons(M68K_RTS);
1789     }
1790    
1791     // Don't poke VIA in InitTimeMgr (via 0x298)
1792     static const uint8 time_via_dat[] = {0x40, 0xe7, 0x00, 0x7c, 0x07, 0x00, 0x28, 0x78, 0x01, 0xd4, 0x43, 0xec, 0x10, 0x00};
1793     if ((base = find_rom_data(0x30000, 0x40000, time_via_dat, sizeof(time_via_dat))) == 0) return false;
1794     D(bug("time_via %08lx\n", base));
1795     wp = (uint16 *)(ROM_BASE + base);
1796     *wp++ = htons(0x4cdf); // movem.l (sp)+,d0-d5/a0-a4
1797     *wp++ = htons(0x1f3f);
1798     *wp = htons(M68K_RTS);
1799    
1800     // Don't read from 0xff800000 (Name Registry, Open Firmware?) (via 0x2a2)
1801     // Remove this if FE03 works!!
1802     static const uint8 open_firmware_dat[] = {0x2f, 0x79, 0xff, 0x80, 0x00, 0x00, 0x00, 0xfc};
1803     if ((base = find_rom_data(0x48000, 0x58000, open_firmware_dat, sizeof(open_firmware_dat))) == 0) return false;
1804     D(bug("open_firmware %08lx\n", base));
1805     wp = (uint16 *)(ROM_BASE + base);
1806     *wp++ = htons(0x2f7c); // move.l #deadbeef,0xfc(a7)
1807     *wp++ = htons(0xdead);
1808     *wp++ = htons(0xbeef);
1809     *wp = htons(0x00fc);
1810     wp = (uint16 *)(ROM_BASE + base + 0x1a);
1811     *wp++ = htons(M68K_NOP); // (FE03 opcode, tries to jump to 0xdeadbeef)
1812     *wp = htons(M68K_NOP);
1813    
1814     // Don't EnableExtCache (via 0x2b2)
1815     static const uint8 ext_cache2_dat[] = {0x4f, 0xef, 0xff, 0xec, 0x20, 0x4f, 0x10, 0xbc, 0x00, 0x01, 0x11, 0x7c, 0x00, 0x1b};
1816     if ((base = find_rom_data(0x13000, 0x20000, ext_cache2_dat, sizeof(ext_cache2_dat))) == 0) return false;
1817     D(bug("ext_cache2 %08lx\n", base));
1818     wp = (uint16 *)(ROM_BASE + base);
1819     *wp = htons(M68K_RTS);
1820    
1821     // Don't install Time Manager task for 60Hz interrupt (Enable60HzInts, via 0x2b8)
1822     if (ROMType == ROMTYPE_NEWWORLD) {
1823     static const uint8 tm_task_dat[] = {0x30, 0x3c, 0x4e, 0x2b, 0xa9, 0xc9};
1824     if ((base = find_rom_data(0x2e0, 0x320, tm_task_dat, sizeof(tm_task_dat))) == 0) return false;
1825     D(bug("tm_task %08lx\n", base));
1826     wp = (uint16 *)(ROM_BASE + base + 28);
1827     *wp++ = htons(M68K_NOP);
1828     *wp++ = htons(M68K_NOP);
1829     *wp++ = htons(M68K_NOP);
1830     *wp++ = htons(M68K_NOP);
1831     *wp++ = htons(M68K_NOP);
1832     *wp = htons(M68K_NOP);
1833     } else {
1834     static const uint8 tm_task_dat[] = {0x20, 0x3c, 0x73, 0x79, 0x73, 0x61};
1835     if ((base = find_rom_data(0x280, 0x300, tm_task_dat, sizeof(tm_task_dat))) == 0) return false;
1836     D(bug("tm_task %08lx\n", base));
1837     wp = (uint16 *)(ROM_BASE + base - 6);
1838     *wp++ = htons(M68K_NOP);
1839     *wp++ = htons(M68K_NOP);
1840     *wp = htons(M68K_NOP);
1841     }
1842    
1843     // Don't read PVR from 0x5fffef80 in DriverServicesLib (via 0x316)
1844     if (ROMType != ROMTYPE_NEWWORLD) {
1845     uint32 dsl_offset = find_rom_resource(FOURCC('n','l','i','b'), -16401);
1846     if (ROMType == ROMTYPE_ZANZIBAR) {
1847     static const uint8 dsl_pvr_dat[] = {0x40, 0x82, 0x00, 0x40, 0x38, 0x60, 0xef, 0x80, 0x3c, 0x63, 0x60, 0x00, 0x80, 0x83, 0x00, 0x00, 0x54, 0x84, 0x84, 0x3e};
1848     if ((base = find_rom_data(dsl_offset, dsl_offset + 0x6000, dsl_pvr_dat, sizeof(dsl_pvr_dat))) == 0) return false;
1849     } else {
1850     static const uint8 dsl_pvr_dat[] = {0x3b, 0xc3, 0x00, 0x00, 0x30, 0x84, 0xff, 0xa0, 0x40, 0x82, 0x00, 0x44, 0x80, 0x84, 0xef, 0xe0, 0x54, 0x84, 0x84, 0x3e};
1851     if ((base = find_rom_data(dsl_offset, dsl_offset + 0x6000, dsl_pvr_dat, sizeof(dsl_pvr_dat))) == 0) return false;
1852     }
1853     D(bug("dsl_pvr %08lx\n", base));
1854     lp = (uint32 *)(ROM_BASE + base + 12);
1855     *lp = htonl(0x3c800000 | (PVR >> 16)); // lis r4,PVR
1856    
1857     // Don't read bus clock from 0x5fffef88 in DriverServicesLib (via 0x316)
1858     if (ROMType == ROMTYPE_ZANZIBAR) {
1859     static const uint8 dsl_bus_dat[] = {0x81, 0x07, 0x00, 0x00, 0x39, 0x20, 0x42, 0x40, 0x81, 0x62, 0xff, 0x20};
1860     if ((base = find_rom_data(dsl_offset, dsl_offset + 0x6000, dsl_bus_dat, sizeof(dsl_bus_dat))) == 0) return false;
1861     D(bug("dsl_bus %08lx\n", base));
1862     lp = (uint32 *)(ROM_BASE + base);
1863     *lp = htonl(0x81000000 + XLM_BUS_CLOCK); // lwz r8,(bus clock speed)
1864     } else {
1865     static const uint8 dsl_bus_dat[] = {0x80, 0x83, 0xef, 0xe8, 0x80, 0x62, 0x00, 0x10, 0x7c, 0x04, 0x03, 0x96};
1866     if ((base = find_rom_data(dsl_offset, dsl_offset + 0x6000, dsl_bus_dat, sizeof(dsl_bus_dat))) == 0) return false;
1867     D(bug("dsl_bus %08lx\n", base));
1868     lp = (uint32 *)(ROM_BASE + base);
1869     *lp = htonl(0x80800000 + XLM_BUS_CLOCK); // lwz r4,(bus clock speed)
1870     }
1871     }
1872    
1873     // Don't open InterruptTreeTNT in MotherBoardHAL init in DriverServicesLib init
1874     if (ROMType == ROMTYPE_ZANZIBAR) {
1875     lp = (uint32 *)(ROM_BASE + find_rom_resource(FOURCC('n','l','i','b'), -16408) + 0x16c);
1876     *lp = htonl(0x38600000); // li r3,0
1877     }
1878    
1879     // Patch Name Registry
1880     static const uint8 name_reg_dat[] = {0x70, 0xff, 0xab, 0xeb};
1881     if ((base = find_rom_data(0x300, 0x380, name_reg_dat, sizeof(name_reg_dat))) == 0) return false;
1882     D(bug("name_reg %08lx\n", base));
1883     wp = (uint16 *)(ROM_BASE + base);
1884     *wp = htons(M68K_EMUL_OP_NAME_REGISTRY);
1885    
1886     #if DISABLE_SCSI
1887     // Fake SCSI Manager
1888     // Remove this if SCSI Manager works!!
1889     static const uint8 scsi_mgr_a_dat[] = {0x4e, 0x56, 0x00, 0x00, 0x20, 0x3c, 0x00, 0x00, 0x04, 0x0c, 0xa7, 0x1e};
1890     static const uint8 scsi_mgr_b_dat[] = {0x4e, 0x56, 0x00, 0x00, 0x2f, 0x0c, 0x20, 0x3c, 0x00, 0x00, 0x04, 0x0c, 0xa7, 0x1e};
1891     if ((base = find_rom_data(0x1c000, 0x28000, scsi_mgr_a_dat, sizeof(scsi_mgr_a_dat))) == 0) {
1892     if ((base = find_rom_data(0x1c000, 0x28000, scsi_mgr_b_dat, sizeof(scsi_mgr_b_dat))) == 0) return false;
1893     }
1894     D(bug("scsi_mgr %08lx\n", base));
1895     wp = (uint16 *)(ROM_BASE + base);
1896     *wp++ = htons(0x21fc); // move.l #xxx,0x624 (SCSIAtomic)
1897     *wp++ = htons((ROM_BASE + base + 18) >> 16);
1898     *wp++ = htons((ROM_BASE + base + 18) & 0xffff);
1899     *wp++ = htons(0x0624);
1900     *wp++ = htons(0x21fc); // move.l #xxx,0xe54 (SCSIDispatch)
1901     *wp++ = htons((ROM_BASE + base + 22) >> 16);
1902     *wp++ = htons((ROM_BASE + base + 22) & 0xffff);
1903     *wp++ = htons(0x0e54);
1904     *wp++ = htons(M68K_RTS);
1905     *wp++ = htons(M68K_EMUL_OP_SCSI_ATOMIC);
1906     *wp++ = htons(M68K_RTS);
1907     *wp++ = htons(M68K_EMUL_OP_SCSI_DISPATCH);
1908     *wp = htons(0x4ed0); // jmp (a0)
1909     wp = (uint16 *)(ROM_BASE + base + 0x20);
1910     *wp++ = htons(0x7000); // moveq #0,d0
1911     *wp = htons(M68K_RTS);
1912     #endif
1913    
1914     #if DISABLE_SCSI
1915     // Don't access SCSI variables
1916     // Remove this if SCSI Manager works!!
1917     if (ROMType == ROMTYPE_NEWWORLD) {
1918     static const uint8 scsi_var_dat[] = {0x70, 0x01, 0xa0, 0x89, 0x4a, 0x6e, 0xfe, 0xac, 0x4f, 0xef, 0x00, 0x10, 0x66, 0x00};
1919     if ((base = find_rom_data(0x1f500, 0x1f600, scsi_var_dat, sizeof(scsi_var_dat))) != 0) {
1920     D(bug("scsi_var %08lx\n", base));
1921     wp = (uint16 *)(ROM_BASE + base + 12);
1922     *wp = htons(0x6000); // bra
1923     }
1924    
1925     static const uint8 scsi_var2_dat[] = {0x4e, 0x56, 0xfc, 0x58, 0x48, 0xe7, 0x1f, 0x38};
1926     if ((base = find_rom_data(0x1f700, 0x1f800, scsi_var2_dat, sizeof(scsi_var2_dat))) != 0) {
1927     D(bug("scsi_var2 %08lx\n", base));
1928     wp = (uint16 *)(ROM_BASE + base);
1929     *wp++ = htons(0x7000); // moveq #0,d0
1930     *wp = htons(M68K_RTS); // bra
1931     }
1932     }
1933     #endif
1934    
1935     // Don't wait in ADBInit (via 0x36c)
1936     static const uint8 adb_init_dat[] = {0x08, 0x2b, 0x00, 0x05, 0x01, 0x5d, 0x66, 0xf8};
1937     if ((base = find_rom_data(0x31000, 0x3d000, adb_init_dat, sizeof(adb_init_dat))) == 0) return false;
1938     D(bug("adb_init %08lx\n", base));
1939     wp = (uint16 *)(ROM_BASE + base + 6);
1940     *wp = htons(M68K_NOP);
1941    
1942     // Modify check in InitResources() so that addresses >0x80000000 work
1943     static const uint8 init_res_dat[] = {0x4a, 0xb8, 0x0a, 0x50, 0x6e, 0x20};
1944     if ((base = find_rom_data(0x78000, 0x8c000, init_res_dat, sizeof(init_res_dat))) == 0) return false;
1945     D(bug("init_res %08lx\n", base));
1946     bp = (uint8 *)(ROM_BASE + base + 4);
1947     *bp = 0x66;
1948    
1949     // Modify vCheckLoad() so that we can patch resources (68k Resource Manager)
1950     static const uint8 check_load_dat[] = {0x20, 0x78, 0x07, 0xf0, 0x4e, 0xd0};
1951     if ((base = find_rom_data(0x78000, 0x8c000, check_load_dat, sizeof(check_load_dat))) == 0) return false;
1952     D(bug("check_load %08lx\n", base));
1953     wp = (uint16 *)(ROM_BASE + base);
1954     *wp++ = htons(M68K_JMP);
1955     *wp++ = htons((ROM_BASE + CHECK_LOAD_PATCH_SPACE) >> 16);
1956     *wp = htons((ROM_BASE + CHECK_LOAD_PATCH_SPACE) & 0xffff);
1957     wp = (uint16 *)(ROM_BASE + CHECK_LOAD_PATCH_SPACE);
1958     *wp++ = htons(0x2f03); // move.l d3,-(a7)
1959     *wp++ = htons(0x2078); // move.l $07f0,a0
1960     *wp++ = htons(0x07f0);
1961     *wp++ = htons(M68K_JSR_A0);
1962     *wp++ = htons(M68K_EMUL_OP_CHECKLOAD);
1963     *wp = htons(M68K_RTS);
1964    
1965     // Replace .Sony driver
1966     sony_offset = find_rom_resource(FOURCC('D','R','V','R'), 4);
1967     if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_NEWWORLD)
1968     sony_offset = find_rom_resource(FOURCC('D','R','V','R'), 4, true); // First DRVR 4 is .MFMFloppy
1969     if (sony_offset == 0) {
1970     sony_offset = find_rom_resource(FOURCC('n','d','r','v'), -20196); // NewWorld 1.6 has "PCFloppy" ndrv
1971     if (sony_offset == 0)
1972     return false;
1973     lp = (uint32 *)(ROM_BASE + rsrc_ptr + 8);
1974     *lp = htonl(FOURCC('D','R','V','R'));
1975     wp = (uint16 *)(ROM_BASE + rsrc_ptr + 12);
1976     *wp = htons(4);
1977     }
1978     D(bug("sony_offset %08lx\n", sony_offset));
1979     memcpy((void *)(ROM_BASE + sony_offset), sony_driver, sizeof(sony_driver));
1980    
1981     // Install .Disk and .AppleCD drivers
1982     memcpy((void *)(ROM_BASE + sony_offset + 0x100), disk_driver, sizeof(disk_driver));
1983     memcpy((void *)(ROM_BASE + sony_offset + 0x200), cdrom_driver, sizeof(cdrom_driver));
1984    
1985     // Install serial drivers
1986 gbeauche 1.9 memcpy_powerpc_code((void *)(ROM_BASE + sony_offset + 0x300), ain_driver, sizeof(ain_driver));
1987     memcpy_powerpc_code((void *)(ROM_BASE + sony_offset + 0x400), aout_driver, sizeof(aout_driver));
1988     memcpy_powerpc_code((void *)(ROM_BASE + sony_offset + 0x500), bin_driver, sizeof(bin_driver));
1989     memcpy_powerpc_code((void *)(ROM_BASE + sony_offset + 0x600), bout_driver, sizeof(bout_driver));
1990 cebix 1.1
1991     // Copy icons to ROM
1992     SonyDiskIconAddr = ROM_BASE + sony_offset + 0x800;
1993     memcpy((void *)(ROM_BASE + sony_offset + 0x800), SonyDiskIcon, sizeof(SonyDiskIcon));
1994     SonyDriveIconAddr = ROM_BASE + sony_offset + 0xa00;
1995     memcpy((void *)(ROM_BASE + sony_offset + 0xa00), SonyDriveIcon, sizeof(SonyDriveIcon));
1996     DiskIconAddr = ROM_BASE + sony_offset + 0xc00;
1997     memcpy((void *)(ROM_BASE + sony_offset + 0xc00), DiskIcon, sizeof(DiskIcon));
1998     CDROMIconAddr = ROM_BASE + sony_offset + 0xe00;
1999     memcpy((void *)(ROM_BASE + sony_offset + 0xe00), CDROMIcon, sizeof(CDROMIcon));
2000    
2001     // Patch driver install routine
2002     static const uint8 drvr_install_dat[] = {0xa7, 0x1e, 0x21, 0xc8, 0x01, 0x1c, 0x4e, 0x75};
2003     if ((base = find_rom_data(0xb00, 0xd00, drvr_install_dat, sizeof(drvr_install_dat))) == 0) return false;
2004     D(bug("drvr_install %08lx\n", base));
2005     wp = (uint16 *)(ROM_BASE + base + 8);
2006     *wp++ = htons(M68K_EMUL_OP_INSTALL_DRIVERS);
2007     *wp = htons(M68K_RTS);
2008    
2009     // Don't install serial drivers from ROM
2010     if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_NEWWORLD) {
2011     wp = (uint16 *)(ROM_BASE + find_rom_resource(FOURCC('S','E','R','D'), 0));
2012     *wp = htons(M68K_RTS);
2013     } else {
2014     wp = (uint16 *)(ROM_BASE + find_rom_resource(FOURCC('s','l','0','5'), 2) + 0xc4);
2015     *wp++ = htons(M68K_NOP);
2016     *wp++ = htons(M68K_NOP);
2017     *wp++ = htons(M68K_NOP);
2018     *wp++ = htons(M68K_NOP);
2019     *wp = htons(0x7000); // moveq #0,d0
2020     wp = (uint16 *)(ROM_BASE + find_rom_resource(FOURCC('s','l','0','5'), 2) + 0x8ee);
2021     *wp = htons(M68K_NOP);
2022     }
2023     uint32 nsrd_offset = find_rom_resource(FOURCC('n','s','r','d'), 1);
2024     if (nsrd_offset) {
2025     lp = (uint32 *)(ROM_BASE + rsrc_ptr + 8);
2026     *lp = htonl(FOURCC('x','s','r','d'));
2027     }
2028    
2029     // Replace ADBOp()
2030     memcpy((void *)(ROM_BASE + find_rom_trap(0xa07c)), adbop_patch, sizeof(adbop_patch));
2031    
2032     // Replace Time Manager
2033     wp = (uint16 *)(ROM_BASE + find_rom_trap(0xa058));
2034     *wp++ = htons(M68K_EMUL_OP_INSTIME);
2035     *wp = htons(M68K_RTS);
2036     wp = (uint16 *)(ROM_BASE + find_rom_trap(0xa059));
2037     *wp++ = htons(0x40e7); // move sr,-(sp)
2038     *wp++ = htons(0x007c); // ori #$0700,sr
2039     *wp++ = htons(0x0700);
2040     *wp++ = htons(M68K_EMUL_OP_RMVTIME);
2041     *wp++ = htons(0x46df); // move (sp)+,sr
2042     *wp = htons(M68K_RTS);
2043     wp = (uint16 *)(ROM_BASE + find_rom_trap(0xa05a));
2044     *wp++ = htons(0x40e7); // move sr,-(sp)
2045     *wp++ = htons(0x007c); // ori #$0700,sr
2046     *wp++ = htons(0x0700);
2047     *wp++ = htons(M68K_EMUL_OP_PRIMETIME);
2048     *wp++ = htons(0x46df); // move (sp)+,sr
2049     *wp = htons(M68K_RTS);
2050     wp = (uint16 *)(ROM_BASE + find_rom_trap(0xa093));
2051     *wp++ = htons(M68K_EMUL_OP_MICROSECONDS);
2052     *wp = htons(M68K_RTS);
2053    
2054     // Disable Egret Manager
2055     static const uint8 egret_dat[] = {0x2f, 0x30, 0x81, 0xe2, 0x20, 0x10, 0x00, 0x18};
2056     if ((base = find_rom_data(0xa000, 0x10000, egret_dat, sizeof(egret_dat))) == 0) return false;
2057     D(bug("egret %08lx\n", base));
2058     wp = (uint16 *)(ROM_BASE + base);
2059     *wp++ = htons(0x7000);
2060     *wp = htons(M68K_RTS);
2061    
2062     // Don't call FE0A opcode in Shutdown Manager
2063     static const uint8 shutdown_dat[] = {0x40, 0xe7, 0x00, 0x7c, 0x07, 0x00, 0x48, 0xe7, 0x3f, 0x00, 0x2c, 0x00, 0x2e, 0x01};
2064     if ((base = find_rom_data(0x30000, 0x40000, shutdown_dat, sizeof(shutdown_dat))) == 0) return false;
2065     D(bug("shutdown %08lx\n", base));
2066     wp = (uint16 *)(ROM_BASE + base);
2067     if (ROMType == ROMTYPE_ZANZIBAR)
2068     *wp = htons(M68K_RTS);
2069 gbeauche 1.6 else if (ntohs(wp[-4]) == 0x61ff)
2070     *wp = htons(M68K_RTS);
2071     else if (ntohs(wp[-2]) == 0x6700)
2072 cebix 1.1 wp[-2] = htons(0x6000); // bra
2073    
2074     // Patch PowerOff()
2075     wp = (uint16 *)(ROM_BASE + find_rom_trap(0xa05b)); // PowerOff()
2076     *wp = htons(M68K_EMUL_RETURN);
2077    
2078     // Patch VIA interrupt handler
2079     static const uint8 via_int_dat[] = {0x70, 0x7f, 0xc0, 0x29, 0x1a, 0x00, 0xc0, 0x29, 0x1c, 0x00};
2080     if ((base = find_rom_data(0x13000, 0x1c000, via_int_dat, sizeof(via_int_dat))) == 0) return false;
2081     D(bug("via_int %08lx\n", base));
2082     uint32 level1_int = ROM_BASE + base;
2083     wp = (uint16 *)level1_int; // Level 1 handler
2084     *wp++ = htons(0x7002); // moveq #2,d0 (60Hz interrupt)
2085     *wp++ = htons(M68K_NOP);
2086     *wp++ = htons(M68K_NOP);
2087     *wp++ = htons(M68K_NOP);
2088     *wp = htons(M68K_NOP);
2089    
2090     static const uint8 via_int2_dat[] = {0x13, 0x7c, 0x00, 0x02, 0x1a, 0x00, 0x4e, 0x71, 0x52, 0xb8, 0x01, 0x6a};
2091     if ((base = find_rom_data(0x10000, 0x18000, via_int2_dat, sizeof(via_int2_dat))) == 0) return false;
2092     D(bug("via_int2 %08lx\n", base));
2093     wp = (uint16 *)(ROM_BASE + base); // 60Hz handler
2094     *wp++ = htons(M68K_EMUL_OP_IRQ);
2095     *wp++ = htons(0x4a80); // tst.l d0
2096     *wp++ = htons(0x6700); // beq xxx
2097     *wp = htons(0xffe8);
2098    
2099     if (ROMType == ROMTYPE_NEWWORLD) {
2100     static const uint8 via_int3_dat[] = {0x48, 0xe7, 0xf0, 0xf0, 0x76, 0x01, 0x60, 0x26};
2101 gbeauche 1.4 if ((base = find_rom_data(0x15000, 0x19000, via_int3_dat, sizeof(via_int3_dat))) == 0) return false;
2102 cebix 1.1 D(bug("via_int3 %08lx\n", base));
2103     wp = (uint16 *)(ROM_BASE + base); // CHRP level 1 handler
2104     *wp++ = htons(M68K_JMP);
2105     *wp++ = htons((level1_int - 12) >> 16);
2106     *wp = htons((level1_int - 12) & 0xffff);
2107     }
2108    
2109     // Patch PutScrap() for clipboard exchange with host OS
2110     uint32 put_scrap = find_rom_trap(0xa9fe); // PutScrap()
2111     wp = (uint16 *)(ROM_BASE + PUT_SCRAP_PATCH_SPACE);
2112     *wp++ = htons(M68K_EMUL_OP_PUT_SCRAP);
2113     *wp++ = htons(M68K_JMP);
2114     *wp++ = htons((ROM_BASE + put_scrap) >> 16);
2115     *wp++ = htons((ROM_BASE + put_scrap) & 0xffff);
2116     lp = (uint32 *)(ROM_BASE + 0x22);
2117     lp = (uint32 *)(ROM_BASE + ntohl(*lp));
2118     lp[0xa9fe & 0x3ff] = htonl(PUT_SCRAP_PATCH_SPACE);
2119    
2120     // Patch GetScrap() for clipboard exchange with host OS
2121     uint32 get_scrap = find_rom_trap(0xa9fd); // GetScrap()
2122     wp = (uint16 *)(ROM_BASE + GET_SCRAP_PATCH_SPACE);
2123     *wp++ = htons(M68K_EMUL_OP_GET_SCRAP);
2124     *wp++ = htons(M68K_JMP);
2125     *wp++ = htons((ROM_BASE + get_scrap) >> 16);
2126     *wp++ = htons((ROM_BASE + get_scrap) & 0xffff);
2127     lp = (uint32 *)(ROM_BASE + 0x22);
2128     lp = (uint32 *)(ROM_BASE + ntohl(*lp));
2129     lp[0xa9fd & 0x3ff] = htonl(GET_SCRAP_PATCH_SPACE);
2130    
2131     #if __BEOS__
2132     // Patch SynchIdleTime()
2133     if (PrefsFindBool("idlewait")) {
2134     wp = (uint16 *)(ROM_BASE + find_rom_trap(0xabf7) + 4); // SynchIdleTime()
2135     D(bug("SynchIdleTime at %08lx\n", wp));
2136     if (ntohs(*wp) == 0x2078) {
2137     *wp++ = htons(M68K_EMUL_OP_IDLE_TIME);
2138     *wp = htons(M68K_NOP);
2139     } else {
2140     D(bug("SynchIdleTime patch not installed\n"));
2141     }
2142     }
2143     #endif
2144    
2145     // Construct list of all sifters used by sound components in ROM
2146     D(bug("Searching for sound components with type sdev in ROM\n"));
2147     uint32 thing = find_rom_resource(FOURCC('t','h','n','g'));
2148     while (thing) {
2149     thing += ROM_BASE;
2150     D(bug(" found %c%c%c%c %c%c%c%c\n", ReadMacInt8(thing), ReadMacInt8(thing + 1), ReadMacInt8(thing + 2), ReadMacInt8(thing + 3), ReadMacInt8(thing + 4), ReadMacInt8(thing + 5), ReadMacInt8(thing + 6), ReadMacInt8(thing + 7)));
2151     if (ReadMacInt32(thing) == FOURCC('s','d','e','v') && ReadMacInt32(thing + 4) == FOURCC('s','i','n','g')) {
2152     WriteMacInt32(thing + 4, FOURCC('a','w','g','c'));
2153     D(bug(" found sdev component at offset %08x in ROM\n", thing));
2154     AddSifter(ReadMacInt32(thing + componentResType), ReadMacInt16(thing + componentResID));
2155     if (ReadMacInt32(thing + componentPFCount))
2156     AddSifter(ReadMacInt32(thing + componentPFResType), ReadMacInt16(thing + componentPFResID));
2157     }
2158     thing = find_rom_resource(FOURCC('t','h','n','g'), 4711, true);
2159     }
2160    
2161     // Patch component code
2162     D(bug("Patching sifters in ROM\n"));
2163     for (int i=0; i<num_sifters; i++) {
2164     if ((thing = find_rom_resource(sifter_list[i].type, sifter_list[i].id)) != 0) {
2165     D(bug(" patching type %08x, id %d\n", sifter_list[i].type, sifter_list[i].id));
2166     // Install 68k glue code
2167     uint16 *wp = (uint16 *)(ROM_BASE + thing);
2168     *wp++ = htons(0x4e56); *wp++ = htons(0x0000); // link a6,#0
2169     *wp++ = htons(0x48e7); *wp++ = htons(0x8018); // movem.l d0/a3-a4,-(a7)
2170     *wp++ = htons(0x266e); *wp++ = htons(0x000c); // movea.l $c(a6),a3
2171     *wp++ = htons(0x286e); *wp++ = htons(0x0008); // movea.l $8(a6),a4
2172     *wp++ = htons(M68K_EMUL_OP_AUDIO_DISPATCH);
2173     *wp++ = htons(0x2d40); *wp++ = htons(0x0010); // move.l d0,$10(a6)
2174     *wp++ = htons(0x4cdf); *wp++ = htons(0x1801); // movem.l (a7)+,d0/a3-a4
2175     *wp++ = htons(0x4e5e); // unlk a6
2176     *wp++ = htons(0x4e74); *wp++ = htons(0x0008); // rtd #8
2177     }
2178     }
2179     return true;
2180     }
2181    
2182    
2183     /*
2184     * Install .Sony, disk and CD-ROM drivers
2185     */
2186    
2187     void InstallDrivers(void)
2188     {
2189     D(bug("Installing drivers...\n"));
2190     M68kRegisters r;
2191     uint8 pb[SIZEOF_IOParam];
2192 gbeauche 1.7
2193 gbeauche 1.5 // Install floppy driver
2194     if (ROMType == ROMTYPE_NEWWORLD) {
2195    
2196     // Force installation of floppy driver with NewWorld ROMs
2197     r.a[0] = ROM_BASE + sony_offset;
2198     r.d[0] = (uint32)SonyRefNum;
2199     Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem()
2200     r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~SonyRefNum * 4); // Get driver handle from Unit Table
2201     Execute68kTrap(0xa029, &r); // HLock()
2202     uint32 dce = ReadMacInt32(r.a[0]);
2203     WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset);
2204     WriteMacInt16(dce + dCtlFlags, SonyDriverFlags);
2205     }
2206 gbeauche 1.8
2207     #if DISABLE_SCSI && 0
2208     // Fake SCSIGlobals
2209     static const uint8 fake_scsi_globals[32] = {0,};
2210     WriteMacInt32(0xc0c, (uint32)fake_scsi_globals);
2211     #endif
2212 gbeauche 1.5
2213 cebix 1.1 // Open .Sony driver
2214     WriteMacInt8((uint32)pb + ioPermssn, 0);
2215     WriteMacInt32((uint32)pb + ioNamePtr, (uint32)"\005.Sony");
2216     r.a[0] = (uint32)pb;
2217     Execute68kTrap(0xa000, &r); // Open()
2218    
2219     // Install disk driver
2220     r.a[0] = ROM_BASE + sony_offset + 0x100;
2221     r.d[0] = (uint32)DiskRefNum;
2222     Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem()
2223     r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~DiskRefNum * 4); // Get driver handle from Unit Table
2224     Execute68kTrap(0xa029, &r); // HLock()
2225     uint32 dce = ReadMacInt32(r.a[0]);
2226     WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x100);
2227     WriteMacInt16(dce + dCtlFlags, DiskDriverFlags);
2228    
2229     // Open disk driver
2230     WriteMacInt32((uint32)pb + ioNamePtr, (uint32)"\005.Disk");
2231     r.a[0] = (uint32)pb;
2232     Execute68kTrap(0xa000, &r); // Open()
2233    
2234     // Install CD-ROM driver unless nocdrom option given
2235     if (!PrefsFindBool("nocdrom")) {
2236    
2237     // Install CD-ROM driver
2238     r.a[0] = ROM_BASE + sony_offset + 0x200;
2239     r.d[0] = (uint32)CDROMRefNum;
2240     Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem()
2241     r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~CDROMRefNum * 4); // Get driver handle from Unit Table
2242     Execute68kTrap(0xa029, &r); // HLock()
2243     dce = ReadMacInt32(r.a[0]);
2244     WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x200);
2245     WriteMacInt16(dce + dCtlFlags, CDROMDriverFlags);
2246    
2247     // Open CD-ROM driver
2248     WriteMacInt32((uint32)pb + ioNamePtr, (uint32)"\010.AppleCD");
2249     r.a[0] = (uint32)pb;
2250     Execute68kTrap(0xa000, &r); // Open()
2251     }
2252    
2253     // Install serial drivers
2254     r.a[0] = ROM_BASE + sony_offset + 0x300;
2255     r.d[0] = (uint32)-6;
2256     Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem()
2257     r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~(-6) * 4); // Get driver handle from Unit Table
2258     Execute68kTrap(0xa029, &r); // HLock()
2259     dce = ReadMacInt32(r.a[0]);
2260     WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x300);
2261     WriteMacInt16(dce + dCtlFlags, 0x4d00);
2262    
2263     r.a[0] = ROM_BASE + sony_offset + 0x400;
2264     r.d[0] = (uint32)-7;
2265     Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem()
2266     r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~(-7) * 4); // Get driver handle from Unit Table
2267     Execute68kTrap(0xa029, &r); // HLock()
2268     dce = ReadMacInt32(r.a[0]);
2269     WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x400);
2270     WriteMacInt16(dce + dCtlFlags, 0x4e00);
2271    
2272     r.a[0] = ROM_BASE + sony_offset + 0x500;
2273     r.d[0] = (uint32)-8;
2274     Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem()
2275     r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~(-8) * 4); // Get driver handle from Unit Table
2276     Execute68kTrap(0xa029, &r); // HLock()
2277     dce = ReadMacInt32(r.a[0]);
2278     WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x500);
2279     WriteMacInt16(dce + dCtlFlags, 0x4d00);
2280    
2281     r.a[0] = ROM_BASE + sony_offset + 0x600;
2282     r.d[0] = (uint32)-9;
2283     Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem()
2284     r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~(-9) * 4); // Get driver handle from Unit Table
2285     Execute68kTrap(0xa029, &r); // HLock()
2286     dce = ReadMacInt32(r.a[0]);
2287     WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x600);
2288     WriteMacInt16(dce + dCtlFlags, 0x4e00);
2289     }