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root/cebix/SheepShaver/src/rom_patches.cpp
Revision: 1.30
Committed: 2004-06-22T17:10:06Z (19 years, 10 months ago) by gbeauche
Branch: MAIN
Changes since 1.29: +0 -21 lines
Log Message: 
Don't handle XLM_IRQ_NEST atomically in emulated mode. That's useless since
this variable is modified only within a single thread and interrupts are
not handled asynchronously.

File Contents

# User Rev Content
1 cebix 1.1 /*
2     * rom_patches.cpp - ROM patches
3     *
4 cebix 1.24 * SheepShaver (C) 1997-2004 Christian Bauer and Marc Hellwig
5 cebix 1.1 *
6     * This program is free software; you can redistribute it and/or modify
7     * it under the terms of the GNU General Public License as published by
8     * the Free Software Foundation; either version 2 of the License, or
9     * (at your option) any later version.
10     *
11     * This program is distributed in the hope that it will be useful,
12     * but WITHOUT ANY WARRANTY; without even the implied warranty of
13     * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14     * GNU General Public License for more details.
15     *
16     * You should have received a copy of the GNU General Public License
17     * along with this program; if not, write to the Free Software
18     * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19     */
20    
21     /*
22     * TODO:
23     * IRQ_NEST must be handled atomically
24     * Don't use r1 in extra routines
25     */
26    
27     #include <string.h>
28    
29     #include "sysdeps.h"
30     #include "rom_patches.h"
31     #include "main.h"
32     #include "prefs.h"
33     #include "cpu_emulation.h"
34     #include "emul_op.h"
35     #include "xlowmem.h"
36     #include "sony.h"
37     #include "disk.h"
38     #include "cdrom.h"
39     #include "audio.h"
40     #include "audio_defs.h"
41     #include "serial.h"
42     #include "macos_util.h"
43 gbeauche 1.18 #include "thunks.h"
44 cebix 1.1
45     #define DEBUG 0
46     #include "debug.h"
47    
48    
49     // 68k breakpoint address
50     //#define M68K_BREAK_POINT 0x29e0 // BootMe
51     //#define M68K_BREAK_POINT 0x2a1e // Boot block code returned
52     //#define M68K_BREAK_POINT 0x3150 // CritError
53     //#define M68K_BREAK_POINT 0x187ce // Unimplemented trap
54    
55     // PowerPC breakpoint address
56     //#define POWERPC_BREAK_POINT 0x36e6c0 // 68k emulator start
57    
58     #define DISABLE_SCSI 1
59    
60    
61     // Other ROM addresses
62 gbeauche 1.17 const uint32 CHECK_LOAD_PATCH_SPACE = 0x2fcf00;
63     const uint32 PUT_SCRAP_PATCH_SPACE = 0x2fcf80;
64     const uint32 GET_SCRAP_PATCH_SPACE = 0x2fcfc0;
65 gbeauche 1.21 const uint32 ADDR_MAP_PATCH_SPACE = 0x2fd100;
66 cebix 1.1
67     // Global variables
68     int ROMType; // ROM type
69     static uint32 sony_offset; // Offset of .Sony driver resource
70    
71     // Prototypes
72     static bool patch_nanokernel_boot(void);
73     static bool patch_68k_emul(void);
74     static bool patch_nanokernel(void);
75     static bool patch_68k(void);
76    
77    
78 gbeauche 1.2 // Decode LZSS data
79     static void decode_lzss(const uint8 *src, uint8 *dest, int size)
80     {
81     char dict[0x1000];
82     int run_mask = 0, dict_idx = 0xfee;
83     for (;;) {
84     if (run_mask < 0x100) {
85     // Start new run
86     if (--size < 0)
87     break;
88     run_mask = *src++ | 0xff00;
89     }
90     bool bit = run_mask & 1;
91     run_mask >>= 1;
92     if (bit) {
93     // Verbatim copy
94     if (--size < 0)
95     break;
96     int c = *src++;
97     dict[dict_idx++] = c;
98     *dest++ = c;
99     dict_idx &= 0xfff;
100     } else {
101     // Copy from dictionary
102     if (--size < 0)
103     break;
104     int idx = *src++;
105     if (--size < 0)
106     break;
107     int cnt = *src++;
108     idx |= (cnt << 4) & 0xf00;
109     cnt = (cnt & 0x0f) + 3;
110     while (cnt--) {
111     char c = dict[idx++];
112     dict[dict_idx++] = c;
113     *dest++ = c;
114     idx &= 0xfff;
115     dict_idx &= 0xfff;
116     }
117     }
118     }
119     }
120    
121     // Decode parcels of ROM image (MacOS 9.X and even earlier)
122     void decode_parcels(const uint8 *src, uint8 *dest, int size)
123     {
124     uint32 parcel_offset = 0x14;
125     D(bug("Offset Type Name\n"));
126     while (parcel_offset != 0) {
127     const uint32 *parcel_data = (uint32 *)(src + parcel_offset);
128 gbeauche 1.3 uint32 next_offset = ntohl(parcel_data[0]);
129 gbeauche 1.2 uint32 parcel_type = ntohl(parcel_data[1]);
130     D(bug("%08x %c%c%c%c %s\n", parcel_offset,
131     (parcel_type >> 24) & 0xff, (parcel_type >> 16) & 0xff,
132     (parcel_type >> 8) & 0xff, parcel_type & 0xff, &parcel_data[6]));
133     if (parcel_type == FOURCC('r','o','m',' ')) {
134     uint32 lzss_offset = ntohl(parcel_data[2]);
135 gbeauche 1.16 uint32 lzss_size = ((uintptr)src + next_offset) - ((uintptr)parcel_data + lzss_offset);
136 gbeauche 1.2 decode_lzss((uint8 *)parcel_data + lzss_offset, dest, lzss_size);
137     }
138 gbeauche 1.3 parcel_offset = next_offset;
139 gbeauche 1.2 }
140     }
141    
142    
143     /*
144     * Decode ROM image, 4 MB plain images or NewWorld images
145     */
146    
147     bool DecodeROM(uint8 *data, uint32 size)
148     {
149     if (size == ROM_SIZE) {
150     // Plain ROM image
151     memcpy((void *)ROM_BASE, data, ROM_SIZE);
152     return true;
153     }
154     else if (strncmp((char *)data, "<CHRP-BOOT>", 11) == 0) {
155     // CHRP compressed ROM image
156     uint32 image_offset, image_size;
157     bool decode_info_ok = false;
158    
159     char *s = strstr((char *)data, "constant lzss-offset");
160     if (s != NULL) {
161     // Probably a plain LZSS compressed ROM image
162     if (sscanf(s - 7, "%06x", &image_offset) == 1) {
163     s = strstr((char *)data, "constant lzss-size");
164     if (s != NULL && (sscanf(s - 7, "%06x", &image_size) == 1))
165     decode_info_ok = true;
166     }
167     }
168     else {
169     // Probably a MacOS 9.2.x ROM image
170     s = strstr((char *)data, "constant parcels-offset");
171     if (s != NULL) {
172     if (sscanf(s - 7, "%06x", &image_offset) == 1) {
173     s = strstr((char *)data, "constant parcels-size");
174     if (s != NULL && (sscanf(s - 7, "%06x", &image_size) == 1))
175     decode_info_ok = true;
176     }
177     }
178     }
179    
180     // No valid information to decode the ROM found?
181     if (!decode_info_ok)
182     return false;
183    
184     // Check signature, this could be a parcels-based ROM image
185     uint32 rom_signature = ntohl(*(uint32 *)(data + image_offset));
186     if (rom_signature == FOURCC('p','r','c','l')) {
187     D(bug("Offset of parcels data: %08x\n", image_offset));
188     D(bug("Size of parcels data: %08x\n", image_size));
189     decode_parcels(data + image_offset, (uint8 *)ROM_BASE, image_size);
190     }
191     else {
192     D(bug("Offset of compressed data: %08x\n", image_offset));
193     D(bug("Size of compressed data: %08x\n", image_size));
194     decode_lzss(data + image_offset, (uint8 *)ROM_BASE, image_size);
195     }
196     return true;
197     }
198     return false;
199     }
200    
201    
202 cebix 1.1 /*
203     * Search ROM for byte string, return ROM offset (or 0)
204     */
205    
206     static uint32 find_rom_data(uint32 start, uint32 end, const uint8 *data, uint32 data_len)
207     {
208     uint32 ofs = start;
209     while (ofs < end) {
210     if (!memcmp((void *)(ROM_BASE + ofs), data, data_len))
211     return ofs;
212     ofs++;
213     }
214     return 0;
215     }
216    
217    
218     /*
219     * Search ROM resource by type/ID, return ROM offset of resource data
220     */
221    
222     static uint32 rsrc_ptr = 0;
223    
224     // id = 4711 means "find any ID"
225     static uint32 find_rom_resource(uint32 s_type, int16 s_id = 4711, bool cont = false)
226     {
227     uint32 *lp = (uint32 *)(ROM_BASE + 0x1a);
228     uint32 x = ntohl(*lp);
229     uint8 *bp = (uint8 *)(ROM_BASE + x + 5);
230     uint32 header_size = *bp;
231    
232     if (!cont)
233     rsrc_ptr = x;
234     else if (rsrc_ptr == 0)
235     return 0;
236    
237     for (;;) {
238     lp = (uint32 *)(ROM_BASE + rsrc_ptr);
239     rsrc_ptr = ntohl(*lp);
240     if (rsrc_ptr == 0)
241     break;
242    
243     rsrc_ptr += header_size;
244    
245     lp = (uint32 *)(ROM_BASE + rsrc_ptr + 4);
246     uint32 data = ntohl(*lp); lp++;
247     uint32 type = ntohl(*lp); lp++;
248     int16 id = ntohs(*(int16 *)lp);
249     if (type == s_type && (id == s_id || s_id == 4711))
250     return data;
251     }
252     return 0;
253     }
254    
255    
256     /*
257     * Search offset of A-Trap routine in ROM
258     */
259    
260     static uint32 find_rom_trap(uint16 trap)
261     {
262     uint32 *lp = (uint32 *)(ROM_BASE + 0x22);
263     lp = (uint32 *)(ROM_BASE + ntohl(*lp));
264    
265     if (trap > 0xa800)
266     return ntohl(lp[trap & 0x3ff]);
267     else
268     return ntohl(lp[(trap & 0xff) + 0x400]);
269     }
270    
271    
272     /*
273 gbeauche 1.20 * Return target of branch instruction specified at ADDR, or 0 if
274     * there is no such instruction
275     */
276    
277     static uint32 powerpc_branch_target(uintptr addr)
278     {
279     uint32 opcode = ntohl(*(uint32 *)addr);
280     uint32 primop = opcode >> 26;
281     uint32 target = 0;
282    
283     if (primop == 18) { // Branch
284     target = opcode & 0x3fffffc;
285     if (target & 0x2000000)
286     target |= 0xfc000000;
287     if ((opcode & 2) == 0)
288     target += addr;
289     }
290     else if (primop == 16) { // Branch Conditional
291     target = (int32)(int16)(opcode & 0xfffc);
292     if ((opcode & 2) == 0)
293     target += addr;
294     }
295     return target;
296     }
297    
298    
299     /*
300     * Search ROM for instruction branching to target address, return 0 if none found
301     */
302    
303     static uint32 find_rom_powerpc_branch(uint32 start, uint32 end, uint32 target)
304     {
305     for (uint32 addr = start; addr < end; addr += 4) {
306     if (powerpc_branch_target(ROM_BASE + addr) == ROM_BASE + target)
307     return addr;
308     }
309     return 0;
310     }
311    
312    
313     /*
314 gbeauche 1.21 * Check that requested ROM patch space is really available
315     */
316    
317     static bool check_rom_patch_space(uint32 base, uint32 size)
318     {
319     size = (size + 3) & -4;
320     for (int i = 0; i < size; i += 4) {
321     uint32 x = ntohl(*(uint32 *)(ROM_BASE + base + i));
322     if (x != 0x6b636b63 && x != 0)
323     return false;
324     }
325     return true;
326     }
327    
328    
329     /*
330 cebix 1.1 * List of audio sifters installed in ROM and System file
331     */
332    
333     struct sift_entry {
334     uint32 type;
335     int16 id;
336     };
337     static sift_entry sifter_list[32];
338     static int num_sifters;
339    
340     void AddSifter(uint32 type, int16 id)
341     {
342     if (FindSifter(type, id))
343     return;
344     D(bug(" adding sifter type %c%c%c%c (%08x), id %d\n", type >> 24, (type >> 16) & 0xff, (type >> 8) & 0xff, type & 0xff, type, id));
345     sifter_list[num_sifters].type = type;
346     sifter_list[num_sifters].id = id;
347     num_sifters++;
348     }
349    
350     bool FindSifter(uint32 type, int16 id)
351     {
352     for (int i=0; i<num_sifters; i++) {
353     if (sifter_list[i].type == type && sifter_list[i].id == id)
354     return true;
355     }
356     return false;
357     }
358    
359    
360     /*
361     * Driver stubs
362     */
363    
364     static const uint8 sony_driver[] = { // Replacement for .Sony driver
365     // Driver header
366     SonyDriverFlags >> 8, SonyDriverFlags & 0xff, 0, 0, 0, 0, 0, 0,
367     0x00, 0x18, // Open() offset
368     0x00, 0x1c, // Prime() offset
369     0x00, 0x20, // Control() offset
370     0x00, 0x2c, // Status() offset
371     0x00, 0x52, // Close() offset
372     0x05, 0x2e, 0x53, 0x6f, 0x6e, 0x79, // ".Sony"
373    
374     // Open()
375     M68K_EMUL_OP_SONY_OPEN >> 8, M68K_EMUL_OP_SONY_OPEN & 0xff,
376     0x4e, 0x75, // rts
377    
378     // Prime()
379     M68K_EMUL_OP_SONY_PRIME >> 8, M68K_EMUL_OP_SONY_PRIME & 0xff,
380     0x60, 0x0e, // bra IOReturn
381    
382     // Control()
383     M68K_EMUL_OP_SONY_CONTROL >> 8, M68K_EMUL_OP_SONY_CONTROL & 0xff,
384     0x0c, 0x68, 0x00, 0x01, 0x00, 0x1a, // cmp.w #1,$1a(a0)
385     0x66, 0x04, // bne IOReturn
386     0x4e, 0x75, // rts
387    
388     // Status()
389     M68K_EMUL_OP_SONY_STATUS >> 8, M68K_EMUL_OP_SONY_STATUS & 0xff,
390    
391     // IOReturn
392     0x32, 0x28, 0x00, 0x06, // move.w 6(a0),d1
393     0x08, 0x01, 0x00, 0x09, // btst #9,d1
394     0x67, 0x0c, // beq 1
395     0x4a, 0x40, // tst.w d0
396     0x6f, 0x02, // ble 2
397     0x42, 0x40, // clr.w d0
398     0x31, 0x40, 0x00, 0x10, //2 move.w d0,$10(a0)
399     0x4e, 0x75, // rts
400     0x4a, 0x40, //1 tst.w d0
401     0x6f, 0x04, // ble 3
402     0x42, 0x40, // clr.w d0
403     0x4e, 0x75, // rts
404     0x2f, 0x38, 0x08, 0xfc, //3 move.l $8fc,-(sp)
405     0x4e, 0x75, // rts
406    
407     // Close()
408     0x70, 0xe8, // moveq #-24,d0
409     0x4e, 0x75 // rts
410     };
411    
412     static const uint8 disk_driver[] = { // Generic disk driver
413     // Driver header
414     DiskDriverFlags >> 8, DiskDriverFlags & 0xff, 0, 0, 0, 0, 0, 0,
415     0x00, 0x18, // Open() offset
416     0x00, 0x1c, // Prime() offset
417     0x00, 0x20, // Control() offset
418     0x00, 0x2c, // Status() offset
419     0x00, 0x52, // Close() offset
420     0x05, 0x2e, 0x44, 0x69, 0x73, 0x6b, // ".Disk"
421    
422     // Open()
423     M68K_EMUL_OP_DISK_OPEN >> 8, M68K_EMUL_OP_DISK_OPEN & 0xff,
424     0x4e, 0x75, // rts
425    
426     // Prime()
427     M68K_EMUL_OP_DISK_PRIME >> 8, M68K_EMUL_OP_DISK_PRIME & 0xff,
428     0x60, 0x0e, // bra IOReturn
429    
430     // Control()
431     M68K_EMUL_OP_DISK_CONTROL >> 8, M68K_EMUL_OP_DISK_CONTROL & 0xff,
432     0x0c, 0x68, 0x00, 0x01, 0x00, 0x1a, // cmp.w #1,$1a(a0)
433     0x66, 0x04, // bne IOReturn
434     0x4e, 0x75, // rts
435    
436     // Status()
437     M68K_EMUL_OP_DISK_STATUS >> 8, M68K_EMUL_OP_DISK_STATUS & 0xff,
438    
439     // IOReturn
440     0x32, 0x28, 0x00, 0x06, // move.w 6(a0),d1
441     0x08, 0x01, 0x00, 0x09, // btst #9,d1
442     0x67, 0x0c, // beq 1
443     0x4a, 0x40, // tst.w d0
444     0x6f, 0x02, // ble 2
445     0x42, 0x40, // clr.w d0
446     0x31, 0x40, 0x00, 0x10, //2 move.w d0,$10(a0)
447     0x4e, 0x75, // rts
448     0x4a, 0x40, //1 tst.w d0
449     0x6f, 0x04, // ble 3
450     0x42, 0x40, // clr.w d0
451     0x4e, 0x75, // rts
452     0x2f, 0x38, 0x08, 0xfc, //3 move.l $8fc,-(sp)
453     0x4e, 0x75, // rts
454    
455     // Close()
456     0x70, 0xe8, // moveq #-24,d0
457     0x4e, 0x75 // rts
458     };
459    
460     static const uint8 cdrom_driver[] = { // CD-ROM driver
461     // Driver header
462     CDROMDriverFlags >> 8, CDROMDriverFlags & 0xff, 0, 0, 0, 0, 0, 0,
463     0x00, 0x1c, // Open() offset
464     0x00, 0x20, // Prime() offset
465     0x00, 0x24, // Control() offset
466     0x00, 0x30, // Status() offset
467     0x00, 0x56, // Close() offset
468     0x08, 0x2e, 0x41, 0x70, 0x70, 0x6c, 0x65, 0x43, 0x44, 0x00, // ".AppleCD"
469    
470     // Open()
471     M68K_EMUL_OP_CDROM_OPEN >> 8, M68K_EMUL_OP_CDROM_OPEN & 0xff,
472     0x4e, 0x75, // rts
473    
474     // Prime()
475     M68K_EMUL_OP_CDROM_PRIME >> 8, M68K_EMUL_OP_CDROM_PRIME & 0xff,
476     0x60, 0x0e, // bra IOReturn
477    
478     // Control()
479     M68K_EMUL_OP_CDROM_CONTROL >> 8, M68K_EMUL_OP_CDROM_CONTROL & 0xff,
480     0x0c, 0x68, 0x00, 0x01, 0x00, 0x1a, // cmp.w #1,$1a(a0)
481     0x66, 0x04, // bne IOReturn
482     0x4e, 0x75, // rts
483    
484     // Status()
485     M68K_EMUL_OP_CDROM_STATUS >> 8, M68K_EMUL_OP_CDROM_STATUS & 0xff,
486    
487     // IOReturn
488     0x32, 0x28, 0x00, 0x06, // move.w 6(a0),d1
489     0x08, 0x01, 0x00, 0x09, // btst #9,d1
490     0x67, 0x0c, // beq 1
491     0x4a, 0x40, // tst.w d0
492     0x6f, 0x02, // ble 2
493     0x42, 0x40, // clr.w d0
494     0x31, 0x40, 0x00, 0x10, //2 move.w d0,$10(a0)
495     0x4e, 0x75, // rts
496     0x4a, 0x40, //1 tst.w d0
497     0x6f, 0x04, // ble 3
498     0x42, 0x40, // clr.w d0
499     0x4e, 0x75, // rts
500     0x2f, 0x38, 0x08, 0xfc, //3 move.l $8fc,-(sp)
501     0x4e, 0x75, // rts
502    
503     // Close()
504     0x70, 0xe8, // moveq #-24,d0
505     0x4e, 0x75 // rts
506     };
507    
508 gbeauche 1.18 static uint32 long_ptr;
509    
510     static void SetLongBase(uint32 addr)
511     {
512     long_ptr = addr;
513     }
514    
515     static void Long(uint32 value)
516     {
517     WriteMacInt32(long_ptr, value);
518     long_ptr += 4;
519     }
520    
521     static void gen_ain_driver(uintptr addr)
522     {
523     SetLongBase(addr);
524 cebix 1.1
525 gbeauche 1.18 // .AIn driver header
526     Long(0x4d000000); Long(0x00000000);
527     Long(0x00200040); Long(0x00600080);
528     Long(0x00a0042e); Long(0x41496e00);
529     Long(0x00000000); Long(0x00000000);
530     Long(0xaafe0700); Long(0x00000000);
531     Long(0x00000000); Long(0x00179822);
532     Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_NOTHING));
533     Long(0x00000000); Long(0x00000000);
534     Long(0xaafe0700); Long(0x00000000);
535     Long(0x00000000); Long(0x00179822);
536     Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_PRIME_IN));
537     Long(0x00000000); Long(0x00000000);
538     Long(0xaafe0700); Long(0x00000000);
539     Long(0x00000000); Long(0x00179822);
540     Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CONTROL));
541     Long(0x00000000); Long(0x00000000);
542     Long(0xaafe0700); Long(0x00000000);
543     Long(0x00000000); Long(0x00179822);
544     Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_STATUS));
545     Long(0x00000000); Long(0x00000000);
546     Long(0xaafe0700); Long(0x00000000);
547     Long(0x00000000); Long(0x00179822);
548     Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_NOTHING));
549     Long(0x00000000); Long(0x00000000);
550 cebix 1.1 };
551    
552 gbeauche 1.18 static void gen_aout_driver(uintptr addr)
553     {
554     SetLongBase(addr);
555    
556     // .AOut driver header
557     Long(0x4d000000); Long(0x00000000);
558     Long(0x00200040); Long(0x00600080);
559     Long(0x00a0052e); Long(0x414f7574);
560     Long(0x00000000); Long(0x00000000);
561     Long(0xaafe0700); Long(0x00000000);
562     Long(0x00000000); Long(0x00179822);
563     Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_OPEN));
564     Long(0x00000000); Long(0x00000000);
565     Long(0xaafe0700); Long(0x00000000);
566     Long(0x00000000); Long(0x00179822);
567     Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_PRIME_OUT));
568     Long(0x00000000); Long(0x00000000);
569     Long(0xaafe0700); Long(0x00000000);
570     Long(0x00000000); Long(0x00179822);
571     Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CONTROL));
572     Long(0x00000000); Long(0x00000000);
573     Long(0xaafe0700); Long(0x00000000);
574     Long(0x00000000); Long(0x00179822);
575     Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_STATUS));
576     Long(0x00000000); Long(0x00000000);
577     Long(0xaafe0700); Long(0x00000000);
578     Long(0x00000000); Long(0x00179822);
579     Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CLOSE));
580     Long(0x00000000); Long(0x00000000);
581 cebix 1.1 };
582    
583 gbeauche 1.18 static void gen_bin_driver(uintptr addr)
584     {
585     SetLongBase(addr);
586    
587     // .BIn driver header
588     Long(0x4d000000); Long(0x00000000);
589     Long(0x00200040); Long(0x00600080);
590     Long(0x00a0042e); Long(0x42496e00);
591     Long(0x00000000); Long(0x00000000);
592     Long(0xaafe0700); Long(0x00000000);
593     Long(0x00000000); Long(0x00179822);
594     Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_NOTHING));
595     Long(0x00000000); Long(0x00000000);
596     Long(0xaafe0700); Long(0x00000000);
597     Long(0x00000000); Long(0x00179822);
598     Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_PRIME_IN));
599     Long(0x00000000); Long(0x00000000);
600     Long(0xaafe0700); Long(0x00000000);
601     Long(0x00000000); Long(0x00179822);
602     Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CONTROL));
603     Long(0x00000000); Long(0x00000000);
604     Long(0xaafe0700); Long(0x00000000);
605     Long(0x00000000); Long(0x00179822);
606     Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_STATUS));
607     Long(0x00000000); Long(0x00000000);
608     Long(0xaafe0700); Long(0x00000000);
609     Long(0x00000000); Long(0x00179822);
610     Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_NOTHING));
611     Long(0x00000000); Long(0x00000000);
612 cebix 1.1 };
613    
614 gbeauche 1.18 static void gen_bout_driver(uintptr addr)
615     {
616     SetLongBase(addr);
617    
618     // .BOut driver header
619     Long(0x4d000000); Long(0x00000000);
620     Long(0x00200040); Long(0x00600080);
621     Long(0x00a0052e); Long(0x424f7574);
622     Long(0x00000000); Long(0x00000000);
623     Long(0xaafe0700); Long(0x00000000);
624     Long(0x00000000); Long(0x00179822);
625     Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_OPEN));
626     Long(0x00000000); Long(0x00000000);
627     Long(0xaafe0700); Long(0x00000000);
628     Long(0x00000000); Long(0x00179822);
629     Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_PRIME_OUT));
630     Long(0x00000000); Long(0x00000000);
631     Long(0xaafe0700); Long(0x00000000);
632     Long(0x00000000); Long(0x00179822);
633     Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CONTROL));
634     Long(0x00000000); Long(0x00000000);
635     Long(0xaafe0700); Long(0x00000000);
636     Long(0x00000000); Long(0x00179822);
637     Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_STATUS));
638     Long(0x00000000); Long(0x00000000);
639     Long(0xaafe0700); Long(0x00000000);
640     Long(0x00000000); Long(0x00179822);
641     Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CLOSE));
642     Long(0x00000000); Long(0x00000000);
643 cebix 1.1 };
644    
645     static const uint8 adbop_patch[] = { // Call ADBOp() completion procedure
646     // The completion procedure may call ADBOp() again!
647     0x40, 0xe7, // move sr,-(sp)
648     0x00, 0x7c, 0x07, 0x00, // ori #$0700,sr
649     M68K_EMUL_OP_ADBOP >> 8, M68K_EMUL_OP_ADBOP & 0xff,
650     0x48, 0xe7, 0x70, 0xf0, // movem.l d1-d3/a0-a3,-(sp)
651     0x26, 0x48, // move.l a0,a3
652     0x4a, 0xab, 0x00, 0x04, // tst.l 4(a3)
653     0x67, 0x00, 0x00, 0x18, // beq 1
654     0x20, 0x53, // move.l (a3),a0
655     0x22, 0x6b, 0x00, 0x04, // move.l 4(a3),a1
656     0x24, 0x6b, 0x00, 0x08, // move.l 8(a3),a2
657     0x26, 0x78, 0x0c, 0xf8, // move.l $cf8,a3
658     0x4e, 0x91, // jsr (a1)
659     0x70, 0x00, // moveq #0,d0
660     0x60, 0x00, 0x00, 0x04, // bra 2
661     0x70, 0xff, //1 moveq #-1,d0
662     0x4c, 0xdf, 0x0f, 0x0e, //2 movem.l (sp)+,d1-d3/a0-a3
663     0x46, 0xdf, // move (sp)+,sr
664     0x4e, 0x75 // rts
665     };
666    
667    
668     /*
669 gbeauche 1.9 * Copy PowerPC code to ROM image and reverse bytes if necessary
670     */
671    
672     static inline void memcpy_powerpc_code(void *dst, const void *src, size_t len)
673     {
674     #ifdef WORDS_BIGENDIAN
675     (void)memcpy(dst, src, len);
676     #else
677     uint32 *d = (uint32 *)dst;
678     uint32 *s = (uint32 *)src;
679     for (int i = 0; i < len/4; i++)
680     d[i] = htonl(s[i]);
681     #endif
682     }
683    
684    
685     /*
686 cebix 1.1 * Install ROM patches (RAMBase and KernelDataAddr must be set)
687     */
688    
689     bool PatchROM(void)
690     {
691     // Print ROM info
692     D(bug("Checksum: %08lx\n", ntohl(*(uint32 *)ROM_BASE)));
693     D(bug("Version: %04x\n", ntohs(*(uint16 *)(ROM_BASE + 8))));
694     D(bug("Sub Version: %04x\n", ntohs(*(uint16 *)(ROM_BASE + 18))));
695     D(bug("Nanokernel ID: %s\n", (char *)ROM_BASE + 0x30d064));
696     D(bug("Resource Map at %08lx\n", ntohl(*(uint32 *)(ROM_BASE + 26))));
697     D(bug("Trap Tables at %08lx\n\n", ntohl(*(uint32 *)(ROM_BASE + 34))));
698    
699     // Detect ROM type
700     if (!memcmp((void *)(ROM_BASE + 0x30d064), "Boot TNT", 8))
701     ROMType = ROMTYPE_TNT;
702     else if (!memcmp((void *)(ROM_BASE + 0x30d064), "Boot Alchemy", 12))
703     ROMType = ROMTYPE_ALCHEMY;
704     else if (!memcmp((void *)(ROM_BASE + 0x30d064), "Boot Zanzibar", 13))
705     ROMType = ROMTYPE_ZANZIBAR;
706     else if (!memcmp((void *)(ROM_BASE + 0x30d064), "Boot Gazelle", 12))
707     ROMType = ROMTYPE_GAZELLE;
708 gbeauche 1.11 else if (!memcmp((void *)(ROM_BASE + 0x30d064), "Boot Gossamer", 13))
709     ROMType = ROMTYPE_GOSSAMER;
710 cebix 1.1 else if (!memcmp((void *)(ROM_BASE + 0x30d064), "NewWorld", 8))
711     ROMType = ROMTYPE_NEWWORLD;
712     else
713     return false;
714    
715 gbeauche 1.14 // Check that other ROM addresses point to really free regions
716 gbeauche 1.21 if (!check_rom_patch_space(CHECK_LOAD_PATCH_SPACE, 0x40))
717 gbeauche 1.14 return false;
718 gbeauche 1.21 if (!check_rom_patch_space(PUT_SCRAP_PATCH_SPACE, 0x40))
719 gbeauche 1.14 return false;
720 gbeauche 1.21 if (!check_rom_patch_space(GET_SCRAP_PATCH_SPACE, 0x40))
721 gbeauche 1.14 return false;
722 gbeauche 1.21 if (!check_rom_patch_space(ADDR_MAP_PATCH_SPACE - 10 * 4, 0x100))
723 gbeauche 1.14 return false;
724    
725 cebix 1.1 // Apply patches
726     if (!patch_nanokernel_boot()) return false;
727     if (!patch_68k_emul()) return false;
728     if (!patch_nanokernel()) return false;
729     if (!patch_68k()) return false;
730    
731     #ifdef M68K_BREAK_POINT
732     // Install 68k breakpoint
733     uint16 *wp = (uint16 *)(ROM_BASE + M68K_BREAK_POINT);
734     *wp++ = htons(M68K_EMUL_BREAK);
735     *wp = htons(M68K_EMUL_RETURN);
736     #endif
737    
738     #ifdef POWERPC_BREAK_POINT
739     // Install PowerPC breakpoint
740     uint32 *lp = (uint32 *)(ROM_BASE + POWERPC_BREAK_POINT);
741     *lp = htonl(0);
742     #endif
743    
744     // Copy 68k emulator to 2MB boundary
745     memcpy((void *)(ROM_BASE + ROM_SIZE), (void *)(ROM_BASE + ROM_SIZE - 0x100000), 0x100000);
746     return true;
747     }
748    
749    
750     /*
751     * Nanokernel boot routine patches
752     */
753    
754     static bool patch_nanokernel_boot(void)
755     {
756     uint32 *lp;
757 gbeauche 1.20 uint32 base, loc;
758 cebix 1.1
759     // ROM boot structure patches
760     lp = (uint32 *)(ROM_BASE + 0x30d000);
761     lp[0x9c >> 2] = htonl(KernelDataAddr); // LA_InfoRecord
762     lp[0xa0 >> 2] = htonl(KernelDataAddr); // LA_KernelData
763     lp[0xa4 >> 2] = htonl(KernelDataAddr + 0x1000); // LA_EmulatorData
764     lp[0xa8 >> 2] = htonl(ROM_BASE + 0x480000); // LA_DispatchTable
765     lp[0xac >> 2] = htonl(ROM_BASE + 0x460000); // LA_EmulatorCode
766     lp[0x360 >> 2] = htonl(0); // Physical RAM base (? on NewWorld ROM, this contains -1)
767     lp[0xfd8 >> 2] = htonl(ROM_BASE + 0x2a); // 68k reset vector
768    
769     // Skip SR/BAT/SDR init
770 gbeauche 1.20 loc = 0x310000;
771 gbeauche 1.11 if (ROMType == ROMTYPE_GAZELLE || ROMType == ROMTYPE_GOSSAMER || ROMType == ROMTYPE_NEWWORLD) {
772 gbeauche 1.20 lp = (uint32 *)(ROM_BASE + loc);
773 cebix 1.1 *lp++ = htonl(POWERPC_NOP);
774     *lp = htonl(0x38000000);
775     }
776 gbeauche 1.20 static const uint8 sr_init_dat[] = {0x35, 0x4a, 0xff, 0xfc, 0x7d, 0x86, 0x50, 0x2e};
777     if ((base = find_rom_data(0x3101b0, 0x3105b0, sr_init_dat, sizeof(sr_init_dat))) == 0) return false;
778     D(bug("sr_init %08lx\n", base));
779     lp = (uint32 *)(ROM_BASE + loc + 8);
780     *lp = htonl(0x48000000 | ((base - loc - 8) & 0x3fffffc)); // b ROM_BASE+0x3101b0
781     lp = (uint32 *)(ROM_BASE + base);
782 cebix 1.1 *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA); // lwz r1,(pointer to Kernel Data)
783     *lp++ = htonl(0x3da0dead); // lis r13,0xdead (start of kernel memory)
784     *lp++ = htonl(0x3dc00010); // lis r14,0x0010 (size of page table)
785     *lp = htonl(0x3de00010); // lis r15,0x0010 (size of kernel memory)
786    
787     // Don't read PVR
788 gbeauche 1.20 static const uint8 pvr_read_dat[] = {0x7d, 0x9f, 0x42, 0xa6};
789     if ((base = find_rom_data(0x3103b0, 0x3108b0, pvr_read_dat, sizeof(pvr_read_dat))) == 0) return false;
790     D(bug("pvr_read %08lx\n", base));
791     lp = (uint32 *)(ROM_BASE + base);
792 cebix 1.1 *lp = htonl(0x81800000 + XLM_PVR); // lwz r12,(theoretical PVR)
793    
794     // Set CPU specific data (even if ROM doesn't have support for that CPU)
795     if (ntohl(lp[6]) != 0x2c0c0001)
796     return false;
797     uint32 ofs = ntohl(lp[7]) & 0xffff;
798     D(bug("ofs %08lx\n", ofs));
799     lp[8] = htonl((ntohl(lp[8]) & 0xffff) | 0x48000000); // beq -> b
800 gbeauche 1.20 loc = (ntohl(lp[8]) & 0xffff) + (uint32)(lp+8) - ROM_BASE;
801 cebix 1.1 D(bug("loc %08lx\n", loc));
802     lp = (uint32 *)(ROM_BASE + ofs + 0x310000);
803     switch (PVR >> 16) {
804     case 1: // 601
805     lp[0] = htonl(0x1000); // Page size
806     lp[1] = htonl(0x8000); // Data cache size
807     lp[2] = htonl(0x8000); // Inst cache size
808     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
809     lp[4] = htonl(0x00010040); // Unified caches/Inst cache line size
810     lp[5] = htonl(0x00400020); // Data cache line size/Data cache block size touch
811     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
812     lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc
813     lp[8] = htonl(0x01000002); // TLB total size/TLB assoc
814     break;
815     case 3: // 603
816     lp[0] = htonl(0x1000); // Page size
817     lp[1] = htonl(0x2000); // Data cache size
818     lp[2] = htonl(0x2000); // Inst cache size
819     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
820     lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
821     lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
822     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
823     lp[7] = htonl(0x00020002); // Inst cache assoc/Data cache assoc
824     lp[8] = htonl(0x00400002); // TLB total size/TLB assoc
825     break;
826     case 4: // 604
827     lp[0] = htonl(0x1000); // Page size
828     lp[1] = htonl(0x4000); // Data cache size
829     lp[2] = htonl(0x4000); // Inst cache size
830     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
831     lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
832     lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
833     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
834     lp[7] = htonl(0x00040004); // Inst cache assoc/Data cache assoc
835     lp[8] = htonl(0x00800002); // TLB total size/TLB assoc
836     break;
837     // case 5: // 740?
838     case 6: // 603e
839     case 7: // 603ev
840     lp[0] = htonl(0x1000); // Page size
841     lp[1] = htonl(0x4000); // Data cache size
842     lp[2] = htonl(0x4000); // Inst cache size
843     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
844     lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
845     lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
846     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
847     lp[7] = htonl(0x00040004); // Inst cache assoc/Data cache assoc
848     lp[8] = htonl(0x00400002); // TLB total size/TLB assoc
849     break;
850     case 8: // 750
851     lp[0] = htonl(0x1000); // Page size
852     lp[1] = htonl(0x8000); // Data cache size
853     lp[2] = htonl(0x8000); // Inst cache size
854     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
855     lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
856     lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
857     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
858     lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc
859     lp[8] = htonl(0x00800002); // TLB total size/TLB assoc
860     break;
861     case 9: // 604e
862     case 10: // 604ev5
863     lp[0] = htonl(0x1000); // Page size
864     lp[1] = htonl(0x8000); // Data cache size
865     lp[2] = htonl(0x8000); // Inst cache size
866     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
867     lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
868     lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
869     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
870     lp[7] = htonl(0x00040004); // Inst cache assoc/Data cache assoc
871     lp[8] = htonl(0x00800002); // TLB total size/TLB assoc
872     break;
873     // case 11: // X704?
874 gbeauche 1.26 case 12: // 7400, 7410
875     case 0x800c:
876 cebix 1.1 lp[0] = htonl(0x1000); // Page size
877     lp[1] = htonl(0x8000); // Data cache size
878     lp[2] = htonl(0x8000); // Inst cache size
879     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
880     lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
881     lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
882     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
883     lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc
884     lp[8] = htonl(0x00800002); // TLB total size/TLB assoc
885     break;
886     case 13: // ???
887     lp[0] = htonl(0x1000); // Page size
888     lp[1] = htonl(0x8000); // Data cache size
889     lp[2] = htonl(0x8000); // Inst cache size
890     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
891     lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
892     lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
893     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
894     lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc
895     lp[8] = htonl(0x01000004); // TLB total size/TLB assoc
896     break;
897     // case 50: // 821
898     // case 80: // 860
899     case 96: // ???
900     lp[0] = htonl(0x1000); // Page size
901     lp[1] = htonl(0x8000); // Data cache size
902     lp[2] = htonl(0x8000); // Inst cache size
903     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
904     lp[4] = htonl(0x00010020); // Unified caches/Inst cache line size
905     lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
906     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
907     lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc
908     lp[8] = htonl(0x00800004); // TLB total size/TLB assoc
909 gbeauche 1.25 break;
910 cebix 1.1 default:
911     printf("WARNING: Unknown CPU type\n");
912     break;
913     }
914    
915     // Don't set SPRG3, don't test MQ
916 gbeauche 1.20 static const uint8 sprg3_mq_dat[] = {0x7d, 0x13, 0x43, 0xa6, 0x3d, 0x00, 0x00, 0x04, 0x7d, 0x00, 0x03, 0xa6, 0x39, 0x00, 0x00, 0x00, 0x7d, 0x00, 0x02, 0xa6};
917     if ((base = find_rom_data(loc + 0x20, loc + 0x60, sprg3_mq_dat, sizeof(sprg3_mq_dat))) == 0) return false;
918     D(bug("sprg3/mq %08lx\n", base));
919     lp = (uint32 *)(ROM_BASE + base);
920     lp[0] = htonl(POWERPC_NOP);
921     lp[2] = htonl(POWERPC_NOP);
922     lp[4] = htonl(POWERPC_NOP);
923 cebix 1.1
924     // Don't read MSR
925 gbeauche 1.20 static const uint8 msr_dat[] = {0x7d, 0xc0, 0x00, 0xa6};
926     if ((base = find_rom_data(loc + 0x40, loc + 0x80, msr_dat, sizeof(msr_dat))) == 0) return false;
927     D(bug("msr %08lx\n", base));
928     lp = (uint32 *)(ROM_BASE + base);
929 cebix 1.1 *lp = htonl(0x39c00000); // li r14,0
930    
931     // Don't write to DEC
932     lp = (uint32 *)(ROM_BASE + loc + 0x70);
933     *lp++ = htonl(POWERPC_NOP);
934     loc = (ntohl(lp[0]) & 0xffff) + (uint32)lp - ROM_BASE;
935     D(bug("loc %08lx\n", loc));
936    
937     // Don't set SPRG3
938 gbeauche 1.20 static const uint8 sprg3_dat[] = {0x39, 0x21, 0x03, 0x60, 0x7d, 0x33, 0x43, 0xa6, 0x39, 0x01, 0x04, 0x20};
939     if ((base = find_rom_data(0x310000, 0x314000, sprg3_dat, sizeof(sprg3_dat))) == 0) return false;
940     D(bug("sprg3 %08lx\n", base + 4));
941     lp = (uint32 *)(ROM_BASE + base + 4);
942 cebix 1.1 *lp = htonl(POWERPC_NOP);
943    
944     // Don't read PVR
945 gbeauche 1.20 static const uint8 pvr_read2_dat[] = {0x7e, 0xff, 0x42, 0xa6, 0x56, 0xf7, 0x84, 0x3e};
946     if ((base = find_rom_data(0x310000, 0x320000, pvr_read2_dat, sizeof(pvr_read2_dat))) == 0) return false;
947     D(bug("pvr_read2 %08lx\n", base));
948     lp = (uint32 *)(ROM_BASE + base);
949 cebix 1.1 *lp = htonl(0x82e00000 + XLM_PVR); // lwz r23,(theoretical PVR)
950 gbeauche 1.20 if ((base = find_rom_data(base + 4, 0x320000, pvr_read2_dat, sizeof(pvr_read2_dat))) != 0) {
951     D(bug("pvr_read2 %08lx\n", base));
952     lp = (uint32 *)(ROM_BASE + base);
953 cebix 1.1 *lp = htonl(0x82e00000 + XLM_PVR); // lwz r23,(theoretical PVR)
954 gbeauche 1.20 }
955     static const uint8 pvr_read3_dat[] = {0x7e, 0x5f, 0x42, 0xa6, 0x56, 0x52, 0x84, 0x3e};
956     if ((base = find_rom_data(0x310000, 0x320000, pvr_read3_dat, sizeof(pvr_read3_dat))) != 0) {
957     D(bug("pvr_read3 %08lx\n", base));
958     lp = (uint32 *)(ROM_BASE + base);
959 cebix 1.1 *lp = htonl(0x82400000 + XLM_PVR); // lwz r18,(theoretical PVR)
960 gbeauche 1.20 }
961     static const uint8 pvr_read4_dat[] = {0x7d, 0x3f, 0x42, 0xa6, 0x55, 0x29, 0x84, 0x3e};
962     if ((base = find_rom_data(0x310000, 0x320000, pvr_read4_dat, sizeof(pvr_read4_dat))) != 0) {
963     D(bug("pvr_read4 %08lx\n", base));
964     lp = (uint32 *)(ROM_BASE + base);
965 gbeauche 1.4 *lp = htonl(0x81200000 + XLM_PVR); // lzw r9,(theoritical PVR)
966 gbeauche 1.20 }
967 cebix 1.1
968     // Don't read SDR1
969 gbeauche 1.20 static const uint8 sdr1_read_dat[] = {0x7d, 0x19, 0x02, 0xa6, 0x55, 0x16, 0x81, 0xde};
970     if ((base = find_rom_data(0x310000, 0x320000, sdr1_read_dat, sizeof(sdr1_read_dat))) == 0) return false;
971     D(bug("sdr1_read %08lx\n", base));
972     lp = (uint32 *)(ROM_BASE + base);
973 cebix 1.1 *lp++ = htonl(0x3d00dead); // lis r8,0xdead (pointer to page table)
974     *lp++ = htonl(0x3ec0001f); // lis r22,0x001f (size of page table)
975     *lp = htonl(POWERPC_NOP);
976    
977 gbeauche 1.20 // Don't clear page table, don't invalidate TLB
978     static const uint8 pgtb_clear_dat[] = {0x36, 0xd6, 0xff, 0xfc, 0x7e, 0xe8, 0xb1, 0x2e, 0x41, 0x81, 0xff, 0xf8};
979     if ((base = find_rom_data(0x310000, 0x320000, pgtb_clear_dat, sizeof(pgtb_clear_dat))) == 0) return false;
980     D(bug("pgtb_clear %08lx\n", base + 4));
981     lp = (uint32 *)(ROM_BASE + base + 4);
982 cebix 1.1 *lp = htonl(POWERPC_NOP);
983 gbeauche 1.20 D(bug("tblie %08lx\n", base + 12));
984     lp = (uint32 *)(ROM_BASE + base + 12);
985 cebix 1.1 *lp = htonl(POWERPC_NOP);
986    
987     // Don't create RAM descriptor table
988 gbeauche 1.20 static const uint8 desc_create_dat[] = {0x97, 0xfd, 0x00, 0x04, 0x3b, 0xff, 0x10, 0x00, 0x4b, 0xff, 0xff, 0xdc};
989     if ((base = find_rom_data(0x310000, 0x320000, desc_create_dat, sizeof(desc_create_dat))) == 0) return false;
990     D(bug("desc_create %08lx\n", base))
991     lp = (uint32 *)(ROM_BASE + base);
992 cebix 1.1 *lp = htonl(POWERPC_NOP);
993    
994     // Don't load SRs and BATs
995 gbeauche 1.20 static const uint8 sr_load[] = {0x7c, 0x00, 0x04, 0xac, 0x83, 0x9d, 0x00, 0x00, 0x93, 0x81, 0x05, 0xe8};
996     if ((loc = find_rom_data(0x310000, 0x320000, sr_load, sizeof(sr_load))) == 0) return false;
997     static const uint8 sr_load_caller[] = {0x3e, 0xd6, 0xff, 0xff, 0x41, 0x81, 0xff, 0xdc, 0xb2, 0xc8, 0x00, 0x02};
998     if ((base = find_rom_data(0x310000, 0x320000, sr_load_caller, sizeof(sr_load_caller))) == 0) return false;
999     if ((base = find_rom_powerpc_branch(base + 12, 0x320000, loc)) == 0) return false;
1000     D(bug("sr_load %08lx, called from %08lx\n", loc, base));
1001     lp = (uint32 *)(ROM_BASE + base);
1002 cebix 1.1 *lp = htonl(POWERPC_NOP);
1003    
1004     // Don't mess with SRs
1005 gbeauche 1.20 static const uint8 sr_load2_dat[] = {0x83, 0xa1, 0x05, 0xe8, 0x57, 0x7c, 0x3e, 0x78, 0x7f, 0xbd, 0xe0, 0x2e};
1006     if ((base = find_rom_data(0x310000, 0x320000, sr_load2_dat, sizeof(sr_load2_dat))) == 0) return false;
1007     D(bug("sr_load2 %08lx\n", base));
1008     lp = (uint32 *)(ROM_BASE + base);
1009 cebix 1.1 *lp = htonl(POWERPC_BLR);
1010    
1011     // Don't check performance monitor
1012 gbeauche 1.20 static const uint8 pm_check_dat[] = {0x7e, 0x58, 0xeb, 0xa6, 0x7e, 0x53, 0x90, 0xf8, 0x7e, 0x78, 0xea, 0xa6};
1013     if ((base = find_rom_data(0x310000, 0x320000, pm_check_dat, sizeof(pm_check_dat))) == 0) return false;
1014     D(bug("pm_check %08lx\n", base));
1015     lp = (uint32 *)(ROM_BASE + base);
1016    
1017     static const int spr_check_list[] = {
1018     952 /* mmcr0 */, 953 /* pmc1 */, 954 /* pmc2 */, 955 /* sia */,
1019     956 /* mmcr1 */, 957 /* pmc3 */, 958 /* pmc4 */, 959 /* sda */
1020     };
1021    
1022     for (int i = 0; i < sizeof(spr_check_list)/sizeof(spr_check_list[0]); i++) {
1023     int spr = spr_check_list[i];
1024     uint32 mtspr = 0x7e4003a6 | ((spr & 0x1f) << 16) | ((spr & 0x3e0) << 6);
1025     uint32 mfspr = 0x7e6002a6 | ((spr & 0x1f) << 16) | ((spr & 0x3e0) << 6);
1026     for (int ofs = 0; ofs < 64; ofs++) {
1027     if (ntohl(lp[ofs]) == mtspr) {
1028     if (ntohl(lp[ofs + 2]) != mfspr)
1029     return false;
1030     D(bug(" SPR%d %08lx\n", spr, base + 4*ofs));
1031     lp[ofs] = htonl(POWERPC_NOP);
1032     lp[ofs + 2] = htonl(POWERPC_NOP);
1033     }
1034     }
1035     }
1036 cebix 1.1
1037     // Jump to 68k emulator
1038 gbeauche 1.20 static const uint8 jump68k_dat[] = {0x7d, 0x92, 0x43, 0xa6, 0x7d, 0x5a, 0x03, 0xa6, 0x7d, 0x7b, 0x03, 0xa6};
1039     if ((loc = find_rom_data(0x310000, 0x320000, jump68k_dat, sizeof(jump68k_dat))) == 0) return false;
1040     static const uint8 jump68k_caller_dat[] = {0x85, 0x13, 0x00, 0x08, 0x56, 0xbf, 0x50, 0x3e, 0x63, 0xff, 0x0c, 0x00};
1041     if ((base = find_rom_data(0x310000, 0x320000, jump68k_caller_dat, sizeof(jump68k_caller_dat))) == 0) return false;
1042     if ((base = find_rom_powerpc_branch(base + 12, 0x320000, loc)) == 0) return false;
1043     D(bug("jump68k %08lx, called from %08lx\n", loc, base));
1044     lp = (uint32 *)(ROM_BASE + base);
1045 cebix 1.1 *lp++ = htonl(0x80610634); // lwz r3,0x0634(r1) (pointer to Emulator Data)
1046     *lp++ = htonl(0x8081119c); // lwz r4,0x119c(r1) (pointer to opcode table)
1047     *lp++ = htonl(0x80011184); // lwz r0,0x1184(r1) (pointer to emulator init routine)
1048     *lp++ = htonl(0x7c0903a6); // mtctr r0
1049     *lp = htonl(POWERPC_BCTR);
1050     return true;
1051     }
1052    
1053    
1054     /*
1055     * 68k emulator patches
1056     */
1057    
1058     static bool patch_68k_emul(void)
1059     {
1060     uint32 *lp;
1061 gbeauche 1.29 uint32 base, loc;
1062 cebix 1.1
1063     // Overwrite twi instructions
1064 gbeauche 1.20 static const uint8 twi_dat[] = {0x0f, 0xff, 0x00, 0x00, 0x0f, 0xff, 0x00, 0x01, 0x0f, 0xff, 0x00, 0x02};
1065     if ((base = find_rom_data(0x36e600, 0x36ea00, twi_dat, sizeof(twi_dat))) == 0) return false;
1066     D(bug("twi %08lx\n", base));
1067 cebix 1.1 lp = (uint32 *)(ROM_BASE + base);
1068     *lp++ = htonl(0x48000000 + 0x36f900 - base); // b 0x36f900 (Emulator start)
1069     *lp++ = htonl(0x48000000 + 0x36fa00 - base - 4); // b 0x36fa00 (Mixed mode)
1070     *lp++ = htonl(0x48000000 + 0x36fb00 - base - 8); // b 0x36fb00 (Reset/FC1E opcode)
1071     *lp++ = htonl(0x48000000 + 0x36fc00 - base - 12); // FE0A opcode
1072     *lp++ = htonl(POWERPC_ILLEGAL); // Interrupt
1073     *lp++ = htonl(POWERPC_ILLEGAL); // ?
1074     *lp++ = htonl(POWERPC_ILLEGAL);
1075     *lp++ = htonl(POWERPC_ILLEGAL);
1076     *lp++ = htonl(POWERPC_ILLEGAL);
1077     *lp++ = htonl(POWERPC_ILLEGAL);
1078     *lp++ = htonl(POWERPC_ILLEGAL);
1079     *lp++ = htonl(POWERPC_ILLEGAL);
1080     *lp++ = htonl(POWERPC_ILLEGAL);
1081     *lp++ = htonl(POWERPC_ILLEGAL);
1082     *lp++ = htonl(POWERPC_ILLEGAL);
1083     *lp = htonl(POWERPC_ILLEGAL);
1084    
1085     #if EMULATED_PPC
1086 gbeauche 1.7 // Install EMUL_RETURN, EXEC_RETURN, EXEC_NATIVE and EMUL_OP opcodes
1087 cebix 1.1 lp = (uint32 *)(ROM_BASE + 0x380000 + (M68K_EMUL_RETURN << 3));
1088     *lp++ = htonl(POWERPC_EMUL_OP);
1089     *lp++ = htonl(0x4bf66e80); // b 0x366084
1090     *lp++ = htonl(POWERPC_EMUL_OP | 1);
1091     *lp++ = htonl(0x4bf66e78); // b 0x366084
1092 gbeauche 1.7 *lp++ = htonl(POWERPC_EMUL_OP | 2);
1093     *lp++ = htonl(0x4bf66e70); // b 0x366084
1094 cebix 1.1 for (int i=0; i<OP_MAX; i++) {
1095 gbeauche 1.7 *lp++ = htonl(POWERPC_EMUL_OP | (i + 3));
1096     *lp++ = htonl(0x4bf66e68 - i*8); // b 0x366084
1097 cebix 1.1 }
1098     #else
1099     // Install EMUL_RETURN, EXEC_RETURN and EMUL_OP opcodes
1100     lp = (uint32 *)(ROM_BASE + 0x380000 + (M68K_EMUL_RETURN << 3));
1101     *lp++ = htonl(0x80000000 + XLM_EMUL_RETURN_PROC); // lwz r0,XLM_EMUL_RETURN_PROC
1102     *lp++ = htonl(0x4bf705fc); // b 0x36f800
1103     *lp++ = htonl(0x80000000 + XLM_EXEC_RETURN_PROC); // lwz r0,XLM_EXEC_RETURN_PROC
1104     *lp++ = htonl(0x4bf705f4); // b 0x36f800
1105 gbeauche 1.7 *lp++ = htonl(0x00dead00); // Let SheepShaver crash, since
1106     *lp++ = htonl(0x00beef00); // no native opcode is available
1107 cebix 1.1 for (int i=0; i<OP_MAX; i++) {
1108     *lp++ = htonl(0x38a00000 + i); // li r5,OP_*
1109 gbeauche 1.7 *lp++ = htonl(0x4bf705ec - i*8); // b 0x36f808
1110 cebix 1.1 }
1111    
1112     // Extra routines for EMUL_RETURN/EXEC_RETURN/EMUL_OP
1113     lp = (uint32 *)(ROM_BASE + 0x36f800);
1114     *lp++ = htonl(0x7c0803a6); // mtlr r0
1115     *lp++ = htonl(0x4e800020); // blr
1116    
1117     *lp++ = htonl(0x80000000 + XLM_EMUL_OP_PROC); // lwz r0,XLM_EMUL_OP_PROC
1118     *lp++ = htonl(0x7c0803a6); // mtlr r0
1119     *lp = htonl(0x4e800020); // blr
1120     #endif
1121    
1122     // Extra routine for 68k emulator start
1123     lp = (uint32 *)(ROM_BASE + 0x36f900);
1124     *lp++ = htonl(0x7c2903a6); // mtctr r1
1125     *lp++ = htonl(0x80200000 + XLM_IRQ_NEST); // lwz r1,XLM_IRQ_NEST
1126     *lp++ = htonl(0x38210001); // addi r1,r1,1
1127     *lp++ = htonl(0x90200000 + XLM_IRQ_NEST); // stw r1,XLM_IRQ_NEST
1128     *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz r1,XLM_KERNEL_DATA
1129     *lp++ = htonl(0x90c10018); // stw r6,0x18(r1)
1130     *lp++ = htonl(0x7cc902a6); // mfctr r6
1131     *lp++ = htonl(0x90c10004); // stw r6,$0004(r1)
1132     *lp++ = htonl(0x80c1065c); // lwz r6,$065c(r1)
1133     *lp++ = htonl(0x90e6013c); // stw r7,$013c(r6)
1134     *lp++ = htonl(0x91060144); // stw r8,$0144(r6)
1135     *lp++ = htonl(0x9126014c); // stw r9,$014c(r6)
1136     *lp++ = htonl(0x91460154); // stw r10,$0154(r6)
1137     *lp++ = htonl(0x9166015c); // stw r11,$015c(r6)
1138     *lp++ = htonl(0x91860164); // stw r12,$0164(r6)
1139     *lp++ = htonl(0x91a6016c); // stw r13,$016c(r6)
1140     *lp++ = htonl(0x7da00026); // mfcr r13
1141     *lp++ = htonl(0x80e10660); // lwz r7,$0660(r1)
1142     *lp++ = htonl(0x7d8802a6); // mflr r12
1143     *lp++ = htonl(0x50e74001); // rlwimi. r7,r7,8,$80000000
1144     *lp++ = htonl(0x814105f0); // lwz r10,0x05f0(r1)
1145     *lp++ = htonl(0x7d4803a6); // mtlr r10
1146     *lp++ = htonl(0x7d8a6378); // mr r10,r12
1147     *lp++ = htonl(0x3d600002); // lis r11,0x0002
1148     *lp++ = htonl(0x616bf072); // ori r11,r11,0xf072 (MSR)
1149     *lp++ = htonl(0x50e7deb4); // rlwimi r7,r7,27,$00000020
1150     *lp = htonl(0x4e800020); // blr
1151    
1152     // Extra routine for Mixed Mode
1153     lp = (uint32 *)(ROM_BASE + 0x36fa00);
1154     *lp++ = htonl(0x7c2903a6); // mtctr r1
1155     *lp++ = htonl(0x80200000 + XLM_IRQ_NEST); // lwz r1,XLM_IRQ_NEST
1156     *lp++ = htonl(0x38210001); // addi r1,r1,1
1157     *lp++ = htonl(0x90200000 + XLM_IRQ_NEST); // stw r1,XLM_IRQ_NEST
1158     *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz r1,XLM_KERNEL_DATA
1159     *lp++ = htonl(0x90c10018); // stw r6,0x18(r1)
1160     *lp++ = htonl(0x7cc902a6); // mfctr r6
1161     *lp++ = htonl(0x90c10004); // stw r6,$0004(r1)
1162     *lp++ = htonl(0x80c1065c); // lwz r6,$065c(r1)
1163     *lp++ = htonl(0x90e6013c); // stw r7,$013c(r6)
1164     *lp++ = htonl(0x91060144); // stw r8,$0144(r6)
1165     *lp++ = htonl(0x9126014c); // stw r9,$014c(r6)
1166     *lp++ = htonl(0x91460154); // stw r10,$0154(r6)
1167     *lp++ = htonl(0x9166015c); // stw r11,$015c(r6)
1168     *lp++ = htonl(0x91860164); // stw r12,$0164(r6)
1169     *lp++ = htonl(0x91a6016c); // stw r13,$016c(r6)
1170     *lp++ = htonl(0x7da00026); // mfcr r13
1171     *lp++ = htonl(0x80e10660); // lwz r7,$0660(r1)
1172     *lp++ = htonl(0x7d8802a6); // mflr r12
1173     *lp++ = htonl(0x50e74001); // rlwimi. r7,r7,8,$80000000
1174     *lp++ = htonl(0x814105f4); // lwz r10,0x05f4(r1)
1175     *lp++ = htonl(0x7d4803a6); // mtlr r10
1176     *lp++ = htonl(0x7d8a6378); // mr r10,r12
1177     *lp++ = htonl(0x3d600002); // lis r11,0x0002
1178     *lp++ = htonl(0x616bf072); // ori r11,r11,0xf072 (MSR)
1179     *lp++ = htonl(0x50e7deb4); // rlwimi r7,r7,27,$00000020
1180     *lp = htonl(0x4e800020); // blr
1181    
1182     // Extra routine for Reset/FC1E opcode
1183 gbeauche 1.4 lp = (uint32 *)(ROM_BASE + 0x36fb00);
1184 cebix 1.1 *lp++ = htonl(0x7c2903a6); // mtctr r1
1185     *lp++ = htonl(0x80200000 + XLM_IRQ_NEST); // lwz r1,XLM_IRQ_NEST
1186     *lp++ = htonl(0x38210001); // addi r1,r1,1
1187     *lp++ = htonl(0x90200000 + XLM_IRQ_NEST); // stw r1,XLM_IRQ_NEST
1188     *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz r1,XLM_KERNEL_DATA
1189     *lp++ = htonl(0x90c10018); // stw r6,0x18(r1)
1190     *lp++ = htonl(0x7cc902a6); // mfctr r6
1191     *lp++ = htonl(0x90c10004); // stw r6,$0004(r1)
1192     *lp++ = htonl(0x80c1065c); // lwz r6,$065c(r1)
1193     *lp++ = htonl(0x90e6013c); // stw r7,$013c(r6)
1194     *lp++ = htonl(0x91060144); // stw r8,$0144(r6)
1195     *lp++ = htonl(0x9126014c); // stw r9,$014c(r6)
1196     *lp++ = htonl(0x91460154); // stw r10,$0154(r6)
1197     *lp++ = htonl(0x9166015c); // stw r11,$015c(r6)
1198     *lp++ = htonl(0x91860164); // stw r12,$0164(r6)
1199     *lp++ = htonl(0x91a6016c); // stw r13,$016c(r6)
1200     *lp++ = htonl(0x7da00026); // mfcr r13
1201     *lp++ = htonl(0x80e10660); // lwz r7,$0660(r1)
1202     *lp++ = htonl(0x7d8802a6); // mflr r12
1203     *lp++ = htonl(0x50e74001); // rlwimi. r7,r7,8,$80000000
1204 gbeauche 1.4 *lp++ = htonl(0x814105f8); // lwz r10,0x05f8(r1)
1205 cebix 1.1 *lp++ = htonl(0x7d4803a6); // mtlr r10
1206     *lp++ = htonl(0x7d8a6378); // mr r10,r12
1207     *lp++ = htonl(0x3d600002); // lis r11,0x0002
1208     *lp++ = htonl(0x616bf072); // ori r11,r11,0xf072 (MSR)
1209     *lp++ = htonl(0x50e7deb4); // rlwimi r7,r7,27,$00000020
1210     *lp = htonl(0x4e800020); // blr
1211    
1212     // Extra routine for FE0A opcode (QuickDraw 3D needs this)
1213     lp = (uint32 *)(ROM_BASE + 0x36fc00);
1214     *lp++ = htonl(0x7c2903a6); // mtctr r1
1215     *lp++ = htonl(0x80200000 + XLM_IRQ_NEST); // lwz r1,XLM_IRQ_NEST
1216     *lp++ = htonl(0x38210001); // addi r1,r1,1
1217     *lp++ = htonl(0x90200000 + XLM_IRQ_NEST); // stw r1,XLM_IRQ_NEST
1218     *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz r1,XLM_KERNEL_DATA
1219     *lp++ = htonl(0x90c10018); // stw r6,0x18(r1)
1220     *lp++ = htonl(0x7cc902a6); // mfctr r6
1221     *lp++ = htonl(0x90c10004); // stw r6,$0004(r1)
1222     *lp++ = htonl(0x80c1065c); // lwz r6,$065c(r1)
1223     *lp++ = htonl(0x90e6013c); // stw r7,$013c(r6)
1224     *lp++ = htonl(0x91060144); // stw r8,$0144(r6)
1225     *lp++ = htonl(0x9126014c); // stw r9,$014c(r6)
1226     *lp++ = htonl(0x91460154); // stw r10,$0154(r6)
1227     *lp++ = htonl(0x9166015c); // stw r11,$015c(r6)
1228     *lp++ = htonl(0x91860164); // stw r12,$0164(r6)
1229     *lp++ = htonl(0x91a6016c); // stw r13,$016c(r6)
1230     *lp++ = htonl(0x7da00026); // mfcr r13
1231     *lp++ = htonl(0x80e10660); // lwz r7,$0660(r1)
1232     *lp++ = htonl(0x7d8802a6); // mflr r12
1233     *lp++ = htonl(0x50e74001); // rlwimi. r7,r7,8,$80000000
1234 gbeauche 1.4 *lp++ = htonl(0x814105fc); // lwz r10,0x05fc(r1)
1235 cebix 1.1 *lp++ = htonl(0x7d4803a6); // mtlr r10
1236     *lp++ = htonl(0x7d8a6378); // mr r10,r12
1237     *lp++ = htonl(0x3d600002); // lis r11,0x0002
1238     *lp++ = htonl(0x616bf072); // ori r11,r11,0xf072 (MSR)
1239     *lp++ = htonl(0x50e7deb4); // rlwimi r7,r7,27,$00000020
1240     *lp = htonl(0x4e800020); // blr
1241    
1242     // Patch DR emulator to jump to right address when an interrupt occurs
1243     lp = (uint32 *)(ROM_BASE + 0x370000);
1244     while (lp < (uint32 *)(ROM_BASE + 0x380000)) {
1245     if (ntohl(*lp) == 0x4ca80020) // bclr 5,8
1246     goto dr_found;
1247     lp++;
1248     }
1249     D(bug("DR emulator patch location not found\n"));
1250     return false;
1251     dr_found:
1252     lp++;
1253 gbeauche 1.29 loc = (uint32)lp - ROM_BASE;
1254     if ((base = powerpc_branch_target(ROM_BASE + loc)) == 0) base = ROM_BASE + loc;
1255     static const uint8 dr_ret_dat[] = {0x80, 0xbf, 0x08, 0x14, 0x53, 0x19, 0x4d, 0xac, 0x7c, 0xa8, 0x03, 0xa6};
1256     if ((base = find_rom_data(base - ROM_BASE, 0x380000, dr_ret_dat, sizeof(dr_ret_dat))) == 0) return false;
1257     D(bug("dr_ret %08lx\n", base));
1258     if (base != loc) {
1259     // OldWorld ROMs contain an absolute branch
1260     D(bug(" patching absolute branch at %08x\n", (uint32)lp - ROM_BASE));
1261     *lp = htonl(0x48000000 + 0xf000 - (((uint32)lp - ROM_BASE) & 0xffff)); // b DR_CACHE_BASE+0x1f000
1262     lp = (uint32 *)(ROM_BASE + 0x37f000);
1263     *lp++ = htonl(0x3c000000 + ((ROM_BASE + base) >> 16)); // lis r0,xxx
1264     *lp++ = htonl(0x60000000 + ((ROM_BASE + base) & 0xffff)); // ori r0,r0,xxx
1265     *lp++ = htonl(0x7c0803a6); // mtlr r0
1266     *lp = htonl(POWERPC_BLR); // blr
1267     }
1268 cebix 1.1 return true;
1269     }
1270    
1271    
1272     /*
1273     * Nanokernel patches
1274     */
1275    
1276     static bool patch_nanokernel(void)
1277     {
1278     uint32 *lp;
1279 gbeauche 1.20 uint32 base, loc;
1280 cebix 1.1
1281     // Patch Mixed Mode trap
1282 gbeauche 1.20 static const uint8 virt2phys_dat[] = {0x7d, 0x1b, 0x43, 0x78, 0x3b, 0xa1, 0x03, 0x20};
1283     if ((base = find_rom_data(0x313000, 0x314000, virt2phys_dat, sizeof(virt2phys_dat))) == 0) return false;
1284     D(bug("virt2phys %08lx\n", base + 8));
1285     lp = (uint32 *)(ROM_BASE + base + 8); // Don't translate virtual->physical
1286     lp[0] = htonl(0x7f7fdb78); // mr r31,r27
1287     lp[2] = htonl(POWERPC_NOP);
1288    
1289     static const uint8 ppc_excp_tbl_dat[] = {0x39, 0x01, 0x04, 0x20, 0x7d, 0x13, 0x43, 0xa6};
1290     if ((base = find_rom_data(0x313000, 0x314000, ppc_excp_tbl_dat, sizeof(ppc_excp_tbl_dat))) == 0) return false;
1291     D(bug("ppc_excp_tbl %08lx\n", base));
1292     lp = (uint32 *)(ROM_BASE + base); // Don't activate PPC exception table
1293 cebix 1.1 *lp++ = htonl(0x39000000 + MODE_NATIVE); // li r8,MODE_NATIVE
1294 gbeauche 1.20 *lp = htonl(0x91000000 + XLM_RUN_MODE); // stw r8,XLM_RUN_MODE
1295 cebix 1.1
1296 gbeauche 1.20 static const uint8 save_fpu_dat[] = {0x7d, 0x00, 0x00, 0xa6, 0x61, 0x08, 0x20, 0x00, 0x7d, 0x00, 0x01, 0x24};
1297     if ((base = find_rom_data(0x310000, 0x314000, save_fpu_dat, sizeof(save_fpu_dat))) == 0) return false;
1298     D(bug("save_fpu %08lx\n", base));
1299     lp = (uint32 *)(ROM_BASE + base); // Don't modify MSR to turn on FPU
1300     if (ntohl(lp[4]) != 0x556b04e2) return false;
1301     loc = ROM_BASE + base;
1302     #if 1
1303     // FIXME: is that really intended?
1304 cebix 1.1 *lp++ = htonl(POWERPC_NOP);
1305     lp++;
1306     *lp++ = htonl(POWERPC_NOP);
1307     lp++;
1308     *lp = htonl(POWERPC_NOP);
1309 gbeauche 1.20 #else
1310     lp[0] = htonl(POWERPC_NOP);
1311     lp[1] = htonl(POWERPC_NOP);
1312     lp[2] = htonl(POWERPC_NOP);
1313     lp[3] = htonl(POWERPC_NOP);
1314     #endif
1315 cebix 1.1
1316 gbeauche 1.20 static const uint8 save_fpu_caller_dat[] = {0x93, 0xa6, 0x01, 0xec, 0x93, 0xc6, 0x01, 0xf4, 0x93, 0xe6, 0x01, 0xfc, 0x40};
1317     if ((base = find_rom_data(0x310000, 0x314000, save_fpu_caller_dat, sizeof(save_fpu_caller_dat))) == 0) return false;
1318     D(bug("save_fpu_caller %08lx\n", base + 12));
1319     if (powerpc_branch_target(ROM_BASE + base + 12) != loc) return false;
1320     lp = (uint32 *)(ROM_BASE + base + 12); // Always save FPU state
1321 cebix 1.1 *lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff)); // bl 0x00312e88
1322    
1323 gbeauche 1.20 static const uint8 mdec_dat[] = {0x7f, 0xf6, 0x02, 0xa6, 0x2c, 0x08, 0x00, 0x00, 0x93, 0xe1, 0x06, 0x68, 0x7d, 0x16, 0x03, 0xa6};
1324     if ((base = find_rom_data(0x310000, 0x314000, mdec_dat, sizeof(mdec_dat))) == 0) return false;
1325     D(bug("mdec %08lx\n", base));
1326     lp = (uint32 *)(ROM_BASE + base); // Don't modify DEC
1327     lp[0] = htonl(0x3be00000); // li r31,0
1328 cebix 1.1 #if 1
1329 gbeauche 1.20 lp[3] = htonl(POWERPC_NOP);
1330     lp[4] = htonl(POWERPC_NOP);
1331 cebix 1.1 #else
1332 gbeauche 1.20 lp[3] = htonl(0x39000040); // li r8,0x40
1333     lp[4] = htonl(0x990600e4); // stb r8,0xe4(r6)
1334 cebix 1.1 #endif
1335    
1336 gbeauche 1.20 static const uint8 restore_fpu_caller_dat[] = {0x81, 0x06, 0x00, 0xf4, 0x81, 0x46, 0x00, 0xfc, 0x7d, 0x09, 0x03, 0xa6, 0x40};
1337     if ((base = find_rom_data(0x310000, 0x314000, restore_fpu_caller_dat, sizeof(restore_fpu_caller_dat))) == 0) return false;
1338     D(bug("restore_fpu_caller %08lx\n", base + 12));
1339     lp = (uint32 *)(ROM_BASE + base + 12); // Always restore FPU state
1340 cebix 1.1 *lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff)); // bl 0x00312ddc
1341    
1342 gbeauche 1.20 static const uint8 m68k_excp_tbl_dat[] = {0x81, 0x21, 0x06, 0x58, 0x39, 0x01, 0x03, 0x60, 0x7d, 0x13, 0x43, 0xa6};
1343     if ((base = find_rom_data(0x310000, 0x314000, m68k_excp_tbl_dat, sizeof(m68k_excp_tbl_dat))) == 0) return false;
1344     D(bug("m68k_excp %08lx\n", base + 4));
1345     lp = (uint32 *)(ROM_BASE + base + 4); // Don't activate 68k exception table
1346 cebix 1.1 *lp++ = htonl(0x39000000 + MODE_68K); // li r8,MODE_68K
1347     *lp = htonl(0x91000000 + XLM_RUN_MODE); // stw r8,XLM_RUN_MODE
1348    
1349     // Patch 68k emulator trap routine
1350 gbeauche 1.20 static const uint8 restore_fpu_caller2_dat[] = {0x81, 0x86, 0x00, 0x8c, 0x80, 0x66, 0x00, 0x94, 0x80, 0x86, 0x00, 0x9c, 0x40};
1351     if ((base = find_rom_data(0x310000, 0x314000, restore_fpu_caller2_dat, sizeof(restore_fpu_caller2_dat))) == 0) return false;
1352     D(bug("restore_fpu_caller2 %08lx\n", base + 12));
1353     loc = powerpc_branch_target(ROM_BASE + base + 12) - ROM_BASE;
1354     lp = (uint32 *)(ROM_BASE + base + 12); // Always restore FPU state
1355 cebix 1.1 *lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff)); // bl 0x00312dd4
1356    
1357 gbeauche 1.20 static const uint8 restore_fpu_dat[] = {0x55, 0x68, 0x04, 0xa5, 0x4c, 0x82, 0x00, 0x20, 0x81, 0x06, 0x00, 0xe4};
1358     if ((base = find_rom_data(0x310000, 0x314000, restore_fpu_dat, sizeof(restore_fpu_dat))) == 0) return false;
1359     D(bug("restore_fpu %08lx\n", base));
1360     if (base != loc) return false;
1361     lp = (uint32 *)(ROM_BASE + base + 4); // Don't modify MSR to turn on FPU
1362 cebix 1.1 *lp++ = htonl(POWERPC_NOP);
1363     lp += 2;
1364     *lp++ = htonl(POWERPC_NOP);
1365     lp++;
1366     *lp++ = htonl(POWERPC_NOP);
1367     *lp++ = htonl(POWERPC_NOP);
1368     *lp = htonl(POWERPC_NOP);
1369    
1370     // Patch trap return routine
1371 gbeauche 1.20 static const uint8 trap_return_dat[] = {0x80, 0xc1, 0x00, 0x18, 0x80, 0x21, 0x00, 0x04, 0x4c, 0x00, 0x00, 0x64};
1372     if ((base = find_rom_data(0x312000, 0x320000, trap_return_dat, sizeof(trap_return_dat))) == 0) return false;
1373     D(bug("trap_return %08lx\n", base + 8));
1374     lp = (uint32 *)(ROM_BASE + base + 8); // Replace rfi
1375     *lp = htonl(POWERPC_BCTR);
1376    
1377     while (ntohl(*lp) != 0x7d5a03a6) lp--;
1378 cebix 1.1 *lp++ = htonl(0x7d4903a6); // mtctr r10
1379     *lp++ = htonl(0x7daff120); // mtcr r13
1380 gbeauche 1.20 *lp = htonl(0x48000000 + ((0x318000 - ((uint32)lp - ROM_BASE)) & 0x03fffffc)); // b ROM_BASE+0x318000
1381     uint32 npc = (uint32)(lp + 1) - ROM_BASE;
1382 cebix 1.1
1383     lp = (uint32 *)(ROM_BASE + 0x318000);
1384     *lp++ = htonl(0x81400000 + XLM_IRQ_NEST); // lwz r10,XLM_IRQ_NEST
1385     *lp++ = htonl(0x394affff); // subi r10,r10,1
1386     *lp++ = htonl(0x91400000 + XLM_IRQ_NEST); // stw r10,XLM_IRQ_NEST
1387 gbeauche 1.20 *lp = htonl(0x48000000 + ((npc - 0x31800c) & 0x03fffffc)); // b ROM_BASE+0x312c2c
1388 gbeauche 1.8
1389 cebix 1.1 /*
1390     // Disable FE0A/FE06 opcodes
1391     lp = (uint32 *)(ROM_BASE + 0x3144ac);
1392     *lp++ = htonl(POWERPC_NOP);
1393     *lp += 8;
1394     */
1395     return true;
1396     }
1397    
1398    
1399     /*
1400     * 68k boot routine patches
1401     */
1402    
1403     static bool patch_68k(void)
1404     {
1405     uint32 *lp;
1406     uint16 *wp;
1407     uint8 *bp;
1408 gbeauche 1.20 uint32 base, loc;
1409 cebix 1.1
1410     // Remove 68k RESET instruction
1411     static const uint8 reset_dat[] = {0x4e, 0x70};
1412     if ((base = find_rom_data(0xc8, 0x120, reset_dat, sizeof(reset_dat))) == 0) return false;
1413     D(bug("reset %08lx\n", base));
1414     wp = (uint16 *)(ROM_BASE + base);
1415     *wp = htons(M68K_NOP);
1416    
1417     // Fake reading PowerMac ID (via Universal)
1418     static const uint8 powermac_id_dat[] = {0x45, 0xf9, 0x5f, 0xff, 0xff, 0xfc, 0x20, 0x12, 0x72, 0x00};
1419     if ((base = find_rom_data(0xe000, 0x15000, powermac_id_dat, sizeof(powermac_id_dat))) == 0) return false;
1420     D(bug("powermac_id %08lx\n", base));
1421     wp = (uint16 *)(ROM_BASE + base);
1422     *wp++ = htons(0x203c); // move.l #id,d0
1423     *wp++ = htons(0);
1424     // if (ROMType == ROMTYPE_NEWWORLD)
1425     // *wp++ = htons(0x3035); // (PowerMac 9500 ID)
1426     // else
1427     *wp++ = htons(0x3020); // (PowerMac 9500 ID)
1428     *wp++ = htons(0xb040); // cmp.w d0,d0
1429     *wp = htons(0x4ed6); // jmp (a6)
1430    
1431     // Patch UniversalInfo
1432     if (ROMType == ROMTYPE_NEWWORLD) {
1433     static const uint8 univ_info_dat[] = {0x3f, 0xff, 0x04, 0x00};
1434 gbeauche 1.4 if ((base = find_rom_data(0x14000, 0x18000, univ_info_dat, sizeof(univ_info_dat))) == 0) return false;
1435 cebix 1.1 D(bug("universal_info %08lx\n", base));
1436     lp = (uint32 *)(ROM_BASE + base - 0x14);
1437     lp[0x00 >> 2] = htonl(ADDR_MAP_PATCH_SPACE - (base - 0x14));
1438     lp[0x10 >> 2] = htonl(0xcc003d11); // Make it like the PowerMac 9500 UniversalInfo
1439     lp[0x14 >> 2] = htonl(0x3fff0401);
1440     lp[0x18 >> 2] = htonl(0x0300001c);
1441     lp[0x1c >> 2] = htonl(0x000108c4);
1442     lp[0x24 >> 2] = htonl(0xc301bf26);
1443     lp[0x28 >> 2] = htonl(0x00000861);
1444     lp[0x58 >> 2] = htonl(0x30200000);
1445     lp[0x60 >> 2] = htonl(0x0000003d);
1446     } else if (ROMType == ROMTYPE_ZANZIBAR) {
1447     base = 0x12b70;
1448     lp = (uint32 *)(ROM_BASE + base - 0x14);
1449     lp[0x00 >> 2] = htonl(ADDR_MAP_PATCH_SPACE - (base - 0x14));
1450     lp[0x10 >> 2] = htonl(0xcc003d11); // Make it like the PowerMac 9500 UniversalInfo
1451     lp[0x14 >> 2] = htonl(0x3fff0401);
1452     lp[0x18 >> 2] = htonl(0x0300001c);
1453     lp[0x1c >> 2] = htonl(0x000108c4);
1454     lp[0x24 >> 2] = htonl(0xc301bf26);
1455     lp[0x28 >> 2] = htonl(0x00000861);
1456     lp[0x58 >> 2] = htonl(0x30200000);
1457     lp[0x60 >> 2] = htonl(0x0000003d);
1458 gbeauche 1.11 } else if (ROMType == ROMTYPE_GOSSAMER) {
1459     base = 0x12d20;
1460     lp = (uint32 *)(ROM_BASE + base - 0x14);
1461     lp[0x00 >> 2] = htonl(ADDR_MAP_PATCH_SPACE - (base - 0x14));
1462     lp[0x10 >> 2] = htonl(0xcc003d11); // Make it like the PowerMac 9500 UniversalInfo
1463     lp[0x14 >> 2] = htonl(0x3fff0401);
1464     lp[0x18 >> 2] = htonl(0x0300001c);
1465     lp[0x1c >> 2] = htonl(0x000108c4);
1466     lp[0x24 >> 2] = htonl(0xc301bf26);
1467     lp[0x28 >> 2] = htonl(0x00000861);
1468     lp[0x58 >> 2] = htonl(0x30410000);
1469     lp[0x60 >> 2] = htonl(0x0000003d);
1470 cebix 1.1 }
1471    
1472     // Construct AddrMap for NewWorld ROM
1473 gbeauche 1.11 if (ROMType == ROMTYPE_NEWWORLD || ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_GOSSAMER) {
1474 cebix 1.1 lp = (uint32 *)(ROM_BASE + ADDR_MAP_PATCH_SPACE);
1475     memset(lp - 10, 0, 0x128);
1476     lp[-10] = htonl(0x0300001c);
1477     lp[-9] = htonl(0x000108c4);
1478     lp[-4] = htonl(0x00300000);
1479     lp[-2] = htonl(0x11010000);
1480     lp[-1] = htonl(0xf8000000);
1481     lp[0] = htonl(0xffc00000);
1482     lp[2] = htonl(0xf3016000);
1483     lp[3] = htonl(0xf3012000);
1484     lp[4] = htonl(0xf3012000);
1485     lp[24] = htonl(0xf3018000);
1486     lp[25] = htonl(0xf3010000);
1487     lp[34] = htonl(0xf3011000);
1488     lp[38] = htonl(0xf3015000);
1489     lp[39] = htonl(0xf3014000);
1490     lp[43] = htonl(0xf3000000);
1491     lp[48] = htonl(0xf8000000);
1492     }
1493    
1494     // Don't initialize VIA (via Universal)
1495     static const uint8 via_init_dat[] = {0x08, 0x00, 0x00, 0x02, 0x67, 0x00, 0x00, 0x2c, 0x24, 0x68, 0x00, 0x08};
1496     if ((base = find_rom_data(0xe000, 0x15000, via_init_dat, sizeof(via_init_dat))) == 0) return false;
1497     D(bug("via_init %08lx\n", base));
1498     wp = (uint16 *)(ROM_BASE + base + 4);
1499     *wp = htons(0x6000); // bra
1500    
1501     static const uint8 via_init2_dat[] = {0x24, 0x68, 0x00, 0x08, 0x00, 0x12, 0x00, 0x30, 0x4e, 0x71};
1502     if ((base = find_rom_data(0xa000, 0x10000, via_init2_dat, sizeof(via_init2_dat))) == 0) return false;
1503     D(bug("via_init2 %08lx\n", base));
1504     wp = (uint16 *)(ROM_BASE + base);
1505     *wp = htons(0x4ed6); // jmp (a6)
1506    
1507     static const uint8 via_init3_dat[] = {0x22, 0x68, 0x00, 0x08, 0x28, 0x3c, 0x20, 0x00, 0x01, 0x00};
1508     if ((base = find_rom_data(0xa000, 0x10000, via_init3_dat, sizeof(via_init3_dat))) == 0) return false;
1509     D(bug("via_init3 %08lx\n", base));
1510     wp = (uint16 *)(ROM_BASE + base);
1511     *wp = htons(0x4ed6); // jmp (a6)
1512    
1513     // Don't RunDiags, get BootGlobs pointer directly
1514     if (ROMType == ROMTYPE_NEWWORLD) {
1515     static const uint8 run_diags_dat[] = {0x60, 0xff, 0x00, 0x0c};
1516     if ((base = find_rom_data(0x110, 0x128, run_diags_dat, sizeof(run_diags_dat))) == 0) return false;
1517     D(bug("run_diags %08lx\n", base));
1518     wp = (uint16 *)(ROM_BASE + base);
1519     *wp++ = htons(0x4df9); // lea xxx,a6
1520     *wp++ = htons((RAMBase + RAMSize - 0x1c) >> 16);
1521     *wp = htons((RAMBase + RAMSize - 0x1c) & 0xffff);
1522     } else {
1523     static const uint8 run_diags_dat[] = {0x74, 0x00, 0x2f, 0x0e};
1524     if ((base = find_rom_data(0xd0, 0xf0, run_diags_dat, sizeof(run_diags_dat))) == 0) return false;
1525     D(bug("run_diags %08lx\n", base));
1526     wp = (uint16 *)(ROM_BASE + base - 6);
1527     *wp++ = htons(0x4df9); // lea xxx,a6
1528     *wp++ = htons((RAMBase + RAMSize - 0x1c) >> 16);
1529     *wp = htons((RAMBase + RAMSize - 0x1c) & 0xffff);
1530     }
1531    
1532     // Replace NVRAM routines
1533     static const uint8 nvram1_dat[] = {0x48, 0xe7, 0x01, 0x0e, 0x24, 0x68, 0x00, 0x08, 0x08, 0x83, 0x00, 0x1f};
1534     if ((base = find_rom_data(0x7000, 0xc000, nvram1_dat, sizeof(nvram1_dat))) == 0) return false;
1535     D(bug("nvram1 %08lx\n", base));
1536     wp = (uint16 *)(ROM_BASE + base);
1537     *wp++ = htons(M68K_EMUL_OP_XPRAM1);
1538     *wp = htons(M68K_RTS);
1539    
1540     if (ROMType == ROMTYPE_NEWWORLD) {
1541     static const uint8 nvram2_dat[] = {0x48, 0xe7, 0x1c, 0xe0, 0x4f, 0xef, 0xff, 0xb4};
1542     if ((base = find_rom_data(0xa000, 0xd000, nvram2_dat, sizeof(nvram2_dat))) == 0) return false;
1543     D(bug("nvram2 %08lx\n", base));
1544     wp = (uint16 *)(ROM_BASE + base);
1545     *wp++ = htons(M68K_EMUL_OP_XPRAM2);
1546     *wp = htons(0x4ed3); // jmp (a3)
1547    
1548     static const uint8 nvram3_dat[] = {0x48, 0xe7, 0xdc, 0xe0, 0x4f, 0xef, 0xff, 0xb4};
1549     if ((base = find_rom_data(0xa000, 0xd000, nvram3_dat, sizeof(nvram3_dat))) == 0) return false;
1550     D(bug("nvram3 %08lx\n", base));
1551     wp = (uint16 *)(ROM_BASE + base);
1552     *wp++ = htons(M68K_EMUL_OP_XPRAM3);
1553     *wp = htons(0x4ed3); // jmp (a3)
1554    
1555     static const uint8 nvram4_dat[] = {0x4e, 0x56, 0xff, 0xa8, 0x48, 0xe7, 0x1f, 0x38, 0x16, 0x2e, 0x00, 0x13};
1556     if ((base = find_rom_data(0xa000, 0xd000, nvram4_dat, sizeof(nvram4_dat))) == 0) return false;
1557     D(bug("nvram4 %08lx\n", base));
1558     wp = (uint16 *)(ROM_BASE + base + 16);
1559     *wp++ = htons(0x1a2e); // move.b ($000f,a6),d5
1560     *wp++ = htons(0x000f);
1561     *wp++ = htons(M68K_EMUL_OP_NVRAM3);
1562     *wp++ = htons(0x4cee); // movem.l ($ff88,a6),d3-d7/a2-a4
1563     *wp++ = htons(0x1cf8);
1564     *wp++ = htons(0xff88);
1565     *wp++ = htons(0x4e5e); // unlk a6
1566     *wp = htons(M68K_RTS);
1567    
1568     static const uint8 nvram5_dat[] = {0x0c, 0x80, 0x03, 0x00, 0x00, 0x00, 0x66, 0x0a, 0x70, 0x00, 0x21, 0xf8, 0x02, 0x0c, 0x01, 0xe4};
1569     if ((base = find_rom_data(0xa000, 0xd000, nvram5_dat, sizeof(nvram5_dat))) == 0) return false;
1570     D(bug("nvram5 %08lx\n", base));
1571     wp = (uint16 *)(ROM_BASE + base + 6);
1572     *wp = htons(M68K_NOP);
1573    
1574     static const uint8 nvram6_dat[] = {0x2f, 0x0a, 0x24, 0x48, 0x4f, 0xef, 0xff, 0xa0, 0x20, 0x0f};
1575     if ((base = find_rom_data(0x9000, 0xb000, nvram6_dat, sizeof(nvram6_dat))) == 0) return false;
1576     D(bug("nvram6 %08lx\n", base));
1577     wp = (uint16 *)(ROM_BASE + base);
1578     *wp++ = htons(0x7000); // moveq #0,d0
1579     *wp++ = htons(0x2080); // move.l d0,(a0)
1580     *wp++ = htons(0x4228); // clr.b 4(a0)
1581     *wp++ = htons(0x0004);
1582     *wp = htons(M68K_RTS);
1583    
1584     static const uint8 nvram7_dat[] = {0x42, 0x2a, 0x00, 0x04, 0x4f, 0xef, 0x00, 0x60, 0x24, 0x5f, 0x4e, 0x75, 0x4f, 0xef, 0xff, 0xa0, 0x20, 0x0f};
1585     base = find_rom_data(0x9000, 0xb000, nvram7_dat, sizeof(nvram7_dat));
1586     if (base) {
1587     D(bug("nvram7 %08lx\n", base));
1588     wp = (uint16 *)(ROM_BASE + base + 12);
1589     *wp = htons(M68K_RTS);
1590     }
1591     } else {
1592     static const uint8 nvram2_dat[] = {0x4e, 0xd6, 0x06, 0x41, 0x13, 0x00};
1593     if ((base = find_rom_data(0x7000, 0xb000, nvram2_dat, sizeof(nvram2_dat))) == 0) return false;
1594     D(bug("nvram2 %08lx\n", base));
1595     wp = (uint16 *)(ROM_BASE + base + 2);
1596     *wp++ = htons(M68K_EMUL_OP_XPRAM2);
1597     *wp = htons(0x4ed3); // jmp (a3)
1598    
1599 gbeauche 1.11 static const uint8 nvram3_dat[] = {0x4e, 0xd3, 0x06, 0x41, 0x13, 0x00};
1600     if ((base = find_rom_data(0x7000, 0xb000, nvram3_dat, sizeof(nvram3_dat))) == 0) return false;
1601     D(bug("nvram3 %08lx\n", base));
1602     wp = (uint16 *)(ROM_BASE + base + 2);
1603     *wp++ = htons(M68K_EMUL_OP_XPRAM3);
1604     *wp = htons(0x4ed3); // jmp (a3)
1605    
1606     static const uint32 nvram4_loc[] = {0x582f0, 0xa0a0, 0x7e50, 0xa1d0, 0x538d0, 0};
1607     wp = (uint16 *)(ROM_BASE + nvram4_loc[ROMType]);
1608 cebix 1.1 *wp++ = htons(0x202f); // move.l 4(sp),d0
1609     *wp++ = htons(0x0004);
1610     *wp++ = htons(M68K_EMUL_OP_NVRAM1);
1611     if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_GAZELLE)
1612     *wp = htons(M68K_RTS);
1613     else {
1614     *wp++ = htons(0x1f40); // move.b d0,8(sp)
1615     *wp++ = htons(0x0008);
1616     *wp++ = htons(0x4e74); // rtd #4
1617     *wp = htons(0x0004);
1618     }
1619    
1620 gbeauche 1.11 static const uint32 nvram5_loc[] = {0x58460, 0xa0f0, 0x7f40, 0xa220, 0x53a20, 0};
1621     wp = (uint16 *)(ROM_BASE + nvram5_loc[ROMType]);
1622 cebix 1.1 if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_GAZELLE) {
1623     *wp++ = htons(0x202f); // move.l 4(sp),d0
1624     *wp++ = htons(0x0004);
1625     *wp++ = htons(0x122f); // move.b 11(sp),d1
1626     *wp++ = htons(0x000b);
1627     *wp++ = htons(M68K_EMUL_OP_NVRAM2);
1628     *wp = htons(M68K_RTS);
1629     } else {
1630     *wp++ = htons(0x202f); // move.l 6(sp),d0
1631     *wp++ = htons(0x0006);
1632     *wp++ = htons(0x122f); // move.b 4(sp),d1
1633     *wp++ = htons(0x0004);
1634     *wp++ = htons(M68K_EMUL_OP_NVRAM2);
1635     *wp++ = htons(0x4e74); // rtd #6
1636     *wp = htons(0x0006);
1637     }
1638     }
1639    
1640     // Fix MemTop/BootGlobs during system startup
1641     static const uint8 mem_top_dat[] = {0x2c, 0x6c, 0xff, 0xec, 0x2a, 0x4c, 0xdb, 0xec, 0xff, 0xf4};
1642     if ((base = find_rom_data(0x120, 0x180, mem_top_dat, sizeof(mem_top_dat))) == 0) return false;
1643     D(bug("mem_top %08lx\n", base));
1644     wp = (uint16 *)(ROM_BASE + base);
1645     *wp++ = htons(M68K_EMUL_OP_FIX_MEMTOP);
1646     *wp = htons(M68K_NOP);
1647    
1648     // Don't initialize SCC (via 0x1ac)
1649 gbeauche 1.20 static const uint8 scc_init_caller_dat[] = {0x21, 0xce, 0x01, 0x08, 0x22, 0x78, 0x0d, 0xd8};
1650     if ((base = find_rom_data(0x180, 0x1f0, scc_init_caller_dat, sizeof(scc_init_caller_dat))) == 0) return false;
1651     D(bug("scc_init_caller %08lx\n", base + 12));
1652     wp = (uint16 *)(ROM_BASE + base + 12);
1653     loc = ntohs(wp[1]) + ((uintptr)wp - ROM_BASE) + 2;
1654 gbeauche 1.21 static const uint8 scc_init_dat[] = {0x20, 0x78, 0x01, 0xdc, 0x22, 0x78, 0x01, 0xd8};
1655 gbeauche 1.22 if ((base = find_rom_data(loc, loc + 0x80, scc_init_dat, sizeof(scc_init_dat))) == 0) return false;
1656 cebix 1.1 D(bug("scc_init %08lx\n", base));
1657 gbeauche 1.20 wp = (uint16 *)(ROM_BASE + base);
1658 cebix 1.1 *wp++ = htons(M68K_EMUL_OP_RESET);
1659     *wp = htons(M68K_RTS);
1660    
1661     // Don't EnableExtCache (via 0x1f6) and don't DisableIntSources(via 0x1fc)
1662     static const uint8 ext_cache_dat[] = {0x4e, 0x7b, 0x00, 0x02};
1663     if ((base = find_rom_data(0x1d0, 0x230, ext_cache_dat, sizeof(ext_cache_dat))) == 0) return false;
1664     D(bug("ext_cache %08lx\n", base));
1665     lp = (uint32 *)(ROM_BASE + base + 6);
1666     wp = (uint16 *)(ROM_BASE + ntohl(*lp) + base + 6);
1667     *wp = htons(M68K_RTS);
1668     lp = (uint32 *)(ROM_BASE + base + 12);
1669     wp = (uint16 *)(ROM_BASE + ntohl(*lp) + base + 12);
1670     *wp = htons(M68K_RTS);
1671    
1672     // Fake CPU speed test (SetupTimeK)
1673     static const uint8 timek_dat[] = {0x0c, 0x38, 0x00, 0x04, 0x01, 0x2f, 0x6d, 0x3c};
1674     if ((base = find_rom_data(0x400, 0x500, timek_dat, sizeof(timek_dat))) == 0) return false;
1675     D(bug("timek %08lx\n", base));
1676     wp = (uint16 *)(ROM_BASE + base);
1677     *wp++ = htons(0x31fc); // move.w #xxx,TimeDBRA
1678     *wp++ = htons(100);
1679     *wp++ = htons(0x0d00);
1680     *wp++ = htons(0x31fc); // move.w #xxx,TimeSCCDBRA
1681     *wp++ = htons(100);
1682     *wp++ = htons(0x0d02);
1683     *wp++ = htons(0x31fc); // move.w #xxx,TimeSCSIDBRA
1684     *wp++ = htons(100);
1685     *wp++ = htons(0x0b24);
1686     *wp++ = htons(0x31fc); // move.w #xxx,TimeRAMDBRA
1687     *wp++ = htons(100);
1688     *wp++ = htons(0x0cea);
1689     *wp = htons(M68K_RTS);
1690    
1691     // Relocate jump tables ($2000..)
1692     static const uint8 jump_tab_dat[] = {0x41, 0xfa, 0x00, 0x0e, 0x21, 0xc8, 0x20, 0x10, 0x4e, 0x75};
1693     if ((base = find_rom_data(0x3000, 0x6000, jump_tab_dat, sizeof(jump_tab_dat))) == 0) return false;
1694     D(bug("jump_tab %08lx\n", base));
1695     lp = (uint32 *)(ROM_BASE + base + 16);
1696     for (;;) {
1697     D(bug(" %08lx\n", (uint32)lp - ROM_BASE));
1698     while ((ntohl(*lp) & 0xff000000) == 0xff000000) {
1699     *lp = htonl((ntohl(*lp) & (ROM_SIZE-1)) + ROM_BASE);
1700     lp++;
1701     }
1702     while (!ntohl(*lp)) lp++;
1703     if (ntohl(*lp) != 0x41fa000e)
1704     break;
1705     lp += 4;
1706     }
1707    
1708     // Create SysZone at start of Mac RAM (SetSysAppZone, via 0x22a)
1709     static const uint8 sys_zone_dat[] = {0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x40, 0x00};
1710     if ((base = find_rom_data(0x600, 0x900, sys_zone_dat, sizeof(sys_zone_dat))) == 0) return false;
1711     D(bug("sys_zone %08lx\n", base));
1712     lp = (uint32 *)(ROM_BASE + base);
1713     *lp++ = htonl(RAMBase ? RAMBase : 0x3000);
1714     *lp = htonl(RAMBase ? RAMBase + 0x1800 : 0x4800);
1715    
1716     // Set boot stack at RAMBase+4MB and fix logical/physical RAM size (CompBootStack)
1717     // The RAM size fix must be done after InitMemMgr!
1718     static const uint8 boot_stack_dat[] = {0x08, 0x38, 0x00, 0x06, 0x24, 0x0b};
1719     if ((base = find_rom_data(0x580, 0x800, boot_stack_dat, sizeof(boot_stack_dat))) == 0) return false;
1720     D(bug("boot_stack %08lx\n", base));
1721     wp = (uint16 *)(ROM_BASE + base);
1722     *wp++ = htons(0x207c); // move.l #RAMBase+0x3ffffe,a0
1723     *wp++ = htons((RAMBase + 0x3ffffe) >> 16);
1724     *wp++ = htons((RAMBase + 0x3ffffe) & 0xffff);
1725     *wp++ = htons(M68K_EMUL_OP_FIX_MEMSIZE);
1726     *wp = htons(M68K_RTS);
1727    
1728     // Get PowerPC page size (InitVMemMgr, via 0x240)
1729     static const uint8 page_size_dat[] = {0x20, 0x30, 0x81, 0xf2, 0x5f, 0xff, 0xef, 0xd8, 0x00, 0x10};
1730     if ((base = find_rom_data(0xb000, 0x12000, page_size_dat, sizeof(page_size_dat))) == 0) return false;
1731     D(bug("page_size %08lx\n", base));
1732     wp = (uint16 *)(ROM_BASE + base);
1733     *wp++ = htons(0x203c); // move.l #$1000,d0
1734     *wp++ = htons(0);
1735     *wp++ = htons(0x1000);
1736     *wp++ = htons(M68K_NOP);
1737     *wp = htons(M68K_NOP);
1738    
1739     // Gestalt PowerPC page size, RAM size (InitGestalt, via 0x25c)
1740     static const uint8 page_size2_dat[] = {0x26, 0x79, 0x5f, 0xff, 0xef, 0xd8, 0x25, 0x6b, 0x00, 0x10, 0x00, 0x1e};
1741     if ((base = find_rom_data(0x50000, 0x70000, page_size2_dat, sizeof(page_size2_dat))) == 0) return false;
1742     D(bug("page_size2 %08lx\n", base));
1743     wp = (uint16 *)(ROM_BASE + base);
1744     *wp++ = htons(0x257c); // move.l #$1000,$1e(a2)
1745     *wp++ = htons(0);
1746     *wp++ = htons(0x1000);
1747     *wp++ = htons(0x001e);
1748     *wp++ = htons(0x157c); // move.b #PVR,$1d(a2)
1749     *wp++ = htons(PVR >> 16);
1750     *wp++ = htons(0x001d);
1751     *wp++ = htons(0x263c); // move.l #RAMSize,d3
1752     *wp++ = htons(RAMSize >> 16);
1753     *wp++ = htons(RAMSize & 0xffff);
1754     *wp++ = htons(M68K_NOP);
1755     *wp++ = htons(M68K_NOP);
1756     *wp = htons(M68K_NOP);
1757     if (ROMType == ROMTYPE_NEWWORLD)
1758     wp = (uint16 *)(ROM_BASE + base + 0x4a);
1759     else
1760     wp = (uint16 *)(ROM_BASE + base + 0x28);
1761     *wp++ = htons(M68K_NOP);
1762     *wp = htons(M68K_NOP);
1763    
1764     // Gestalt CPU/bus clock speed (InitGestalt, via 0x25c)
1765     if (ROMType == ROMTYPE_ZANZIBAR) {
1766     wp = (uint16 *)(ROM_BASE + 0x5d87a);
1767     *wp++ = htons(0x203c); // move.l #Hz,d0
1768     *wp++ = htons(BusClockSpeed >> 16);
1769     *wp++ = htons(BusClockSpeed & 0xffff);
1770     *wp++ = htons(M68K_NOP);
1771     *wp = htons(M68K_NOP);
1772     wp = (uint16 *)(ROM_BASE + 0x5d888);
1773     *wp++ = htons(0x203c); // move.l #Hz,d0
1774     *wp++ = htons(CPUClockSpeed >> 16);
1775     *wp++ = htons(CPUClockSpeed & 0xffff);
1776     *wp++ = htons(M68K_NOP);
1777     *wp = htons(M68K_NOP);
1778     }
1779    
1780     // Don't write to GC interrupt mask register (via 0x262)
1781     if (ROMType != ROMTYPE_NEWWORLD) {
1782     static const uint8 gc_mask_dat[] = {0x83, 0xa8, 0x00, 0x24, 0x4e, 0x71};
1783     if ((base = find_rom_data(0x13000, 0x20000, gc_mask_dat, sizeof(gc_mask_dat))) == 0) return false;
1784     D(bug("gc_mask %08lx\n", base));
1785     wp = (uint16 *)(ROM_BASE + base);
1786     *wp++ = htons(M68K_NOP);
1787     *wp = htons(M68K_NOP);
1788     wp = (uint16 *)(ROM_BASE + base + 0x40);
1789     *wp++ = htons(M68K_NOP);
1790     *wp = htons(M68K_NOP);
1791     wp = (uint16 *)(ROM_BASE + base + 0x78);
1792     *wp++ = htons(M68K_NOP);
1793     *wp = htons(M68K_NOP);
1794     wp = (uint16 *)(ROM_BASE + base + 0x96);
1795     *wp++ = htons(M68K_NOP);
1796     *wp = htons(M68K_NOP);
1797    
1798     static const uint8 gc_mask2_dat[] = {0x02, 0xa8, 0x00, 0x00, 0x00, 0x80, 0x00, 0x24};
1799     if ((base = find_rom_data(0x13000, 0x20000, gc_mask2_dat, sizeof(gc_mask2_dat))) == 0) return false;
1800     D(bug("gc_mask2 %08lx\n", base));
1801     wp = (uint16 *)(ROM_BASE + base);
1802 gbeauche 1.11 if (ROMType == ROMTYPE_GOSSAMER)
1803     *wp++ = htons(M68K_NOP);
1804 cebix 1.1 for (int i=0; i<5; i++) {
1805     *wp++ = htons(M68K_NOP);
1806     *wp++ = htons(M68K_NOP);
1807     *wp++ = htons(M68K_NOP);
1808     *wp++ = htons(M68K_NOP);
1809     wp += 2;
1810     }
1811 gbeauche 1.11 if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_GOSSAMER) {
1812 cebix 1.1 for (int i=0; i<6; i++) {
1813     *wp++ = htons(M68K_NOP);
1814     *wp++ = htons(M68K_NOP);
1815     *wp++ = htons(M68K_NOP);
1816     *wp++ = htons(M68K_NOP);
1817     wp += 2;
1818     }
1819     }
1820     }
1821    
1822     // Don't initialize Cuda (via 0x274)
1823     static const uint8 cuda_init_dat[] = {0x08, 0xa9, 0x00, 0x04, 0x16, 0x00, 0x4e, 0x71, 0x13, 0x7c, 0x00, 0x84, 0x1c, 0x00, 0x4e, 0x71};
1824     if ((base = find_rom_data(0xa000, 0x12000, cuda_init_dat, sizeof(cuda_init_dat))) == 0) return false;
1825     D(bug("cuda_init %08lx\n", base));
1826     wp = (uint16 *)(ROM_BASE + base);
1827     *wp++ = htons(M68K_NOP);
1828     *wp++ = htons(M68K_NOP);
1829     *wp++ = htons(M68K_NOP);
1830     *wp++ = htons(M68K_NOP);
1831     *wp++ = htons(M68K_NOP);
1832     *wp++ = htons(M68K_NOP);
1833     *wp = htons(M68K_NOP);
1834    
1835     // Patch GetCPUSpeed (via 0x27a) (some ROMs have two of them)
1836     static const uint8 cpu_speed_dat[] = {0x20, 0x30, 0x81, 0xf2, 0x5f, 0xff, 0xef, 0xd8, 0x00, 0x04, 0x4c, 0x7c};
1837 gbeauche 1.4 if ((base = find_rom_data(0x6000, 0xa000, cpu_speed_dat, sizeof(cpu_speed_dat))) == 0) return false;
1838 cebix 1.1 D(bug("cpu_speed %08lx\n", base));
1839     wp = (uint16 *)(ROM_BASE + base);
1840     *wp++ = htons(0x203c); // move.l #(MHz<<16)|MHz,d0
1841     *wp++ = htons(CPUClockSpeed / 1000000);
1842     *wp++ = htons(CPUClockSpeed / 1000000);
1843     *wp = htons(M68K_RTS);
1844 gbeauche 1.4 if ((base = find_rom_data(base, 0xa000, cpu_speed_dat, sizeof(cpu_speed_dat))) != 0) {
1845 cebix 1.1 D(bug("cpu_speed2 %08lx\n", base));
1846     wp = (uint16 *)(ROM_BASE + base);
1847     *wp++ = htons(0x203c); // move.l #(MHz<<16)|MHz,d0
1848     *wp++ = htons(CPUClockSpeed / 1000000);
1849     *wp++ = htons(CPUClockSpeed / 1000000);
1850     *wp = htons(M68K_RTS);
1851     }
1852    
1853     // Don't poke VIA in InitTimeMgr (via 0x298)
1854     static const uint8 time_via_dat[] = {0x40, 0xe7, 0x00, 0x7c, 0x07, 0x00, 0x28, 0x78, 0x01, 0xd4, 0x43, 0xec, 0x10, 0x00};
1855     if ((base = find_rom_data(0x30000, 0x40000, time_via_dat, sizeof(time_via_dat))) == 0) return false;
1856     D(bug("time_via %08lx\n", base));
1857     wp = (uint16 *)(ROM_BASE + base);
1858     *wp++ = htons(0x4cdf); // movem.l (sp)+,d0-d5/a0-a4
1859     *wp++ = htons(0x1f3f);
1860     *wp = htons(M68K_RTS);
1861    
1862     // Don't read from 0xff800000 (Name Registry, Open Firmware?) (via 0x2a2)
1863     // Remove this if FE03 works!!
1864     static const uint8 open_firmware_dat[] = {0x2f, 0x79, 0xff, 0x80, 0x00, 0x00, 0x00, 0xfc};
1865     if ((base = find_rom_data(0x48000, 0x58000, open_firmware_dat, sizeof(open_firmware_dat))) == 0) return false;
1866     D(bug("open_firmware %08lx\n", base));
1867     wp = (uint16 *)(ROM_BASE + base);
1868     *wp++ = htons(0x2f7c); // move.l #deadbeef,0xfc(a7)
1869     *wp++ = htons(0xdead);
1870     *wp++ = htons(0xbeef);
1871     *wp = htons(0x00fc);
1872     wp = (uint16 *)(ROM_BASE + base + 0x1a);
1873     *wp++ = htons(M68K_NOP); // (FE03 opcode, tries to jump to 0xdeadbeef)
1874     *wp = htons(M68K_NOP);
1875    
1876     // Don't EnableExtCache (via 0x2b2)
1877     static const uint8 ext_cache2_dat[] = {0x4f, 0xef, 0xff, 0xec, 0x20, 0x4f, 0x10, 0xbc, 0x00, 0x01, 0x11, 0x7c, 0x00, 0x1b};
1878     if ((base = find_rom_data(0x13000, 0x20000, ext_cache2_dat, sizeof(ext_cache2_dat))) == 0) return false;
1879     D(bug("ext_cache2 %08lx\n", base));
1880     wp = (uint16 *)(ROM_BASE + base);
1881     *wp = htons(M68K_RTS);
1882    
1883     // Don't install Time Manager task for 60Hz interrupt (Enable60HzInts, via 0x2b8)
1884 gbeauche 1.13 if (ROMType == ROMTYPE_NEWWORLD || ROMType == ROMTYPE_GOSSAMER) {
1885 cebix 1.1 static const uint8 tm_task_dat[] = {0x30, 0x3c, 0x4e, 0x2b, 0xa9, 0xc9};
1886 gbeauche 1.13 if ((base = find_rom_data(0x2a0, 0x320, tm_task_dat, sizeof(tm_task_dat))) == 0) return false;
1887 cebix 1.1 D(bug("tm_task %08lx\n", base));
1888 gbeauche 1.13 wp = (uint16 *)(ROM_BASE + base + 28);
1889 cebix 1.1 *wp++ = htons(M68K_NOP);
1890     *wp++ = htons(M68K_NOP);
1891     *wp++ = htons(M68K_NOP);
1892     *wp++ = htons(M68K_NOP);
1893     *wp++ = htons(M68K_NOP);
1894     *wp = htons(M68K_NOP);
1895     } else {
1896     static const uint8 tm_task_dat[] = {0x20, 0x3c, 0x73, 0x79, 0x73, 0x61};
1897     if ((base = find_rom_data(0x280, 0x300, tm_task_dat, sizeof(tm_task_dat))) == 0) return false;
1898     D(bug("tm_task %08lx\n", base));
1899     wp = (uint16 *)(ROM_BASE + base - 6);
1900     *wp++ = htons(M68K_NOP);
1901     *wp++ = htons(M68K_NOP);
1902     *wp = htons(M68K_NOP);
1903     }
1904    
1905     // Don't read PVR from 0x5fffef80 in DriverServicesLib (via 0x316)
1906 gbeauche 1.11 if (ROMType != ROMTYPE_NEWWORLD && ROMType != ROMTYPE_GOSSAMER) {
1907 cebix 1.1 uint32 dsl_offset = find_rom_resource(FOURCC('n','l','i','b'), -16401);
1908     if (ROMType == ROMTYPE_ZANZIBAR) {
1909     static const uint8 dsl_pvr_dat[] = {0x40, 0x82, 0x00, 0x40, 0x38, 0x60, 0xef, 0x80, 0x3c, 0x63, 0x60, 0x00, 0x80, 0x83, 0x00, 0x00, 0x54, 0x84, 0x84, 0x3e};
1910     if ((base = find_rom_data(dsl_offset, dsl_offset + 0x6000, dsl_pvr_dat, sizeof(dsl_pvr_dat))) == 0) return false;
1911     } else {
1912     static const uint8 dsl_pvr_dat[] = {0x3b, 0xc3, 0x00, 0x00, 0x30, 0x84, 0xff, 0xa0, 0x40, 0x82, 0x00, 0x44, 0x80, 0x84, 0xef, 0xe0, 0x54, 0x84, 0x84, 0x3e};
1913     if ((base = find_rom_data(dsl_offset, dsl_offset + 0x6000, dsl_pvr_dat, sizeof(dsl_pvr_dat))) == 0) return false;
1914     }
1915     D(bug("dsl_pvr %08lx\n", base));
1916     lp = (uint32 *)(ROM_BASE + base + 12);
1917     *lp = htonl(0x3c800000 | (PVR >> 16)); // lis r4,PVR
1918    
1919     // Don't read bus clock from 0x5fffef88 in DriverServicesLib (via 0x316)
1920     if (ROMType == ROMTYPE_ZANZIBAR) {
1921     static const uint8 dsl_bus_dat[] = {0x81, 0x07, 0x00, 0x00, 0x39, 0x20, 0x42, 0x40, 0x81, 0x62, 0xff, 0x20};
1922     if ((base = find_rom_data(dsl_offset, dsl_offset + 0x6000, dsl_bus_dat, sizeof(dsl_bus_dat))) == 0) return false;
1923     D(bug("dsl_bus %08lx\n", base));
1924     lp = (uint32 *)(ROM_BASE + base);
1925     *lp = htonl(0x81000000 + XLM_BUS_CLOCK); // lwz r8,(bus clock speed)
1926     } else {
1927     static const uint8 dsl_bus_dat[] = {0x80, 0x83, 0xef, 0xe8, 0x80, 0x62, 0x00, 0x10, 0x7c, 0x04, 0x03, 0x96};
1928     if ((base = find_rom_data(dsl_offset, dsl_offset + 0x6000, dsl_bus_dat, sizeof(dsl_bus_dat))) == 0) return false;
1929     D(bug("dsl_bus %08lx\n", base));
1930     lp = (uint32 *)(ROM_BASE + base);
1931     *lp = htonl(0x80800000 + XLM_BUS_CLOCK); // lwz r4,(bus clock speed)
1932     }
1933     }
1934    
1935     // Don't open InterruptTreeTNT in MotherBoardHAL init in DriverServicesLib init
1936     if (ROMType == ROMTYPE_ZANZIBAR) {
1937     lp = (uint32 *)(ROM_BASE + find_rom_resource(FOURCC('n','l','i','b'), -16408) + 0x16c);
1938     *lp = htonl(0x38600000); // li r3,0
1939     }
1940    
1941 gbeauche 1.19 // FIXME: Fake reading from [HpChk]+4 (the callchain reports some function from DriverServicesLib)
1942     if (1) {
1943     uint32 hpchk_offset = find_rom_resource(FOURCC('n','l','i','b'), 10);
1944     static const uint8 hpchk_dat[] = {0x80, 0x80, 0x03, 0x16, 0x94, 0x21, 0xff, 0xb0, 0x83, 0xc4, 0x00, 0x04};
1945     if ((base = find_rom_data(hpchk_offset, hpchk_offset + 0x3000, hpchk_dat, sizeof(hpchk_dat))) == 0) return false;
1946     D(bug("hpchk %08lx\n", base));
1947     lp = (uint32 *)(ROM_BASE + base);
1948     *lp = htonl(0x80800000 + XLM_ZERO_PAGE); // lwz r4,(zero page)
1949     }
1950    
1951 cebix 1.1 // Patch Name Registry
1952     static const uint8 name_reg_dat[] = {0x70, 0xff, 0xab, 0xeb};
1953     if ((base = find_rom_data(0x300, 0x380, name_reg_dat, sizeof(name_reg_dat))) == 0) return false;
1954     D(bug("name_reg %08lx\n", base));
1955     wp = (uint16 *)(ROM_BASE + base);
1956     *wp = htons(M68K_EMUL_OP_NAME_REGISTRY);
1957    
1958     #if DISABLE_SCSI
1959     // Fake SCSI Manager
1960     // Remove this if SCSI Manager works!!
1961     static const uint8 scsi_mgr_a_dat[] = {0x4e, 0x56, 0x00, 0x00, 0x20, 0x3c, 0x00, 0x00, 0x04, 0x0c, 0xa7, 0x1e};
1962     static const uint8 scsi_mgr_b_dat[] = {0x4e, 0x56, 0x00, 0x00, 0x2f, 0x0c, 0x20, 0x3c, 0x00, 0x00, 0x04, 0x0c, 0xa7, 0x1e};
1963     if ((base = find_rom_data(0x1c000, 0x28000, scsi_mgr_a_dat, sizeof(scsi_mgr_a_dat))) == 0) {
1964     if ((base = find_rom_data(0x1c000, 0x28000, scsi_mgr_b_dat, sizeof(scsi_mgr_b_dat))) == 0) return false;
1965     }
1966     D(bug("scsi_mgr %08lx\n", base));
1967     wp = (uint16 *)(ROM_BASE + base);
1968     *wp++ = htons(0x21fc); // move.l #xxx,0x624 (SCSIAtomic)
1969     *wp++ = htons((ROM_BASE + base + 18) >> 16);
1970     *wp++ = htons((ROM_BASE + base + 18) & 0xffff);
1971     *wp++ = htons(0x0624);
1972     *wp++ = htons(0x21fc); // move.l #xxx,0xe54 (SCSIDispatch)
1973     *wp++ = htons((ROM_BASE + base + 22) >> 16);
1974     *wp++ = htons((ROM_BASE + base + 22) & 0xffff);
1975     *wp++ = htons(0x0e54);
1976     *wp++ = htons(M68K_RTS);
1977     *wp++ = htons(M68K_EMUL_OP_SCSI_ATOMIC);
1978     *wp++ = htons(M68K_RTS);
1979     *wp++ = htons(M68K_EMUL_OP_SCSI_DISPATCH);
1980     *wp = htons(0x4ed0); // jmp (a0)
1981     wp = (uint16 *)(ROM_BASE + base + 0x20);
1982     *wp++ = htons(0x7000); // moveq #0,d0
1983     *wp = htons(M68K_RTS);
1984     #endif
1985    
1986     #if DISABLE_SCSI
1987     // Don't access SCSI variables
1988     // Remove this if SCSI Manager works!!
1989     if (ROMType == ROMTYPE_NEWWORLD) {
1990     static const uint8 scsi_var_dat[] = {0x70, 0x01, 0xa0, 0x89, 0x4a, 0x6e, 0xfe, 0xac, 0x4f, 0xef, 0x00, 0x10, 0x66, 0x00};
1991     if ((base = find_rom_data(0x1f500, 0x1f600, scsi_var_dat, sizeof(scsi_var_dat))) != 0) {
1992     D(bug("scsi_var %08lx\n", base));
1993     wp = (uint16 *)(ROM_BASE + base + 12);
1994     *wp = htons(0x6000); // bra
1995     }
1996    
1997     static const uint8 scsi_var2_dat[] = {0x4e, 0x56, 0xfc, 0x58, 0x48, 0xe7, 0x1f, 0x38};
1998     if ((base = find_rom_data(0x1f700, 0x1f800, scsi_var2_dat, sizeof(scsi_var2_dat))) != 0) {
1999     D(bug("scsi_var2 %08lx\n", base));
2000     wp = (uint16 *)(ROM_BASE + base);
2001     *wp++ = htons(0x7000); // moveq #0,d0
2002 gbeauche 1.11 *wp = htons(M68K_RTS);
2003     }
2004     }
2005     else if (ROMType == ROMTYPE_GOSSAMER) {
2006     static const uint8 scsi_var_dat[] = {0x70, 0x01, 0xa0, 0x89, 0x4a, 0x6e, 0xfe, 0xac, 0x4f, 0xef, 0x00, 0x10, 0x66, 0x00};
2007     if ((base = find_rom_data(0x1d700, 0x1d800, scsi_var_dat, sizeof(scsi_var_dat))) != 0) {
2008     D(bug("scsi_var %08lx\n", base));
2009     wp = (uint16 *)(ROM_BASE + base + 12);
2010     *wp = htons(0x6000); // bra
2011     }
2012    
2013     static const uint8 scsi_var2_dat[] = {0x4e, 0x56, 0xfc, 0x5a, 0x48, 0xe7, 0x1f, 0x38};
2014     if ((base = find_rom_data(0x1d900, 0x1da00, scsi_var2_dat, sizeof(scsi_var2_dat))) != 0) {
2015     D(bug("scsi_var2 %08lx\n", base));
2016     wp = (uint16 *)(ROM_BASE + base);
2017     *wp++ = htons(0x7000); // moveq #0,d0
2018     *wp = htons(M68K_RTS);
2019 cebix 1.1 }
2020     }
2021     #endif
2022    
2023     // Don't wait in ADBInit (via 0x36c)
2024     static const uint8 adb_init_dat[] = {0x08, 0x2b, 0x00, 0x05, 0x01, 0x5d, 0x66, 0xf8};
2025     if ((base = find_rom_data(0x31000, 0x3d000, adb_init_dat, sizeof(adb_init_dat))) == 0) return false;
2026     D(bug("adb_init %08lx\n", base));
2027     wp = (uint16 *)(ROM_BASE + base + 6);
2028     *wp = htons(M68K_NOP);
2029    
2030     // Modify check in InitResources() so that addresses >0x80000000 work
2031     static const uint8 init_res_dat[] = {0x4a, 0xb8, 0x0a, 0x50, 0x6e, 0x20};
2032     if ((base = find_rom_data(0x78000, 0x8c000, init_res_dat, sizeof(init_res_dat))) == 0) return false;
2033     D(bug("init_res %08lx\n", base));
2034     bp = (uint8 *)(ROM_BASE + base + 4);
2035     *bp = 0x66;
2036    
2037     // Modify vCheckLoad() so that we can patch resources (68k Resource Manager)
2038     static const uint8 check_load_dat[] = {0x20, 0x78, 0x07, 0xf0, 0x4e, 0xd0};
2039     if ((base = find_rom_data(0x78000, 0x8c000, check_load_dat, sizeof(check_load_dat))) == 0) return false;
2040     D(bug("check_load %08lx\n", base));
2041     wp = (uint16 *)(ROM_BASE + base);
2042     *wp++ = htons(M68K_JMP);
2043     *wp++ = htons((ROM_BASE + CHECK_LOAD_PATCH_SPACE) >> 16);
2044     *wp = htons((ROM_BASE + CHECK_LOAD_PATCH_SPACE) & 0xffff);
2045     wp = (uint16 *)(ROM_BASE + CHECK_LOAD_PATCH_SPACE);
2046     *wp++ = htons(0x2f03); // move.l d3,-(a7)
2047     *wp++ = htons(0x2078); // move.l $07f0,a0
2048     *wp++ = htons(0x07f0);
2049     *wp++ = htons(M68K_JSR_A0);
2050     *wp++ = htons(M68K_EMUL_OP_CHECKLOAD);
2051     *wp = htons(M68K_RTS);
2052    
2053     // Replace .Sony driver
2054     sony_offset = find_rom_resource(FOURCC('D','R','V','R'), 4);
2055     if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_NEWWORLD)
2056     sony_offset = find_rom_resource(FOURCC('D','R','V','R'), 4, true); // First DRVR 4 is .MFMFloppy
2057     if (sony_offset == 0) {
2058     sony_offset = find_rom_resource(FOURCC('n','d','r','v'), -20196); // NewWorld 1.6 has "PCFloppy" ndrv
2059     if (sony_offset == 0)
2060     return false;
2061     lp = (uint32 *)(ROM_BASE + rsrc_ptr + 8);
2062     *lp = htonl(FOURCC('D','R','V','R'));
2063     wp = (uint16 *)(ROM_BASE + rsrc_ptr + 12);
2064     *wp = htons(4);
2065     }
2066     D(bug("sony_offset %08lx\n", sony_offset));
2067     memcpy((void *)(ROM_BASE + sony_offset), sony_driver, sizeof(sony_driver));
2068    
2069     // Install .Disk and .AppleCD drivers
2070     memcpy((void *)(ROM_BASE + sony_offset + 0x100), disk_driver, sizeof(disk_driver));
2071     memcpy((void *)(ROM_BASE + sony_offset + 0x200), cdrom_driver, sizeof(cdrom_driver));
2072    
2073     // Install serial drivers
2074 gbeauche 1.18 gen_ain_driver( ROM_BASE + sony_offset + 0x300);
2075     gen_aout_driver(ROM_BASE + sony_offset + 0x400);
2076     gen_bin_driver( ROM_BASE + sony_offset + 0x500);
2077     gen_bout_driver(ROM_BASE + sony_offset + 0x600);
2078 cebix 1.1
2079     // Copy icons to ROM
2080     SonyDiskIconAddr = ROM_BASE + sony_offset + 0x800;
2081     memcpy((void *)(ROM_BASE + sony_offset + 0x800), SonyDiskIcon, sizeof(SonyDiskIcon));
2082     SonyDriveIconAddr = ROM_BASE + sony_offset + 0xa00;
2083     memcpy((void *)(ROM_BASE + sony_offset + 0xa00), SonyDriveIcon, sizeof(SonyDriveIcon));
2084     DiskIconAddr = ROM_BASE + sony_offset + 0xc00;
2085     memcpy((void *)(ROM_BASE + sony_offset + 0xc00), DiskIcon, sizeof(DiskIcon));
2086     CDROMIconAddr = ROM_BASE + sony_offset + 0xe00;
2087     memcpy((void *)(ROM_BASE + sony_offset + 0xe00), CDROMIcon, sizeof(CDROMIcon));
2088    
2089     // Patch driver install routine
2090     static const uint8 drvr_install_dat[] = {0xa7, 0x1e, 0x21, 0xc8, 0x01, 0x1c, 0x4e, 0x75};
2091     if ((base = find_rom_data(0xb00, 0xd00, drvr_install_dat, sizeof(drvr_install_dat))) == 0) return false;
2092     D(bug("drvr_install %08lx\n", base));
2093     wp = (uint16 *)(ROM_BASE + base + 8);
2094     *wp++ = htons(M68K_EMUL_OP_INSTALL_DRIVERS);
2095     *wp = htons(M68K_RTS);
2096    
2097     // Don't install serial drivers from ROM
2098 gbeauche 1.11 if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_NEWWORLD || ROMType == ROMTYPE_GOSSAMER) {
2099 cebix 1.1 wp = (uint16 *)(ROM_BASE + find_rom_resource(FOURCC('S','E','R','D'), 0));
2100     *wp = htons(M68K_RTS);
2101     } else {
2102     wp = (uint16 *)(ROM_BASE + find_rom_resource(FOURCC('s','l','0','5'), 2) + 0xc4);
2103     *wp++ = htons(M68K_NOP);
2104     *wp++ = htons(M68K_NOP);
2105     *wp++ = htons(M68K_NOP);
2106     *wp++ = htons(M68K_NOP);
2107     *wp = htons(0x7000); // moveq #0,d0
2108     wp = (uint16 *)(ROM_BASE + find_rom_resource(FOURCC('s','l','0','5'), 2) + 0x8ee);
2109     *wp = htons(M68K_NOP);
2110     }
2111     uint32 nsrd_offset = find_rom_resource(FOURCC('n','s','r','d'), 1);
2112     if (nsrd_offset) {
2113     lp = (uint32 *)(ROM_BASE + rsrc_ptr + 8);
2114     *lp = htonl(FOURCC('x','s','r','d'));
2115     }
2116    
2117     // Replace ADBOp()
2118     memcpy((void *)(ROM_BASE + find_rom_trap(0xa07c)), adbop_patch, sizeof(adbop_patch));
2119    
2120     // Replace Time Manager
2121     wp = (uint16 *)(ROM_BASE + find_rom_trap(0xa058));
2122     *wp++ = htons(M68K_EMUL_OP_INSTIME);
2123     *wp = htons(M68K_RTS);
2124     wp = (uint16 *)(ROM_BASE + find_rom_trap(0xa059));
2125     *wp++ = htons(0x40e7); // move sr,-(sp)
2126     *wp++ = htons(0x007c); // ori #$0700,sr
2127     *wp++ = htons(0x0700);
2128     *wp++ = htons(M68K_EMUL_OP_RMVTIME);
2129     *wp++ = htons(0x46df); // move (sp)+,sr
2130     *wp = htons(M68K_RTS);
2131     wp = (uint16 *)(ROM_BASE + find_rom_trap(0xa05a));
2132     *wp++ = htons(0x40e7); // move sr,-(sp)
2133     *wp++ = htons(0x007c); // ori #$0700,sr
2134     *wp++ = htons(0x0700);
2135     *wp++ = htons(M68K_EMUL_OP_PRIMETIME);
2136     *wp++ = htons(0x46df); // move (sp)+,sr
2137     *wp = htons(M68K_RTS);
2138     wp = (uint16 *)(ROM_BASE + find_rom_trap(0xa093));
2139     *wp++ = htons(M68K_EMUL_OP_MICROSECONDS);
2140     *wp = htons(M68K_RTS);
2141    
2142     // Disable Egret Manager
2143     static const uint8 egret_dat[] = {0x2f, 0x30, 0x81, 0xe2, 0x20, 0x10, 0x00, 0x18};
2144     if ((base = find_rom_data(0xa000, 0x10000, egret_dat, sizeof(egret_dat))) == 0) return false;
2145     D(bug("egret %08lx\n", base));
2146     wp = (uint16 *)(ROM_BASE + base);
2147     *wp++ = htons(0x7000);
2148     *wp = htons(M68K_RTS);
2149    
2150     // Don't call FE0A opcode in Shutdown Manager
2151     static const uint8 shutdown_dat[] = {0x40, 0xe7, 0x00, 0x7c, 0x07, 0x00, 0x48, 0xe7, 0x3f, 0x00, 0x2c, 0x00, 0x2e, 0x01};
2152     if ((base = find_rom_data(0x30000, 0x40000, shutdown_dat, sizeof(shutdown_dat))) == 0) return false;
2153     D(bug("shutdown %08lx\n", base));
2154     wp = (uint16 *)(ROM_BASE + base);
2155     if (ROMType == ROMTYPE_ZANZIBAR)
2156     *wp = htons(M68K_RTS);
2157 gbeauche 1.6 else if (ntohs(wp[-4]) == 0x61ff)
2158     *wp = htons(M68K_RTS);
2159     else if (ntohs(wp[-2]) == 0x6700)
2160 cebix 1.1 wp[-2] = htons(0x6000); // bra
2161    
2162     // Patch PowerOff()
2163     wp = (uint16 *)(ROM_BASE + find_rom_trap(0xa05b)); // PowerOff()
2164     *wp = htons(M68K_EMUL_RETURN);
2165    
2166     // Patch VIA interrupt handler
2167     static const uint8 via_int_dat[] = {0x70, 0x7f, 0xc0, 0x29, 0x1a, 0x00, 0xc0, 0x29, 0x1c, 0x00};
2168     if ((base = find_rom_data(0x13000, 0x1c000, via_int_dat, sizeof(via_int_dat))) == 0) return false;
2169     D(bug("via_int %08lx\n", base));
2170     uint32 level1_int = ROM_BASE + base;
2171     wp = (uint16 *)level1_int; // Level 1 handler
2172     *wp++ = htons(0x7002); // moveq #2,d0 (60Hz interrupt)
2173     *wp++ = htons(M68K_NOP);
2174     *wp++ = htons(M68K_NOP);
2175     *wp++ = htons(M68K_NOP);
2176     *wp = htons(M68K_NOP);
2177    
2178     static const uint8 via_int2_dat[] = {0x13, 0x7c, 0x00, 0x02, 0x1a, 0x00, 0x4e, 0x71, 0x52, 0xb8, 0x01, 0x6a};
2179     if ((base = find_rom_data(0x10000, 0x18000, via_int2_dat, sizeof(via_int2_dat))) == 0) return false;
2180     D(bug("via_int2 %08lx\n", base));
2181     wp = (uint16 *)(ROM_BASE + base); // 60Hz handler
2182     *wp++ = htons(M68K_EMUL_OP_IRQ);
2183     *wp++ = htons(0x4a80); // tst.l d0
2184     *wp++ = htons(0x6700); // beq xxx
2185     *wp = htons(0xffe8);
2186    
2187     if (ROMType == ROMTYPE_NEWWORLD) {
2188     static const uint8 via_int3_dat[] = {0x48, 0xe7, 0xf0, 0xf0, 0x76, 0x01, 0x60, 0x26};
2189 gbeauche 1.4 if ((base = find_rom_data(0x15000, 0x19000, via_int3_dat, sizeof(via_int3_dat))) == 0) return false;
2190 cebix 1.1 D(bug("via_int3 %08lx\n", base));
2191     wp = (uint16 *)(ROM_BASE + base); // CHRP level 1 handler
2192     *wp++ = htons(M68K_JMP);
2193     *wp++ = htons((level1_int - 12) >> 16);
2194     *wp = htons((level1_int - 12) & 0xffff);
2195     }
2196    
2197     // Patch PutScrap() for clipboard exchange with host OS
2198     uint32 put_scrap = find_rom_trap(0xa9fe); // PutScrap()
2199     wp = (uint16 *)(ROM_BASE + PUT_SCRAP_PATCH_SPACE);
2200     *wp++ = htons(M68K_EMUL_OP_PUT_SCRAP);
2201     *wp++ = htons(M68K_JMP);
2202     *wp++ = htons((ROM_BASE + put_scrap) >> 16);
2203     *wp++ = htons((ROM_BASE + put_scrap) & 0xffff);
2204     lp = (uint32 *)(ROM_BASE + 0x22);
2205     lp = (uint32 *)(ROM_BASE + ntohl(*lp));
2206     lp[0xa9fe & 0x3ff] = htonl(PUT_SCRAP_PATCH_SPACE);
2207    
2208     // Patch GetScrap() for clipboard exchange with host OS
2209     uint32 get_scrap = find_rom_trap(0xa9fd); // GetScrap()
2210     wp = (uint16 *)(ROM_BASE + GET_SCRAP_PATCH_SPACE);
2211     *wp++ = htons(M68K_EMUL_OP_GET_SCRAP);
2212     *wp++ = htons(M68K_JMP);
2213     *wp++ = htons((ROM_BASE + get_scrap) >> 16);
2214     *wp++ = htons((ROM_BASE + get_scrap) & 0xffff);
2215     lp = (uint32 *)(ROM_BASE + 0x22);
2216     lp = (uint32 *)(ROM_BASE + ntohl(*lp));
2217     lp[0xa9fd & 0x3ff] = htonl(GET_SCRAP_PATCH_SPACE);
2218    
2219     // Patch SynchIdleTime()
2220     if (PrefsFindBool("idlewait")) {
2221     wp = (uint16 *)(ROM_BASE + find_rom_trap(0xabf7) + 4); // SynchIdleTime()
2222     D(bug("SynchIdleTime at %08lx\n", wp));
2223 gbeauche 1.28 if (ntohs(*wp) == 0x2078) { // movea.l ExpandMem,a0
2224 cebix 1.1 *wp++ = htons(M68K_EMUL_OP_IDLE_TIME);
2225     *wp = htons(M68K_NOP);
2226 gbeauche 1.28 }
2227     else if (ntohs(*wp) == 0x70fe) // moveq #-2,d0
2228     *wp++ = htons(M68K_EMUL_OP_IDLE_TIME_2);
2229     else {
2230 cebix 1.1 D(bug("SynchIdleTime patch not installed\n"));
2231     }
2232     }
2233    
2234     // Construct list of all sifters used by sound components in ROM
2235     D(bug("Searching for sound components with type sdev in ROM\n"));
2236     uint32 thing = find_rom_resource(FOURCC('t','h','n','g'));
2237     while (thing) {
2238     thing += ROM_BASE;
2239     D(bug(" found %c%c%c%c %c%c%c%c\n", ReadMacInt8(thing), ReadMacInt8(thing + 1), ReadMacInt8(thing + 2), ReadMacInt8(thing + 3), ReadMacInt8(thing + 4), ReadMacInt8(thing + 5), ReadMacInt8(thing + 6), ReadMacInt8(thing + 7)));
2240     if (ReadMacInt32(thing) == FOURCC('s','d','e','v') && ReadMacInt32(thing + 4) == FOURCC('s','i','n','g')) {
2241     WriteMacInt32(thing + 4, FOURCC('a','w','g','c'));
2242     D(bug(" found sdev component at offset %08x in ROM\n", thing));
2243     AddSifter(ReadMacInt32(thing + componentResType), ReadMacInt16(thing + componentResID));
2244     if (ReadMacInt32(thing + componentPFCount))
2245     AddSifter(ReadMacInt32(thing + componentPFResType), ReadMacInt16(thing + componentPFResID));
2246     }
2247     thing = find_rom_resource(FOURCC('t','h','n','g'), 4711, true);
2248     }
2249    
2250     // Patch component code
2251     D(bug("Patching sifters in ROM\n"));
2252     for (int i=0; i<num_sifters; i++) {
2253     if ((thing = find_rom_resource(sifter_list[i].type, sifter_list[i].id)) != 0) {
2254     D(bug(" patching type %08x, id %d\n", sifter_list[i].type, sifter_list[i].id));
2255     // Install 68k glue code
2256     uint16 *wp = (uint16 *)(ROM_BASE + thing);
2257     *wp++ = htons(0x4e56); *wp++ = htons(0x0000); // link a6,#0
2258     *wp++ = htons(0x48e7); *wp++ = htons(0x8018); // movem.l d0/a3-a4,-(a7)
2259     *wp++ = htons(0x266e); *wp++ = htons(0x000c); // movea.l $c(a6),a3
2260     *wp++ = htons(0x286e); *wp++ = htons(0x0008); // movea.l $8(a6),a4
2261     *wp++ = htons(M68K_EMUL_OP_AUDIO_DISPATCH);
2262     *wp++ = htons(0x2d40); *wp++ = htons(0x0010); // move.l d0,$10(a6)
2263     *wp++ = htons(0x4cdf); *wp++ = htons(0x1801); // movem.l (a7)+,d0/a3-a4
2264     *wp++ = htons(0x4e5e); // unlk a6
2265     *wp++ = htons(0x4e74); *wp++ = htons(0x0008); // rtd #8
2266     }
2267     }
2268     return true;
2269     }
2270    
2271    
2272     /*
2273     * Install .Sony, disk and CD-ROM drivers
2274     */
2275    
2276     void InstallDrivers(void)
2277     {
2278     D(bug("Installing drivers...\n"));
2279     M68kRegisters r;
2280 gbeauche 1.18 SheepArray<SIZEOF_IOParam> pb_var;
2281     const uintptr pb = pb_var.addr();
2282 gbeauche 1.7
2283 gbeauche 1.5 // Install floppy driver
2284 gbeauche 1.14 if (ROMType == ROMTYPE_NEWWORLD || ROMType == ROMTYPE_GOSSAMER) {
2285 gbeauche 1.5
2286 gbeauche 1.14 // Force installation of floppy driver with NewWorld and Gossamer ROMs
2287 gbeauche 1.5 r.a[0] = ROM_BASE + sony_offset;
2288     r.d[0] = (uint32)SonyRefNum;
2289     Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem()
2290     r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~SonyRefNum * 4); // Get driver handle from Unit Table
2291     Execute68kTrap(0xa029, &r); // HLock()
2292     uint32 dce = ReadMacInt32(r.a[0]);
2293     WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset);
2294     WriteMacInt16(dce + dCtlFlags, SonyDriverFlags);
2295     }
2296 gbeauche 1.8
2297 gbeauche 1.27 #if DISABLE_SCSI && HAVE_SIGSEGV_SKIP_INSTRUCTION
2298 gbeauche 1.8 // Fake SCSIGlobals
2299 gbeauche 1.19 WriteMacInt32(0xc0c, SheepMem::ZeroPage());
2300 gbeauche 1.8 #endif
2301 gbeauche 1.5
2302 cebix 1.1 // Open .Sony driver
2303 gbeauche 1.18 SheepString sony_str("\005.Sony");
2304     WriteMacInt8(pb + ioPermssn, 0);
2305     WriteMacInt32(pb + ioNamePtr, sony_str.addr());
2306     r.a[0] = pb;
2307 cebix 1.1 Execute68kTrap(0xa000, &r); // Open()
2308    
2309     // Install disk driver
2310     r.a[0] = ROM_BASE + sony_offset + 0x100;
2311     r.d[0] = (uint32)DiskRefNum;
2312     Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem()
2313     r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~DiskRefNum * 4); // Get driver handle from Unit Table
2314     Execute68kTrap(0xa029, &r); // HLock()
2315     uint32 dce = ReadMacInt32(r.a[0]);
2316     WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x100);
2317     WriteMacInt16(dce + dCtlFlags, DiskDriverFlags);
2318    
2319     // Open disk driver
2320 gbeauche 1.18 SheepString disk_str("\005.Disk");
2321     WriteMacInt32(pb + ioNamePtr, disk_str.addr());
2322     r.a[0] = pb;
2323 cebix 1.1 Execute68kTrap(0xa000, &r); // Open()
2324    
2325     // Install CD-ROM driver unless nocdrom option given
2326     if (!PrefsFindBool("nocdrom")) {
2327    
2328     // Install CD-ROM driver
2329     r.a[0] = ROM_BASE + sony_offset + 0x200;
2330     r.d[0] = (uint32)CDROMRefNum;
2331     Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem()
2332     r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~CDROMRefNum * 4); // Get driver handle from Unit Table
2333     Execute68kTrap(0xa029, &r); // HLock()
2334     dce = ReadMacInt32(r.a[0]);
2335     WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x200);
2336     WriteMacInt16(dce + dCtlFlags, CDROMDriverFlags);
2337    
2338     // Open CD-ROM driver
2339 gbeauche 1.18 SheepString apple_cd("\010.AppleCD");
2340     WriteMacInt32(pb + ioNamePtr, apple_cd.addr());
2341     r.a[0] = pb;
2342 cebix 1.1 Execute68kTrap(0xa000, &r); // Open()
2343     }
2344    
2345     // Install serial drivers
2346     r.a[0] = ROM_BASE + sony_offset + 0x300;
2347     r.d[0] = (uint32)-6;
2348     Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem()
2349     r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~(-6) * 4); // Get driver handle from Unit Table
2350     Execute68kTrap(0xa029, &r); // HLock()
2351     dce = ReadMacInt32(r.a[0]);
2352     WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x300);
2353     WriteMacInt16(dce + dCtlFlags, 0x4d00);
2354    
2355     r.a[0] = ROM_BASE + sony_offset + 0x400;
2356     r.d[0] = (uint32)-7;
2357     Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem()
2358     r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~(-7) * 4); // Get driver handle from Unit Table
2359     Execute68kTrap(0xa029, &r); // HLock()
2360     dce = ReadMacInt32(r.a[0]);
2361     WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x400);
2362     WriteMacInt16(dce + dCtlFlags, 0x4e00);
2363    
2364     r.a[0] = ROM_BASE + sony_offset + 0x500;
2365     r.d[0] = (uint32)-8;
2366     Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem()
2367     r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~(-8) * 4); // Get driver handle from Unit Table
2368     Execute68kTrap(0xa029, &r); // HLock()
2369     dce = ReadMacInt32(r.a[0]);
2370     WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x500);
2371     WriteMacInt16(dce + dCtlFlags, 0x4d00);
2372    
2373     r.a[0] = ROM_BASE + sony_offset + 0x600;
2374     r.d[0] = (uint32)-9;
2375     Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem()
2376     r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~(-9) * 4); // Get driver handle from Unit Table
2377     Execute68kTrap(0xa029, &r); // HLock()
2378     dce = ReadMacInt32(r.a[0]);
2379     WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x600);
2380     WriteMacInt16(dce + dCtlFlags, 0x4e00);
2381     }