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root/cebix/SheepShaver/src/rom_patches.cpp
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Comparing SheepShaver/src/rom_patches.cpp (file contents):
Revision 1.11 by gbeauche, 2003-10-05T23:05:03Z vs.
Revision 1.32 by gbeauche, 2004-06-30T08:17:12Z

# Line 1 | Line 1
1   /*
2   *  rom_patches.cpp - ROM patches
3   *
4 < *  SheepShaver (C) 1997-2002 Christian Bauer and Marc Hellwig
4 > *  SheepShaver (C) 1997-2004 Christian Bauer and Marc Hellwig
5   *
6   *  This program is free software; you can redistribute it and/or modify
7   *  it under the terms of the GNU General Public License as published by
# Line 40 | Line 40
40   #include "audio_defs.h"
41   #include "serial.h"
42   #include "macos_util.h"
43 + #include "thunks.h"
44  
45   #define DEBUG 0
46   #include "debug.h"
# Line 58 | Line 59
59  
60  
61   // Other ROM addresses
62 < const uint32 CHECK_LOAD_PATCH_SPACE = 0x2f7f00;
63 < const uint32 PUT_SCRAP_PATCH_SPACE = 0x2f7f80;
64 < const uint32 GET_SCRAP_PATCH_SPACE = 0x2f7fc0;
65 < const uint32 ADDR_MAP_PATCH_SPACE = 0x2f8000;
62 > const uint32 CHECK_LOAD_PATCH_SPACE = 0x2fcf00;
63 > const uint32 PUT_SCRAP_PATCH_SPACE = 0x2fcf80;
64 > const uint32 GET_SCRAP_PATCH_SPACE = 0x2fcfc0;
65 > const uint32 ADDR_MAP_PATCH_SPACE = 0x2fd100;
66  
67   // Global variables
68   int ROMType;                            // ROM type
# Line 131 | Line 132 | void decode_parcels(const uint8 *src, ui
132                            (parcel_type >> 8) & 0xff, parcel_type & 0xff, &parcel_data[6]));
133                  if (parcel_type == FOURCC('r','o','m',' ')) {
134                          uint32 lzss_offset  = ntohl(parcel_data[2]);
135 <                        uint32 lzss_size = ((uint32)src + parcel_offset) - ((uint32)parcel_data + lzss_offset);
135 >                        uint32 lzss_size = ((uintptr)src + next_offset) - ((uintptr)parcel_data + lzss_offset);
136                          decode_lzss((uint8 *)parcel_data + lzss_offset, dest, lzss_size);
137                  }
138                  parcel_offset = next_offset;
# Line 269 | Line 270 | static uint32 find_rom_trap(uint16 trap)
270  
271  
272   /*
273 + *  Return target of branch instruction specified at ADDR, or 0 if
274 + *  there is no such instruction
275 + */
276 +
277 + static uint32 powerpc_branch_target(uintptr addr)
278 + {
279 +        uint32 opcode = ntohl(*(uint32 *)addr);
280 +        uint32 primop = opcode >> 26;
281 +        uint32 target = 0;
282 +
283 +        if (primop == 18) {                     // Branch
284 +                target = opcode & 0x3fffffc;
285 +                if (target & 0x2000000)
286 +                        target |= 0xfc000000;
287 +                if ((opcode & 2) == 0)
288 +                        target += addr;
289 +        }
290 +        else if (primop == 16) {        // Branch Conditional
291 +                target = (int32)(int16)(opcode & 0xfffc);
292 +                if ((opcode & 2) == 0)
293 +                        target += addr;
294 +        }
295 +        return target;
296 + }
297 +
298 +
299 + /*
300 + *  Search ROM for instruction branching to target address, return 0 if none found
301 + */
302 +
303 + static uint32 find_rom_powerpc_branch(uint32 start, uint32 end, uint32 target)
304 + {
305 +        for (uint32 addr = start; addr < end; addr += 4) {
306 +                if (powerpc_branch_target(ROM_BASE + addr) == ROM_BASE + target)
307 +                        return addr;
308 +        }
309 +        return 0;
310 + }
311 +
312 +
313 + /*
314 + *  Check that requested ROM patch space is really available
315 + */
316 +
317 + static bool check_rom_patch_space(uint32 base, uint32 size)
318 + {
319 +        size = (size + 3) & -4;
320 +        for (int i = 0; i < size; i += 4) {
321 +                uint32 x = ntohl(*(uint32 *)(ROM_BASE + base + i));
322 +                if (x != 0x6b636b63 && x != 0)
323 +                        return false;
324 +        }
325 +        return true;
326 + }
327 +
328 +
329 + /*
330   *  List of audio sifters installed in ROM and System file
331   */
332  
# Line 447 | Line 505 | static const uint8 cdrom_driver[] = {  //
505          0x4e, 0x75                                                      //  rts
506   };
507  
508 < #if EMULATED_PPC
451 < #define SERIAL_TRAMPOLINES 1
452 < static uint32 serial_nothing_tvect[2] = {tswap32(POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_NOTHING)), 0};
453 < static uint32 serial_open_tvect[2] = {tswap32(POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_OPEN)), 0};
454 < static uint32 serial_prime_in_tvect[2] = {tswap32(POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_PRIME_IN)), 0};
455 < static uint32 serial_prime_out_tvect[2] = {tswap32(POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_PRIME_OUT)), 0};
456 < static uint32 serial_control_tvect[2] = {tswap32(POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_CONTROL)), 0};
457 < static uint32 serial_status_tvect[2] = {tswap32(POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_STATUS)), 0};
458 < static uint32 serial_close_tvect[2] = {tswap32(POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_CLOSE)), 0};
459 < #elif defined(__linux__)
460 < #define SERIAL_TRAMPOLINES 1
461 < static uint32 serial_nothing_tvect[2] = {(uint32)SerialNothing, 0};
462 < static uint32 serial_open_tvect[2] = {(uint32)SerialOpen, 0};
463 < static uint32 serial_prime_in_tvect[2] = {(uint32)SerialPrimeIn, 0};
464 < static uint32 serial_prime_out_tvect[2] = {(uint32)SerialPrimeOut, 0};
465 < static uint32 serial_control_tvect[2] = {(uint32)SerialControl, 0};
466 < static uint32 serial_status_tvect[2] = {(uint32)SerialStatus, 0};
467 < static uint32 serial_close_tvect[2] = {(uint32)SerialClose, 0};
468 < #endif
508 > static uint32 long_ptr;
509  
510 < static const uint32 ain_driver[] = {    // .AIn driver header
511 <        0x4d000000, 0x00000000,
512 <        0x00200040, 0x00600080,
513 <        0x00a0042e, 0x41496e00,
514 <        0x00000000, 0x00000000,
515 <        0xaafe0700, 0x00000000,
516 <        0x00000000, 0x00179822,
517 < #ifdef SERIAL_TRAMPOLINES
518 <        0x00010004, (uint32)serial_nothing_tvect,
519 < #else
520 <        0x00010004, (uint32)SerialNothing,
521 < #endif
522 <        0x00000000, 0x00000000,
523 <        0xaafe0700, 0x00000000,
524 <        0x00000000, 0x00179822,
525 < #ifdef SERIAL_TRAMPOLINES
526 <        0x00010004, (uint32)serial_prime_in_tvect,
527 < #else
528 <        0x00010004, (uint32)SerialPrimeIn,
529 < #endif
530 <        0x00000000, 0x00000000,
531 <        0xaafe0700, 0x00000000,
532 <        0x00000000, 0x00179822,
533 < #ifdef SERIAL_TRAMPOLINES
534 <        0x00010004, (uint32)serial_control_tvect,
535 < #else
536 <        0x00010004, (uint32)SerialControl,
537 < #endif
538 <        0x00000000, 0x00000000,
539 <        0xaafe0700, 0x00000000,
540 <        0x00000000, 0x00179822,
541 < #ifdef SERIAL_TRAMPOLINES
542 <        0x00010004, (uint32)serial_status_tvect,
543 < #else
544 <        0x00010004, (uint32)SerialStatus,
545 < #endif
546 <        0x00000000, 0x00000000,
547 <        0xaafe0700, 0x00000000,
548 <        0x00000000, 0x00179822,
549 < #ifdef SERIAL_TRAMPOLINES
510 <        0x00010004, (uint32)serial_nothing_tvect,
511 < #else
512 <        0x00010004, (uint32)SerialNothing,
513 < #endif
514 <        0x00000000, 0x00000000,
510 > static void SetLongBase(uint32 addr)
511 > {
512 >        long_ptr = addr;
513 > }
514 >
515 > static void Long(uint32 value)
516 > {
517 >        WriteMacInt32(long_ptr, value);
518 >        long_ptr += 4;
519 > }
520 >
521 > static void gen_ain_driver(uintptr addr)
522 > {
523 >        SetLongBase(addr);
524 >
525 >        // .AIn driver header
526 >        Long(0x4d000000); Long(0x00000000);
527 >        Long(0x00200040); Long(0x00600080);
528 >        Long(0x00a0042e); Long(0x41496e00);
529 >        Long(0x00000000); Long(0x00000000);
530 >        Long(0xaafe0700); Long(0x00000000);
531 >        Long(0x00000000); Long(0x00179822);
532 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_NOTHING));
533 >        Long(0x00000000); Long(0x00000000);
534 >        Long(0xaafe0700); Long(0x00000000);
535 >        Long(0x00000000); Long(0x00179822);
536 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_PRIME_IN));
537 >        Long(0x00000000); Long(0x00000000);
538 >        Long(0xaafe0700); Long(0x00000000);
539 >        Long(0x00000000); Long(0x00179822);
540 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CONTROL));
541 >        Long(0x00000000); Long(0x00000000);
542 >        Long(0xaafe0700); Long(0x00000000);
543 >        Long(0x00000000); Long(0x00179822);
544 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_STATUS));
545 >        Long(0x00000000); Long(0x00000000);
546 >        Long(0xaafe0700); Long(0x00000000);
547 >        Long(0x00000000); Long(0x00179822);
548 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_NOTHING));
549 >        Long(0x00000000); Long(0x00000000);
550   };
551  
552 < static const uint32 aout_driver[] = {   // .AOut driver header
553 <        0x4d000000, 0x00000000,
554 <        0x00200040, 0x00600080,
555 <        0x00a0052e, 0x414f7574,
556 <        0x00000000, 0x00000000,
557 <        0xaafe0700, 0x00000000,
558 <        0x00000000, 0x00179822,
559 < #ifdef SERIAL_TRAMPOLINES
560 <        0x00010004, (uint32)serial_open_tvect,
561 < #else
562 <        0x00010004, (uint32)SerialOpen,
563 < #endif
564 <        0x00000000, 0x00000000,
565 <        0xaafe0700, 0x00000000,
566 <        0x00000000, 0x00179822,
567 < #ifdef SERIAL_TRAMPOLINES
568 <        0x00010004, (uint32)serial_prime_out_tvect,
569 < #else
570 <        0x00010004, (uint32)SerialPrimeOut,
571 < #endif
572 <        0x00000000, 0x00000000,
573 <        0xaafe0700, 0x00000000,
574 <        0x00000000, 0x00179822,
575 < #ifdef SERIAL_TRAMPOLINES
576 <        0x00010004, (uint32)serial_control_tvect,
577 < #else
578 <        0x00010004, (uint32)SerialControl,
579 < #endif
580 <        0x00000000, 0x00000000,
546 <        0xaafe0700, 0x00000000,
547 <        0x00000000, 0x00179822,
548 < #ifdef SERIAL_TRAMPOLINES
549 <        0x00010004, (uint32)serial_status_tvect,
550 < #else
551 <        0x00010004, (uint32)SerialStatus,
552 < #endif
553 <        0x00000000, 0x00000000,
554 <        0xaafe0700, 0x00000000,
555 <        0x00000000, 0x00179822,
556 < #ifdef SERIAL_TRAMPOLINES
557 <        0x00010004, (uint32)serial_close_tvect,
558 < #else
559 <        0x00010004, (uint32)SerialClose,
560 < #endif
561 <        0x00000000, 0x00000000,
552 > static void gen_aout_driver(uintptr addr)
553 > {
554 >        SetLongBase(addr);
555 >
556 >        // .AOut driver header
557 >        Long(0x4d000000); Long(0x00000000);
558 >        Long(0x00200040); Long(0x00600080);
559 >        Long(0x00a0052e); Long(0x414f7574);
560 >        Long(0x00000000); Long(0x00000000);
561 >        Long(0xaafe0700); Long(0x00000000);
562 >        Long(0x00000000); Long(0x00179822);
563 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_OPEN));
564 >        Long(0x00000000); Long(0x00000000);
565 >        Long(0xaafe0700); Long(0x00000000);
566 >        Long(0x00000000); Long(0x00179822);
567 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_PRIME_OUT));
568 >        Long(0x00000000); Long(0x00000000);
569 >        Long(0xaafe0700); Long(0x00000000);
570 >        Long(0x00000000); Long(0x00179822);
571 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CONTROL));
572 >        Long(0x00000000); Long(0x00000000);
573 >        Long(0xaafe0700); Long(0x00000000);
574 >        Long(0x00000000); Long(0x00179822);
575 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_STATUS));
576 >        Long(0x00000000); Long(0x00000000);
577 >        Long(0xaafe0700); Long(0x00000000);
578 >        Long(0x00000000); Long(0x00179822);
579 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CLOSE));
580 >        Long(0x00000000); Long(0x00000000);
581   };
582  
583 < static const uint32 bin_driver[] = {    // .BIn driver header
584 <        0x4d000000, 0x00000000,
585 <        0x00200040, 0x00600080,
586 <        0x00a0042e, 0x42496e00,
587 <        0x00000000, 0x00000000,
588 <        0xaafe0700, 0x00000000,
589 <        0x00000000, 0x00179822,
590 < #ifdef SERIAL_TRAMPOLINES
591 <        0x00010004, (uint32)serial_nothing_tvect,
592 < #else
593 <        0x00010004, (uint32)SerialNothing,
594 < #endif
595 <        0x00000000, 0x00000000,
596 <        0xaafe0700, 0x00000000,
597 <        0x00000000, 0x00179822,
598 < #ifdef SERIAL_TRAMPOLINES
599 <        0x00010004, (uint32)serial_prime_in_tvect,
600 < #else
601 <        0x00010004, (uint32)SerialPrimeIn,
602 < #endif
603 <        0x00000000, 0x00000000,
604 <        0xaafe0700, 0x00000000,
605 <        0x00000000, 0x00179822,
606 < #ifdef SERIAL_TRAMPOLINES
607 <        0x00010004, (uint32)serial_control_tvect,
608 < #else
609 <        0x00010004, (uint32)SerialControl,
610 < #endif
611 <        0x00000000, 0x00000000,
593 <        0xaafe0700, 0x00000000,
594 <        0x00000000, 0x00179822,
595 < #ifdef SERIAL_TRAMPOLINES
596 <        0x00010004, (uint32)serial_status_tvect,
597 < #else
598 <        0x00010004, (uint32)SerialStatus,
599 < #endif
600 <        0x00000000, 0x00000000,
601 <        0xaafe0700, 0x00000000,
602 <        0x00000000, 0x00179822,
603 < #ifdef SERIAL_TRAMPOLINES
604 <        0x00010004, (uint32)serial_nothing_tvect,
605 < #else
606 <        0x00010004, (uint32)SerialNothing,
607 < #endif
608 <        0x00000000, 0x00000000,
583 > static void gen_bin_driver(uintptr addr)
584 > {
585 >        SetLongBase(addr);
586 >
587 >        // .BIn driver header
588 >        Long(0x4d000000); Long(0x00000000);
589 >        Long(0x00200040); Long(0x00600080);
590 >        Long(0x00a0042e); Long(0x42496e00);
591 >        Long(0x00000000); Long(0x00000000);
592 >        Long(0xaafe0700); Long(0x00000000);
593 >        Long(0x00000000); Long(0x00179822);
594 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_NOTHING));
595 >        Long(0x00000000); Long(0x00000000);
596 >        Long(0xaafe0700); Long(0x00000000);
597 >        Long(0x00000000); Long(0x00179822);
598 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_PRIME_IN));
599 >        Long(0x00000000); Long(0x00000000);
600 >        Long(0xaafe0700); Long(0x00000000);
601 >        Long(0x00000000); Long(0x00179822);
602 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CONTROL));
603 >        Long(0x00000000); Long(0x00000000);
604 >        Long(0xaafe0700); Long(0x00000000);
605 >        Long(0x00000000); Long(0x00179822);
606 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_STATUS));
607 >        Long(0x00000000); Long(0x00000000);
608 >        Long(0xaafe0700); Long(0x00000000);
609 >        Long(0x00000000); Long(0x00179822);
610 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_NOTHING));
611 >        Long(0x00000000); Long(0x00000000);
612   };
613  
614 < static const uint32 bout_driver[] = {   // .BOut driver header
615 <        0x4d000000, 0x00000000,
616 <        0x00200040, 0x00600080,
617 <        0x00a0052e, 0x424f7574,
618 <        0x00000000, 0x00000000,
619 <        0xaafe0700, 0x00000000,
620 <        0x00000000, 0x00179822,
621 < #ifdef SERIAL_TRAMPOLINES
622 <        0x00010004, (uint32)serial_open_tvect,
623 < #else
624 <        0x00010004, (uint32)SerialOpen,
625 < #endif
626 <        0x00000000, 0x00000000,
627 <        0xaafe0700, 0x00000000,
628 <        0x00000000, 0x00179822,
629 < #ifdef SERIAL_TRAMPOLINES
630 <        0x00010004, (uint32)serial_prime_out_tvect,
631 < #else
632 <        0x00010004, (uint32)SerialPrimeOut,
633 < #endif
634 <        0x00000000, 0x00000000,
635 <        0xaafe0700, 0x00000000,
636 <        0x00000000, 0x00179822,
637 < #ifdef SERIAL_TRAMPOLINES
638 <        0x00010004, (uint32)serial_control_tvect,
639 < #else
640 <        0x00010004, (uint32)SerialControl,
641 < #endif
642 <        0x00000000, 0x00000000,
640 <        0xaafe0700, 0x00000000,
641 <        0x00000000, 0x00179822,
642 < #ifdef SERIAL_TRAMPOLINES
643 <        0x00010004, (uint32)serial_status_tvect,
644 < #else
645 <        0x00010004, (uint32)SerialStatus,
646 < #endif
647 <        0x00000000, 0x00000000,
648 <        0xaafe0700, 0x00000000,
649 <        0x00000000, 0x00179822,
650 < #ifdef SERIAL_TRAMPOLINES
651 <        0x00010004, (uint32)serial_close_tvect,
652 < #else
653 <        0x00010004, (uint32)SerialClose,
654 < #endif
655 <        0x00000000, 0x00000000,
614 > static void gen_bout_driver(uintptr addr)
615 > {
616 >        SetLongBase(addr);
617 >
618 >        // .BOut driver header
619 >        Long(0x4d000000); Long(0x00000000);
620 >        Long(0x00200040); Long(0x00600080);
621 >        Long(0x00a0052e); Long(0x424f7574);
622 >        Long(0x00000000); Long(0x00000000);
623 >        Long(0xaafe0700); Long(0x00000000);
624 >        Long(0x00000000); Long(0x00179822);
625 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_OPEN));
626 >        Long(0x00000000); Long(0x00000000);
627 >        Long(0xaafe0700); Long(0x00000000);
628 >        Long(0x00000000); Long(0x00179822);
629 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_PRIME_OUT));
630 >        Long(0x00000000); Long(0x00000000);
631 >        Long(0xaafe0700); Long(0x00000000);
632 >        Long(0x00000000); Long(0x00179822);
633 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CONTROL));
634 >        Long(0x00000000); Long(0x00000000);
635 >        Long(0xaafe0700); Long(0x00000000);
636 >        Long(0x00000000); Long(0x00179822);
637 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_STATUS));
638 >        Long(0x00000000); Long(0x00000000);
639 >        Long(0xaafe0700); Long(0x00000000);
640 >        Long(0x00000000); Long(0x00179822);
641 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CLOSE));
642 >        Long(0x00000000); Long(0x00000000);
643   };
644  
645   static const uint8 adbop_patch[] = {    // Call ADBOp() completion procedure
# Line 725 | Line 712 | bool PatchROM(void)
712          else
713                  return false;
714  
715 +        // Check that other ROM addresses point to really free regions
716 +        if (!check_rom_patch_space(CHECK_LOAD_PATCH_SPACE, 0x40))
717 +                return false;
718 +        if (!check_rom_patch_space(PUT_SCRAP_PATCH_SPACE, 0x40))
719 +                return false;
720 +        if (!check_rom_patch_space(GET_SCRAP_PATCH_SPACE, 0x40))
721 +                return false;
722 +        if (!check_rom_patch_space(ADDR_MAP_PATCH_SPACE - 10 * 4, 0x100))
723 +                return false;
724 +
725          // Apply patches
726          if (!patch_nanokernel_boot()) return false;
727          if (!patch_68k_emul()) return false;
# Line 757 | Line 754 | bool PatchROM(void)
754   static bool patch_nanokernel_boot(void)
755   {
756          uint32 *lp;
757 +        uint32 base, loc;
758  
759          // ROM boot structure patches
760          lp = (uint32 *)(ROM_BASE + 0x30d000);
# Line 769 | Line 767 | static bool patch_nanokernel_boot(void)
767          lp[0xfd8 >> 2] = htonl(ROM_BASE + 0x2a);                // 68k reset vector
768  
769          // Skip SR/BAT/SDR init
770 +        loc = 0x310000;
771          if (ROMType == ROMTYPE_GAZELLE || ROMType == ROMTYPE_GOSSAMER || ROMType == ROMTYPE_NEWWORLD) {
772 <                lp = (uint32 *)(ROM_BASE + 0x310000);
772 >                lp = (uint32 *)(ROM_BASE + loc);
773                  *lp++ = htonl(POWERPC_NOP);
774                  *lp = htonl(0x38000000);
775          }
776 <        static const uint32 sr_init_loc[] = {0x3101b0, 0x3101b0, 0x3101b0, 0x3101ec, 0x3101fc, 0x310200};
777 <        lp = (uint32 *)(ROM_BASE + 0x310008);
778 <        *lp = htonl(0x48000000 | (sr_init_loc[ROMType] - 8) & 0xffff);  // b            ROM_BASE+0x3101b0
779 <        lp = (uint32 *)(ROM_BASE + sr_init_loc[ROMType]);
776 >        static const uint8 sr_init_dat[] = {0x35, 0x4a, 0xff, 0xfc, 0x7d, 0x86, 0x50, 0x2e};
777 >        if ((base = find_rom_data(0x3101b0, 0x3105b0, sr_init_dat, sizeof(sr_init_dat))) == 0) return false;
778 >        D(bug("sr_init %08lx\n", base));
779 >        lp = (uint32 *)(ROM_BASE + loc + 8);
780 >        *lp = htonl(0x48000000 | ((base - loc - 8) & 0x3fffffc));       // b            ROM_BASE+0x3101b0
781 >        lp = (uint32 *)(ROM_BASE + base);
782          *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);            // lwz  r1,(pointer to Kernel Data)
783          *lp++ = htonl(0x3da0dead);              // lis  r13,0xdead      (start of kernel memory)
784          *lp++ = htonl(0x3dc00010);              // lis  r14,0x0010      (size of page table)
785          *lp = htonl(0x3de00010);                // lis  r15,0x0010      (size of kernel memory)
786  
787          // Don't read PVR
788 <        static const uint32 pvr_loc[] = {0x3103b0, 0x3103b4, 0x3103b4, 0x310400, 0x310430, 0x310438};
789 <        lp = (uint32 *)(ROM_BASE + pvr_loc[ROMType]);
788 >        static const uint8 pvr_read_dat[] = {0x7d, 0x9f, 0x42, 0xa6};
789 >        if ((base = find_rom_data(0x3103b0, 0x3108b0, pvr_read_dat, sizeof(pvr_read_dat))) == 0) return false;
790 >        D(bug("pvr_read %08lx\n", base));
791 >        lp = (uint32 *)(ROM_BASE + base);
792          *lp = htonl(0x81800000 + XLM_PVR);      // lwz  r12,(theoretical PVR)
793  
794          // Set CPU specific data (even if ROM doesn't have support for that CPU)
792        lp = (uint32 *)(ROM_BASE + pvr_loc[ROMType]);
795          if (ntohl(lp[6]) != 0x2c0c0001)
796                  return false;
797          uint32 ofs = ntohl(lp[7]) & 0xffff;
798          D(bug("ofs %08lx\n", ofs));
799          lp[8] = htonl((ntohl(lp[8]) & 0xffff) | 0x48000000);    // beq -> b
800 <        uint32 loc = (ntohl(lp[8]) & 0xffff) + (uint32)(lp+8) - ROM_BASE;
800 >        loc = (ntohl(lp[8]) & 0xffff) + (uint32)(lp+8) - ROM_BASE;
801          D(bug("loc %08lx\n", loc));
802          lp = (uint32 *)(ROM_BASE + ofs + 0x310000);
803          switch (PVR >> 16) {
# Line 845 | Line 847 | static bool patch_nanokernel_boot(void)
847                          lp[7] = htonl(0x00040004);      // Inst cache assoc/Data cache assoc
848                          lp[8] = htonl(0x00400002);      // TLB total size/TLB assoc
849                          break;
850 <                case 8:         // 750
850 >                case 8:         // 750, 750FX
851 >                case 0x7000:
852                          lp[0] = htonl(0x1000);          // Page size
853                          lp[1] = htonl(0x8000);          // Data cache size
854                          lp[2] = htonl(0x8000);          // Inst cache size
# Line 869 | Line 872 | static bool patch_nanokernel_boot(void)
872                          lp[8] = htonl(0x00800002);      // TLB total size/TLB assoc
873                          break;
874   //              case 11:        // X704?
875 <                case 12:        // ???
875 >                case 12:        // 7400, 7410, 7450, 7455, 7457
876 >                case 0x800c:
877 >                case 0x8000:
878 >                case 0x8001:
879 >                case 0x8002:
880                          lp[0] = htonl(0x1000);          // Page size
881                          lp[1] = htonl(0x8000);          // Data cache size
882                          lp[2] = htonl(0x8000);          // Inst cache size
# Line 910 | Line 917 | static bool patch_nanokernel_boot(void)
917          }
918  
919          // Don't set SPRG3, don't test MQ
920 <        lp = (uint32 *)(ROM_BASE + loc + 0x20);
921 <        *lp++ = htonl(POWERPC_NOP);
922 <        lp++;
923 <        *lp++ = htonl(POWERPC_NOP);
924 <        lp++;
925 <        *lp = htonl(POWERPC_NOP);
920 >        static const uint8 sprg3_mq_dat[] = {0x7d, 0x13, 0x43, 0xa6, 0x3d, 0x00, 0x00, 0x04, 0x7d, 0x00, 0x03, 0xa6, 0x39, 0x00, 0x00, 0x00, 0x7d, 0x00, 0x02, 0xa6};
921 >        if ((base = find_rom_data(loc + 0x20, loc + 0x60, sprg3_mq_dat, sizeof(sprg3_mq_dat))) == 0) return false;
922 >        D(bug("sprg3/mq %08lx\n", base));
923 >        lp = (uint32 *)(ROM_BASE + base);
924 >        lp[0] = htonl(POWERPC_NOP);
925 >        lp[2] = htonl(POWERPC_NOP);
926 >        lp[4] = htonl(POWERPC_NOP);
927  
928          // Don't read MSR
929 <        lp = (uint32 *)(ROM_BASE + loc + 0x40);
929 >        static const uint8 msr_dat[] = {0x7d, 0xc0, 0x00, 0xa6};
930 >        if ((base = find_rom_data(loc + 0x40, loc + 0x80, msr_dat, sizeof(msr_dat))) == 0) return false;
931 >        D(bug("msr %08lx\n", base));
932 >        lp = (uint32 *)(ROM_BASE + base);
933          *lp = htonl(0x39c00000);                // li   r14,0
934  
935          // Don't write to DEC
# Line 928 | Line 939 | static bool patch_nanokernel_boot(void)
939          D(bug("loc %08lx\n", loc));
940  
941          // Don't set SPRG3
942 <        lp = (uint32 *)(ROM_BASE + loc + 0x2c);
942 >        static const uint8 sprg3_dat[] = {0x39, 0x21, 0x03, 0x60, 0x7d, 0x33, 0x43, 0xa6, 0x39, 0x01, 0x04, 0x20};
943 >        if ((base = find_rom_data(0x310000, 0x314000, sprg3_dat, sizeof(sprg3_dat))) == 0) return false;
944 >        D(bug("sprg3 %08lx\n", base + 4));
945 >        lp = (uint32 *)(ROM_BASE + base + 4);
946          *lp = htonl(POWERPC_NOP);
947  
948          // Don't read PVR
949 <        static const uint32 pvr_ofs[] = {0x138, 0x138, 0x138, 0x140, 0x148, 0x148};
950 <        lp = (uint32 *)(ROM_BASE + loc + pvr_ofs[ROMType]);
949 >        static const uint8 pvr_read2_dat[] = {0x7e, 0xff, 0x42, 0xa6, 0x56, 0xf7, 0x84, 0x3e};
950 >        if ((base = find_rom_data(0x310000, 0x320000, pvr_read2_dat, sizeof(pvr_read2_dat))) == 0) return false;
951 >        D(bug("pvr_read2 %08lx\n", base));
952 >        lp = (uint32 *)(ROM_BASE + base);
953          *lp = htonl(0x82e00000 + XLM_PVR);              // lwz  r23,(theoretical PVR)
954 <        lp = (uint32 *)(ROM_BASE + loc + 0x170);
955 <        if (ntohl(*lp) == 0x7eff42a6)   // NewWorld or Gossamer ROM
954 >        if ((base = find_rom_data(base + 4, 0x320000, pvr_read2_dat, sizeof(pvr_read2_dat))) != 0) {
955 >                D(bug("pvr_read2 %08lx\n", base));
956 >                lp = (uint32 *)(ROM_BASE + base);
957                  *lp = htonl(0x82e00000 + XLM_PVR);      // lwz  r23,(theoretical PVR)
958 <        lp = (uint32 *)(ROM_BASE + 0x313134);
959 <        if (ntohl(*lp) == 0x7e5f42a6)
960 <                *lp = htonl(0x82400000 + XLM_PVR);      // lwz  r18,(theoretical PVR)
961 <        lp = (uint32 *)(ROM_BASE + 0x3131f4);
962 <        if (ntohl(*lp) == 0x7e5f42a6)   // NewWorld ROM
958 >        }
959 >        static const uint8 pvr_read3_dat[] = {0x7e, 0x5f, 0x42, 0xa6, 0x56, 0x52, 0x84, 0x3e};
960 >        if ((base = find_rom_data(0x310000, 0x320000, pvr_read3_dat, sizeof(pvr_read3_dat))) != 0) {
961 >                D(bug("pvr_read3 %08lx\n", base));
962 >                lp = (uint32 *)(ROM_BASE + base);
963                  *lp = htonl(0x82400000 + XLM_PVR);      // lwz  r18,(theoretical PVR)
964 <        lp = (uint32 *)(ROM_BASE + 0x314600);
965 <        if (ntohl(*lp) == 0x7d3f42a6)
964 >        }
965 >        static const uint8 pvr_read4_dat[] = {0x7d, 0x3f, 0x42, 0xa6, 0x55, 0x29, 0x84, 0x3e};
966 >        if ((base = find_rom_data(0x310000, 0x320000, pvr_read4_dat, sizeof(pvr_read4_dat))) != 0) {
967 >                D(bug("pvr_read4 %08lx\n", base));
968 >                lp = (uint32 *)(ROM_BASE + base);
969                  *lp = htonl(0x81200000 + XLM_PVR);      // lzw  r9,(theoritical PVR)
970 +        }
971  
972          // Don't read SDR1
973 <        static const uint32 sdr1_ofs[] = {0x174, 0x174, 0x174, 0x17c, 0x19c, 0x19c};
974 <        lp = (uint32 *)(ROM_BASE + loc + sdr1_ofs[ROMType]);
973 >        static const uint8 sdr1_read_dat[] = {0x7d, 0x19, 0x02, 0xa6, 0x55, 0x16, 0x81, 0xde};
974 >        if ((base = find_rom_data(0x310000, 0x320000, sdr1_read_dat, sizeof(sdr1_read_dat))) == 0) return false;
975 >        D(bug("sdr1_read %08lx\n", base));
976 >        lp = (uint32 *)(ROM_BASE + base);
977          *lp++ = htonl(0x3d00dead);              // lis  r8,0xdead               (pointer to page table)
978          *lp++ = htonl(0x3ec0001f);              // lis  r22,0x001f      (size of page table)
979          *lp = htonl(POWERPC_NOP);
980  
981 <        // Don't clear page table
982 <        static const uint32 pgtb_ofs[] = {0x198, 0x198, 0x198, 0x1a0, 0x1c0, 0x1c4};
983 <        lp = (uint32 *)(ROM_BASE + loc + pgtb_ofs[ROMType]);
981 >        // Don't clear page table, don't invalidate TLB
982 >        static const uint8 pgtb_clear_dat[] = {0x36, 0xd6, 0xff, 0xfc, 0x7e, 0xe8, 0xb1, 0x2e, 0x41, 0x81, 0xff, 0xf8};
983 >        if ((base = find_rom_data(0x310000, 0x320000, pgtb_clear_dat, sizeof(pgtb_clear_dat))) == 0) return false;
984 >        D(bug("pgtb_clear %08lx\n", base + 4));
985 >        lp = (uint32 *)(ROM_BASE + base + 4);
986          *lp = htonl(POWERPC_NOP);
987 <
988 <        // Don't invalidate TLB
964 <        static const uint32 tlb_ofs[] = {0x1a0, 0x1a0, 0x1a0, 0x1a8, 0x1c8, 0x1cc};
965 <        lp = (uint32 *)(ROM_BASE + loc + tlb_ofs[ROMType]);
987 >        D(bug("tblie %08lx\n", base + 12));
988 >        lp = (uint32 *)(ROM_BASE + base + 12);
989          *lp = htonl(POWERPC_NOP);
990  
991          // Don't create RAM descriptor table
992 <        static const uint32 desc_ofs[] = {0x350, 0x350, 0x350, 0x358, 0x378, 0x37c};
993 <        lp = (uint32 *)(ROM_BASE + loc + desc_ofs[ROMType]);
992 >        static const uint8 desc_create_dat[] = {0x97, 0xfd, 0x00, 0x04, 0x3b, 0xff, 0x10, 0x00, 0x4b, 0xff, 0xff, 0xdc};
993 >        if ((base = find_rom_data(0x310000, 0x320000, desc_create_dat, sizeof(desc_create_dat))) == 0) return false;
994 >        D(bug("desc_create %08lx\n", base))
995 >        lp = (uint32 *)(ROM_BASE + base);
996          *lp = htonl(POWERPC_NOP);
997  
998          // Don't load SRs and BATs
999 <        static const uint32 sr_ofs[] = {0x3d8, 0x3d8, 0x3d8, 0x3e0, 0x400, 0x404};
1000 <        lp = (uint32 *)(ROM_BASE + loc + sr_ofs[ROMType]);
999 >        static const uint8 sr_load[] = {0x7c, 0x00, 0x04, 0xac, 0x83, 0x9d, 0x00, 0x00, 0x93, 0x81, 0x05, 0xe8};
1000 >        if ((loc = find_rom_data(0x310000, 0x320000, sr_load, sizeof(sr_load))) == 0) return false;
1001 >        static const uint8 sr_load_caller[] = {0x3e, 0xd6, 0xff, 0xff, 0x41, 0x81, 0xff, 0xdc, 0xb2, 0xc8, 0x00, 0x02};
1002 >        if ((base = find_rom_data(0x310000, 0x320000, sr_load_caller, sizeof(sr_load_caller))) == 0) return false;
1003 >        if ((base = find_rom_powerpc_branch(base + 12, 0x320000, loc)) == 0) return false;
1004 >        D(bug("sr_load %08lx, called from %08lx\n", loc, base));
1005 >        lp = (uint32 *)(ROM_BASE + base);
1006          *lp = htonl(POWERPC_NOP);
1007  
1008          // Don't mess with SRs
1009 <        static const uint32 sr2_ofs[] = {0x312118, 0x312118, 0x312118, 0x312118, 0x312118, 0x3121b4};
1010 <        lp = (uint32 *)(ROM_BASE + sr2_ofs[ROMType]);
1009 >        static const uint8 sr_load2_dat[] = {0x83, 0xa1, 0x05, 0xe8, 0x57, 0x7c, 0x3e, 0x78, 0x7f, 0xbd, 0xe0, 0x2e};
1010 >        if ((base = find_rom_data(0x310000, 0x320000, sr_load2_dat, sizeof(sr_load2_dat))) == 0) return false;
1011 >        D(bug("sr_load2 %08lx\n", base));
1012 >        lp = (uint32 *)(ROM_BASE + base);
1013          *lp = htonl(POWERPC_BLR);
1014  
1015          // Don't check performance monitor
1016 <        static const uint32 pm_ofs[] = {0x313148, 0x313148, 0x313148, 0x313148, 0x313158, 0x313218};
1017 <        lp = (uint32 *)(ROM_BASE + pm_ofs[ROMType]);
1018 <        while (ntohl(*lp) != 0x7e58eba6) lp++;
1019 <        *lp++ = htonl(POWERPC_NOP);
1020 <        while (ntohl(*lp) != 0x7e78eaa6) lp++;
1021 <        *lp++ = htonl(POWERPC_NOP);
1022 <        while (ntohl(*lp) != 0x7e59eba6) lp++;
1023 <        *lp++ = htonl(POWERPC_NOP);
1024 <        while (ntohl(*lp) != 0x7e79eaa6) lp++;
1025 <        *lp++ = htonl(POWERPC_NOP);
1026 <        while (ntohl(*lp) != 0x7e5aeba6) lp++;
1027 <        *lp++ = htonl(POWERPC_NOP);
1028 <        while (ntohl(*lp) != 0x7e7aeaa6) lp++;
1029 <        *lp++ = htonl(POWERPC_NOP);
1030 <        while (ntohl(*lp) != 0x7e5beba6) lp++;
1031 <        *lp++ = htonl(POWERPC_NOP);
1032 <        while (ntohl(*lp) != 0x7e7beaa6) lp++;
1033 <        *lp++ = htonl(POWERPC_NOP);
1034 <        while (ntohl(*lp) != 0x7e5feba6) lp++;
1035 <        *lp++ = htonl(POWERPC_NOP);
1036 <        while (ntohl(*lp) != 0x7e7feaa6) lp++;
1037 <        *lp++ = htonl(POWERPC_NOP);
1038 <        while (ntohl(*lp) != 0x7e5ceba6) lp++;
1039 <        *lp++ = htonl(POWERPC_NOP);
1008 <        while (ntohl(*lp) != 0x7e7ceaa6) lp++;
1009 <        *lp++ = htonl(POWERPC_NOP);
1010 <        while (ntohl(*lp) != 0x7e5deba6) lp++;
1011 <        *lp++ = htonl(POWERPC_NOP);
1012 <        while (ntohl(*lp) != 0x7e7deaa6) lp++;
1013 <        *lp++ = htonl(POWERPC_NOP);
1014 <        while (ntohl(*lp) != 0x7e5eeba6) lp++;
1015 <        *lp++ = htonl(POWERPC_NOP);
1016 <        while (ntohl(*lp) != 0x7e7eeaa6) lp++;
1017 <        *lp++ = htonl(POWERPC_NOP);
1016 >        static const uint8 pm_check_dat[] = {0x7e, 0x58, 0xeb, 0xa6, 0x7e, 0x53, 0x90, 0xf8, 0x7e, 0x78, 0xea, 0xa6};
1017 >        if ((base = find_rom_data(0x310000, 0x320000, pm_check_dat, sizeof(pm_check_dat))) == 0) return false;
1018 >        D(bug("pm_check %08lx\n", base));
1019 >        lp = (uint32 *)(ROM_BASE + base);
1020 >        
1021 >        static const int spr_check_list[] = {
1022 >                952 /* mmcr0 */, 953 /* pmc1 */, 954 /* pmc2 */, 955 /* sia */,
1023 >                956 /* mmcr1 */, 957 /* pmc3 */, 958 /* pmc4 */, 959 /* sda */
1024 >        };
1025 >
1026 >        for (int i = 0; i < sizeof(spr_check_list)/sizeof(spr_check_list[0]); i++) {
1027 >                int spr = spr_check_list[i];
1028 >                uint32 mtspr = 0x7e4003a6 | ((spr & 0x1f) << 16) | ((spr & 0x3e0) << 6);
1029 >                uint32 mfspr = 0x7e6002a6 | ((spr & 0x1f) << 16) | ((spr & 0x3e0) << 6);
1030 >                for (int ofs = 0; ofs < 64; ofs++) {
1031 >                        if (ntohl(lp[ofs]) == mtspr) {
1032 >                                if (ntohl(lp[ofs + 2]) != mfspr)
1033 >                                        return false;
1034 >                                D(bug("  SPR%d %08lx\n", spr, base + 4*ofs));
1035 >                                lp[ofs] = htonl(POWERPC_NOP);
1036 >                                lp[ofs + 2] = htonl(POWERPC_NOP);
1037 >                        }
1038 >                }
1039 >        }
1040  
1041          // Jump to 68k emulator
1042 <        static const uint32 jump68k_ofs[] = {0x40c, 0x40c, 0x40c, 0x414, 0x434, 0x438};
1043 <        lp = (uint32 *)(ROM_BASE + loc + jump68k_ofs[ROMType]);
1042 >        static const uint8 jump68k_dat[] = {0x7d, 0x92, 0x43, 0xa6, 0x7d, 0x5a, 0x03, 0xa6, 0x7d, 0x7b, 0x03, 0xa6};
1043 >        if ((loc = find_rom_data(0x310000, 0x320000, jump68k_dat, sizeof(jump68k_dat))) == 0) return false;
1044 >        static const uint8 jump68k_caller_dat[] = {0x85, 0x13, 0x00, 0x08, 0x56, 0xbf, 0x50, 0x3e, 0x63, 0xff, 0x0c, 0x00};
1045 >        if ((base = find_rom_data(0x310000, 0x320000, jump68k_caller_dat, sizeof(jump68k_caller_dat))) == 0) return false;
1046 >        if ((base = find_rom_powerpc_branch(base + 12, 0x320000, loc)) == 0) return false;
1047 >        D(bug("jump68k %08lx, called from %08lx\n", loc, base));
1048 >        lp = (uint32 *)(ROM_BASE + base);
1049          *lp++ = htonl(0x80610634);              // lwz  r3,0x0634(r1)   (pointer to Emulator Data)
1050          *lp++ = htonl(0x8081119c);              // lwz  r4,0x119c(r1)   (pointer to opcode table)
1051          *lp++ = htonl(0x80011184);              // lwz  r0,0x1184(r1)   (pointer to emulator init routine)
# Line 1035 | Line 1062 | static bool patch_nanokernel_boot(void)
1062   static bool patch_68k_emul(void)
1063   {
1064          uint32 *lp;
1065 <        uint32 base;
1065 >        uint32 base, loc;
1066  
1067          // Overwrite twi instructions
1068 <        static const uint32 twi_loc[] = {0x36e680, 0x36e6c0, 0x36e6c0, 0x36e6c0, 0x36e740, 0x36e740};
1069 <        base = twi_loc[ROMType];
1068 >        static const uint8 twi_dat[] = {0x0f, 0xff, 0x00, 0x00, 0x0f, 0xff, 0x00, 0x01, 0x0f, 0xff, 0x00, 0x02};
1069 >        if ((base = find_rom_data(0x36e600, 0x36ea00, twi_dat, sizeof(twi_dat))) == 0) return false;
1070 >        D(bug("twi %08lx\n", base));
1071          lp = (uint32 *)(ROM_BASE + base);
1072          *lp++ = htonl(0x48000000 + 0x36f900 - base);            // b 0x36f900 (Emulator start)
1073          *lp++ = htonl(0x48000000 + 0x36fa00 - base - 4);        // b 0x36fa00 (Mixed mode)
# Line 1098 | Line 1126 | static bool patch_68k_emul(void)
1126          // Extra routine for 68k emulator start
1127          lp = (uint32 *)(ROM_BASE + 0x36f900);
1128          *lp++ = htonl(0x7c2903a6);                                      // mtctr        r1
1101 #if EMULATED_PPC
1102        *lp++ = POWERPC_NATIVE_OP(NATIVE_DISABLE_INTERRUPT);
1103 #else
1129          *lp++ = htonl(0x80200000 + XLM_IRQ_NEST);       // lwz          r1,XLM_IRQ_NEST
1130          *lp++ = htonl(0x38210001);                                      // addi         r1,r1,1
1131          *lp++ = htonl(0x90200000 + XLM_IRQ_NEST);       // stw          r1,XLM_IRQ_NEST
1107 #endif
1132          *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz              r1,XLM_KERNEL_DATA
1133          *lp++ = htonl(0x90c10018);                                      // stw          r6,0x18(r1)
1134          *lp++ = htonl(0x7cc902a6);                                      // mfctr        r6
# Line 1132 | Line 1156 | static bool patch_68k_emul(void)
1156          // Extra routine for Mixed Mode
1157          lp = (uint32 *)(ROM_BASE + 0x36fa00);
1158          *lp++ = htonl(0x7c2903a6);                                      // mtctr        r1
1135 #if EMULATED_PPC
1136        *lp++ = POWERPC_NATIVE_OP(NATIVE_DISABLE_INTERRUPT);
1137 #else
1159          *lp++ = htonl(0x80200000 + XLM_IRQ_NEST);       // lwz          r1,XLM_IRQ_NEST
1160          *lp++ = htonl(0x38210001);                                      // addi         r1,r1,1
1161          *lp++ = htonl(0x90200000 + XLM_IRQ_NEST);       // stw          r1,XLM_IRQ_NEST
1141 #endif
1162          *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz              r1,XLM_KERNEL_DATA
1163          *lp++ = htonl(0x90c10018);                                      // stw          r6,0x18(r1)
1164          *lp++ = htonl(0x7cc902a6);                                      // mfctr        r6
# Line 1166 | Line 1186 | static bool patch_68k_emul(void)
1186          // Extra routine for Reset/FC1E opcode
1187          lp = (uint32 *)(ROM_BASE + 0x36fb00);
1188          *lp++ = htonl(0x7c2903a6);                                      // mtctr        r1
1169 #if EMULATED_PPC
1170        *lp++ = POWERPC_NATIVE_OP(NATIVE_DISABLE_INTERRUPT);
1171 #else
1189          *lp++ = htonl(0x80200000 + XLM_IRQ_NEST);       // lwz          r1,XLM_IRQ_NEST
1190          *lp++ = htonl(0x38210001);                                      // addi         r1,r1,1
1191          *lp++ = htonl(0x90200000 + XLM_IRQ_NEST);       // stw          r1,XLM_IRQ_NEST
1175 #endif
1192          *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz              r1,XLM_KERNEL_DATA
1193          *lp++ = htonl(0x90c10018);                                      // stw          r6,0x18(r1)
1194          *lp++ = htonl(0x7cc902a6);                                      // mfctr        r6
# Line 1200 | Line 1216 | static bool patch_68k_emul(void)
1216          // Extra routine for FE0A opcode (QuickDraw 3D needs this)
1217          lp = (uint32 *)(ROM_BASE + 0x36fc00);
1218          *lp++ = htonl(0x7c2903a6);                                      // mtctr        r1
1203 #if EMULATED_PPC
1204        *lp++ = POWERPC_NATIVE_OP(NATIVE_DISABLE_INTERRUPT);
1205 #else
1219          *lp++ = htonl(0x80200000 + XLM_IRQ_NEST);       // lwz          r1,XLM_IRQ_NEST
1220          *lp++ = htonl(0x38210001);                                      // addi         r1,r1,1
1221          *lp++ = htonl(0x90200000 + XLM_IRQ_NEST);       // stw          r1,XLM_IRQ_NEST
1209 #endif
1222          *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz              r1,XLM_KERNEL_DATA
1223          *lp++ = htonl(0x90c10018);                                      // stw          r6,0x18(r1)
1224          *lp++ = htonl(0x7cc902a6);                                      // mfctr        r6
# Line 1242 | Line 1254 | static bool patch_68k_emul(void)
1254          return false;
1255   dr_found:
1256          lp++;
1257 <        *lp = htonl(0x48000000 + 0xf000 - (((uint32)lp - ROM_BASE) & 0xffff));          // b    DR_CACHE_BASE+0x1f000
1258 <        lp = (uint32 *)(ROM_BASE + 0x37f000);
1259 <        *lp++ = htonl(0x3c000000 + ((ROM_BASE + 0x46d0a4) >> 16));              // lis  r0,xxx
1260 <        *lp++ = htonl(0x60000000 + ((ROM_BASE + 0x46d0a4) & 0xffff));   // ori  r0,r0,xxx
1261 <        *lp++ = htonl(0x7c0903a6);                                                                              // mtctr        r0
1262 <        *lp = htonl(POWERPC_BCTR);                                                                              // bctr
1257 >        loc = (uint32)lp - ROM_BASE;
1258 >        if ((base = powerpc_branch_target(ROM_BASE + loc)) == 0) base = ROM_BASE + loc;
1259 >        static const uint8 dr_ret_dat[] = {0x80, 0xbf, 0x08, 0x14, 0x53, 0x19, 0x4d, 0xac, 0x7c, 0xa8, 0x03, 0xa6};
1260 >        if ((base = find_rom_data(base - ROM_BASE, 0x380000, dr_ret_dat, sizeof(dr_ret_dat))) == 0) return false;
1261 >        D(bug("dr_ret %08lx\n", base));
1262 >        if (base != loc) {
1263 >                // OldWorld ROMs contain an absolute branch
1264 >                D(bug(" patching absolute branch at %08x\n", (uint32)lp - ROM_BASE));
1265 >                *lp = htonl(0x48000000 + 0xf000 - (((uint32)lp - ROM_BASE) & 0xffff));          // b    DR_CACHE_BASE+0x1f000
1266 >                lp = (uint32 *)(ROM_BASE + 0x37f000);
1267 >                *lp++ = htonl(0x3c000000 + ((ROM_BASE + base) >> 16));                  // lis  r0,xxx
1268 >                *lp++ = htonl(0x60000000 + ((ROM_BASE + base) & 0xffff));               // ori  r0,r0,xxx
1269 >                *lp++ = htonl(0x7c0803a6);                                                                              // mtlr r0
1270 >                *lp = htonl(POWERPC_BLR);                                                                               // blr
1271 >        }
1272          return true;
1273   }
1274  
# Line 1259 | Line 1280 | dr_found:
1280   static bool patch_nanokernel(void)
1281   {
1282          uint32 *lp;
1283 +        uint32 base, loc;
1284  
1285          // Patch Mixed Mode trap
1286 <        lp = (uint32 *)(ROM_BASE + 0x313c90);   // Don't translate virtual->physical
1287 <        while (ntohl(*lp) != 0x3ba10320) lp++;
1288 <        lp++;
1289 <        *lp++ = htonl(0x7f7fdb78);                                      // mr           r31,r27
1290 <        lp++;
1291 <        *lp = htonl(POWERPC_NOP);
1292 <
1293 <        lp = (uint32 *)(ROM_BASE + 0x313c3c);   // Don't activate PPC exception table
1294 <        while (ntohl(*lp) != 0x39010420) lp++;
1286 >        static const uint8 virt2phys_dat[] = {0x7d, 0x1b, 0x43, 0x78, 0x3b, 0xa1, 0x03, 0x20};
1287 >        if ((base = find_rom_data(0x313000, 0x314000, virt2phys_dat, sizeof(virt2phys_dat))) == 0) return false;
1288 >        D(bug("virt2phys %08lx\n", base + 8));
1289 >        lp = (uint32 *)(ROM_BASE + base + 8);   // Don't translate virtual->physical
1290 >        lp[0] = htonl(0x7f7fdb78);                                      // mr           r31,r27
1291 >        lp[2] = htonl(POWERPC_NOP);
1292 >
1293 >        static const uint8 ppc_excp_tbl_dat[] = {0x39, 0x01, 0x04, 0x20, 0x7d, 0x13, 0x43, 0xa6};
1294 >        if ((base = find_rom_data(0x313000, 0x314000, ppc_excp_tbl_dat, sizeof(ppc_excp_tbl_dat))) == 0) return false;
1295 >        D(bug("ppc_excp_tbl %08lx\n", base));
1296 >        lp = (uint32 *)(ROM_BASE + base);               // Don't activate PPC exception table
1297          *lp++ = htonl(0x39000000 + MODE_NATIVE);        // li   r8,MODE_NATIVE
1298 <        *lp = htonl(0x91000000 + XLM_RUN_MODE); // stw  r8,XLM_RUN_MODE
1298 >        *lp = htonl(0x91000000 + XLM_RUN_MODE);         // stw  r8,XLM_RUN_MODE
1299  
1300 <        lp = (uint32 *)(ROM_BASE + 0x312e88);   // Don't modify MSR to turn on FPU
1301 <        while (ntohl(*lp) != 0x556b04e2) lp++;
1302 <        lp -= 4;
1300 >        static const uint8 save_fpu_dat[] = {0x7d, 0x00, 0x00, 0xa6, 0x61, 0x08, 0x20, 0x00, 0x7d, 0x00, 0x01, 0x24};
1301 >        if ((base = find_rom_data(0x310000, 0x314000, save_fpu_dat, sizeof(save_fpu_dat))) == 0) return false;
1302 >        D(bug("save_fpu %08lx\n", base));
1303 >        lp = (uint32 *)(ROM_BASE + base);               // Don't modify MSR to turn on FPU
1304 >        if (ntohl(lp[4]) != 0x556b04e2) return false;
1305 >        loc = ROM_BASE + base;
1306 > #if 1
1307 >        // FIXME: is that really intended?
1308          *lp++ = htonl(POWERPC_NOP);
1309          lp++;
1310          *lp++ = htonl(POWERPC_NOP);
1311          lp++;
1312          *lp = htonl(POWERPC_NOP);
1313 + #else
1314 +        lp[0] = htonl(POWERPC_NOP);
1315 +        lp[1] = htonl(POWERPC_NOP);
1316 +        lp[2] = htonl(POWERPC_NOP);
1317 +        lp[3] = htonl(POWERPC_NOP);
1318 + #endif
1319  
1320 <        lp = (uint32 *)(ROM_BASE + 0x312b3c);   // Always save FPU state
1321 <        while (ntohl(*lp) != 0x81010668) lp++;
1322 <        lp--;
1320 >        static const uint8 save_fpu_caller_dat[] = {0x93, 0xa6, 0x01, 0xec, 0x93, 0xc6, 0x01, 0xf4, 0x93, 0xe6, 0x01, 0xfc, 0x40};
1321 >        if ((base = find_rom_data(0x310000, 0x314000, save_fpu_caller_dat, sizeof(save_fpu_caller_dat))) == 0) return false;
1322 >        D(bug("save_fpu_caller %08lx\n", base + 12));
1323 >        if (powerpc_branch_target(ROM_BASE + base + 12) != loc) return false;
1324 >        lp = (uint32 *)(ROM_BASE + base + 12);  // Always save FPU state
1325          *lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff));        // bl   0x00312e88
1326  
1327 <        lp = (uint32 *)(ROM_BASE + 0x312b44);   // Don't read DEC
1328 <        while (ntohl(*lp) != 0x7ff602a6) lp++;
1329 <        *lp = htonl(0x3be00000);                                        // li   r31,0
1330 <
1331 <        lp = (uint32 *)(ROM_BASE + 0x312b50);   // Don't write DEC
1295 <        while (ntohl(*lp) != 0x7d1603a6) lp++;
1327 >        static const uint8 mdec_dat[] = {0x7f, 0xf6, 0x02, 0xa6, 0x2c, 0x08, 0x00, 0x00, 0x93, 0xe1, 0x06, 0x68, 0x7d, 0x16, 0x03, 0xa6};
1328 >        if ((base = find_rom_data(0x310000, 0x314000, mdec_dat, sizeof(mdec_dat))) == 0) return false;
1329 >        D(bug("mdec %08lx\n", base));
1330 >        lp = (uint32 *)(ROM_BASE + base);               // Don't modify DEC
1331 >        lp[0] = htonl(0x3be00000);                                      // li   r31,0
1332   #if 1
1333 <        *lp++ = htonl(POWERPC_NOP);
1334 <        *lp = htonl(POWERPC_NOP);
1333 >        lp[3] = htonl(POWERPC_NOP);
1334 >        lp[4] = htonl(POWERPC_NOP);
1335   #else
1336 <        *lp++ = htonl(0x39000040);                                      // li   r8,0x40
1337 <        *lp = htonl(0x990600e4);                                        // stb  r8,0xe4(r6)
1336 >        lp[3] = htonl(0x39000040);                                      // li   r8,0x40
1337 >        lp[4] = htonl(0x990600e4);                                      // stb  r8,0xe4(r6)
1338   #endif
1339  
1340 <        lp = (uint32 *)(ROM_BASE + 0x312b9c);   // Always restore FPU state
1341 <        while (ntohl(*lp) != 0x7c00092d) lp++;
1342 <        lp--;
1340 >        static const uint8 restore_fpu_caller_dat[] = {0x81, 0x06, 0x00, 0xf4, 0x81, 0x46, 0x00, 0xfc, 0x7d, 0x09, 0x03, 0xa6, 0x40};
1341 >        if ((base = find_rom_data(0x310000, 0x314000, restore_fpu_caller_dat, sizeof(restore_fpu_caller_dat))) == 0) return false;
1342 >        D(bug("restore_fpu_caller %08lx\n", base + 12));
1343 >        lp = (uint32 *)(ROM_BASE + base + 12);  // Always restore FPU state
1344          *lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff));        // bl   0x00312ddc
1345  
1346 <        lp = (uint32 *)(ROM_BASE + 0x312a68);   // Don't activate 68k exception table
1347 <        while (ntohl(*lp) != 0x39010360) lp++;
1346 >        static const uint8 m68k_excp_tbl_dat[] = {0x81, 0x21, 0x06, 0x58, 0x39, 0x01, 0x03, 0x60, 0x7d, 0x13, 0x43, 0xa6};
1347 >        if ((base = find_rom_data(0x310000, 0x314000, m68k_excp_tbl_dat, sizeof(m68k_excp_tbl_dat))) == 0) return false;
1348 >        D(bug("m68k_excp %08lx\n", base + 4));
1349 >        lp = (uint32 *)(ROM_BASE + base + 4);   // Don't activate 68k exception table
1350          *lp++ = htonl(0x39000000 + MODE_68K);           // li   r8,MODE_68K
1351          *lp = htonl(0x91000000 + XLM_RUN_MODE);         // stw  r8,XLM_RUN_MODE
1352  
1353          // Patch 68k emulator trap routine
1354 <        lp = (uint32 *)(ROM_BASE + 0x312994);   // Always restore FPU state
1355 <        while (ntohl(*lp) != 0x39260040) lp++;
1356 <        lp--;
1354 >        static const uint8 restore_fpu_caller2_dat[] = {0x81, 0x86, 0x00, 0x8c, 0x80, 0x66, 0x00, 0x94, 0x80, 0x86, 0x00, 0x9c, 0x40};
1355 >        if ((base = find_rom_data(0x310000, 0x314000, restore_fpu_caller2_dat, sizeof(restore_fpu_caller2_dat))) == 0) return false;
1356 >        D(bug("restore_fpu_caller2 %08lx\n", base + 12));
1357 >        loc = powerpc_branch_target(ROM_BASE + base + 12) - ROM_BASE;
1358 >        lp = (uint32 *)(ROM_BASE + base + 12);  // Always restore FPU state
1359          *lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff));        // bl   0x00312dd4
1360  
1361 <        lp = (uint32 *)(ROM_BASE + 0x312dd8);   // Don't modify MSR to turn on FPU
1362 <        while (ntohl(*lp) != 0x810600e4) lp++;
1363 <        lp--;
1361 >        static const uint8 restore_fpu_dat[] = {0x55, 0x68, 0x04, 0xa5, 0x4c, 0x82, 0x00, 0x20, 0x81, 0x06, 0x00, 0xe4};
1362 >        if ((base = find_rom_data(0x310000, 0x314000, restore_fpu_dat, sizeof(restore_fpu_dat))) == 0) return false;
1363 >        D(bug("restore_fpu %08lx\n", base));
1364 >        if (base != loc) return false;
1365 >        lp = (uint32 *)(ROM_BASE + base + 4);   // Don't modify MSR to turn on FPU
1366          *lp++ = htonl(POWERPC_NOP);
1367          lp += 2;
1368          *lp++ = htonl(POWERPC_NOP);
# Line 1329 | Line 1372 | static bool patch_nanokernel(void)
1372          *lp = htonl(POWERPC_NOP);
1373  
1374          // Patch trap return routine
1375 <        lp = (uint32 *)(ROM_BASE + 0x312c20);
1376 <        while (ntohl(*lp) != 0x7d5a03a6) lp++;
1375 >        static const uint8 trap_return_dat[] = {0x80, 0xc1, 0x00, 0x18, 0x80, 0x21, 0x00, 0x04, 0x4c, 0x00, 0x00, 0x64};
1376 >        if ((base = find_rom_data(0x312000, 0x320000, trap_return_dat, sizeof(trap_return_dat))) == 0) return false;
1377 >        D(bug("trap_return %08lx\n", base + 8));
1378 >        lp = (uint32 *)(ROM_BASE + base + 8);   // Replace rfi
1379 >        *lp = htonl(POWERPC_BCTR);
1380 >
1381 >        while (ntohl(*lp) != 0x7d5a03a6) lp--;
1382          *lp++ = htonl(0x7d4903a6);                                      // mtctr        r10
1383          *lp++ = htonl(0x7daff120);                                      // mtcr r13
1384 <        *lp = htonl(0x48000000 + 0x8000 - (((uint32)lp - ROM_BASE) & 0xffff));  // b            ROM_BASE+0x318000
1385 <        uint32 xlp = ((uint32)(lp+1) - ROM_BASE) & 0xffff;
1338 <
1339 <        lp = (uint32 *)(ROM_BASE + 0x312c50);   // Replace rfi
1340 <        while (ntohl(*lp) != 0x4c000064) lp++;
1341 <        *lp = htonl(POWERPC_BCTR);
1384 >        *lp = htonl(0x48000000 + ((0x318000 - ((uint32)lp - ROM_BASE)) & 0x03fffffc));  // b            ROM_BASE+0x318000
1385 >        uint32 npc = (uint32)(lp + 1) - ROM_BASE;
1386  
1387          lp = (uint32 *)(ROM_BASE + 0x318000);
1344 #if EMULATED_PPC
1345        *lp++ = POWERPC_NATIVE_OP(NATIVE_ENABLE_INTERRUPT);
1346        *lp = htonl(0x48000000 + ((xlp - 0x8004) & 0x03fffffc));        // b            ROM_BASE+0x312c2c
1347 #else
1388          *lp++ = htonl(0x81400000 + XLM_IRQ_NEST);       // lwz  r10,XLM_IRQ_NEST
1389          *lp++ = htonl(0x394affff);                                      // subi r10,r10,1
1390          *lp++ = htonl(0x91400000 + XLM_IRQ_NEST);       // stw  r10,XLM_IRQ_NEST
1391 <        *lp = htonl(0x48000000 + ((xlp - 0x800c) & 0x03fffffc));        // b            ROM_BASE+0x312c2c
1352 < #endif
1391 >        *lp = htonl(0x48000000 + ((npc - 0x31800c) & 0x03fffffc));      // b            ROM_BASE+0x312c2c
1392  
1393   /*
1394          // Disable FE0A/FE06 opcodes
# Line 1370 | Line 1409 | static bool patch_68k(void)
1409          uint32 *lp;
1410          uint16 *wp;
1411          uint8 *bp;
1412 <        uint32 base;
1412 >        uint32 base, loc;
1413  
1414          // Remove 68k RESET instruction
1415          static const uint8 reset_dat[] = {0x4e, 0x70};
# Line 1611 | Line 1650 | static bool patch_68k(void)
1650          *wp = htons(M68K_NOP);
1651  
1652          // Don't initialize SCC (via 0x1ac)
1653 <        static const uint8 scc_init_dat[] = {0x48, 0xe7, 0x38, 0xfe};
1654 <        if ((base = find_rom_data(0x190, 0x1f0, scc_init_dat, sizeof(scc_init_dat))) == 0) return false;
1653 >        static const uint8 scc_init_caller_dat[] = {0x21, 0xce, 0x01, 0x08, 0x22, 0x78, 0x0d, 0xd8};
1654 >        if ((base = find_rom_data(0x180, 0x1f0, scc_init_caller_dat, sizeof(scc_init_caller_dat))) == 0) return false;
1655 >        D(bug("scc_init_caller %08lx\n", base + 12));
1656 >        wp = (uint16 *)(ROM_BASE + base + 12);
1657 >        loc = ntohs(wp[1]) + ((uintptr)wp - ROM_BASE) + 2;
1658 >        static const uint8 scc_init_dat[] = {0x20, 0x78, 0x01, 0xdc, 0x22, 0x78, 0x01, 0xd8};
1659 >        if ((base = find_rom_data(loc, loc + 0x80, scc_init_dat, sizeof(scc_init_dat))) == 0) return false;
1660          D(bug("scc_init %08lx\n", base));
1661 <        wp = (uint16 *)(ROM_BASE + base - 2);
1618 <        wp = (uint16 *)(ROM_BASE + ntohs(*wp) + base - 2);
1661 >        wp = (uint16 *)(ROM_BASE + base);
1662          *wp++ = htons(M68K_EMUL_OP_RESET);
1663          *wp = htons(M68K_RTS);
1664  
# Line 1707 | Line 1750 | static bool patch_68k(void)
1750          *wp++ = htons(0x1000);
1751          *wp++ = htons(0x001e);
1752          *wp++ = htons(0x157c);                  // move.b       #PVR,$1d(a2)
1753 <        *wp++ = htons(PVR >> 16);
1753 >        *wp++ = htons(((PVR & 0x80000000) ? 0x10 : 0) | ((PVR >> 16) & 0xff));
1754          *wp++ = htons(0x001d);
1755          *wp++ = htons(0x263c);                  // move.l       #RAMSize,d3
1756          *wp++ = htons(RAMSize >> 16);
# Line 1842 | Line 1885 | static bool patch_68k(void)
1885          *wp = htons(M68K_RTS);
1886  
1887          // Don't install Time Manager task for 60Hz interrupt (Enable60HzInts, via 0x2b8)
1888 <        if (ROMType == ROMTYPE_NEWWORLD) {
1888 >        if (ROMType == ROMTYPE_NEWWORLD || ROMType == ROMTYPE_GOSSAMER) {
1889                  static const uint8 tm_task_dat[] = {0x30, 0x3c, 0x4e, 0x2b, 0xa9, 0xc9};
1890 <                if ((base = find_rom_data(0x2e0, 0x320, tm_task_dat, sizeof(tm_task_dat))) == 0) return false;
1890 >                if ((base = find_rom_data(0x2a0, 0x320, tm_task_dat, sizeof(tm_task_dat))) == 0) return false;
1891                  D(bug("tm_task %08lx\n", base));
1892 <                wp = (uint16 *)(ROM_BASE + base + 28); // FIXME: this is not right for all nw ROMs
1892 >                wp = (uint16 *)(ROM_BASE + base + 28);
1893                  *wp++ = htons(M68K_NOP);
1894                  *wp++ = htons(M68K_NOP);
1895                  *wp++ = htons(M68K_NOP);
1896                  *wp++ = htons(M68K_NOP);
1897                  *wp++ = htons(M68K_NOP);
1898                  *wp = htons(M68K_NOP);
1856        } else if (ROMType == ROMTYPE_GOSSAMER) {
1857                static const uint8 tm_task_dat[] = {0x30, 0x3c, 0x4e, 0x2b, 0xa9, 0xc9};
1858                if ((base = find_rom_data(0x2a0, 0x2e0, tm_task_dat, sizeof(tm_task_dat))) == 0) return false;
1859                D(bug("tm_task %08lx\n", base));
1860                wp = (uint16 *)(ROM_BASE + base + 22);
1861                *wp++ = htons(M68K_NOP);
1862                *wp++ = htons(M68K_NOP);
1863                *wp++ = htons(M68K_NOP);
1899          } else {
1900                  static const uint8 tm_task_dat[] = {0x20, 0x3c, 0x73, 0x79, 0x73, 0x61};
1901                  if ((base = find_rom_data(0x280, 0x300, tm_task_dat, sizeof(tm_task_dat))) == 0) return false;
# Line 1907 | Line 1942 | static bool patch_68k(void)
1942                  *lp = htonl(0x38600000);                // li   r3,0
1943          }
1944  
1945 +        // FIXME: Fake reading from [HpChk]+4 (the callchain reports some function from DriverServicesLib)
1946 +        if (1) {
1947 +                uint32 hpchk_offset = find_rom_resource(FOURCC('n','l','i','b'), 10);
1948 +                static const uint8 hpchk_dat[] = {0x80, 0x80, 0x03, 0x16, 0x94, 0x21, 0xff, 0xb0, 0x83, 0xc4, 0x00, 0x04};
1949 +                if ((base = find_rom_data(hpchk_offset, hpchk_offset + 0x3000, hpchk_dat, sizeof(hpchk_dat))) == 0) return false;
1950 +                D(bug("hpchk %08lx\n", base));
1951 +                lp = (uint32 *)(ROM_BASE + base);
1952 +                *lp = htonl(0x80800000 + XLM_ZERO_PAGE);                // lwz  r4,(zero page)
1953 +        }
1954 +
1955          // Patch Name Registry
1956          static const uint8 name_reg_dat[] = {0x70, 0xff, 0xab, 0xeb};
1957          if ((base = find_rom_data(0x300, 0x380, name_reg_dat, sizeof(name_reg_dat))) == 0) return false;
# Line 2030 | Line 2075 | static bool patch_68k(void)
2075          memcpy((void *)(ROM_BASE + sony_offset + 0x200), cdrom_driver, sizeof(cdrom_driver));
2076  
2077          // Install serial drivers
2078 <        memcpy_powerpc_code((void *)(ROM_BASE + sony_offset + 0x300), ain_driver, sizeof(ain_driver));
2079 <        memcpy_powerpc_code((void *)(ROM_BASE + sony_offset + 0x400), aout_driver, sizeof(aout_driver));
2080 <        memcpy_powerpc_code((void *)(ROM_BASE + sony_offset + 0x500), bin_driver, sizeof(bin_driver));
2081 <        memcpy_powerpc_code((void *)(ROM_BASE + sony_offset + 0x600), bout_driver, sizeof(bout_driver));
2078 >        gen_ain_driver( ROM_BASE + sony_offset + 0x300);
2079 >        gen_aout_driver(ROM_BASE + sony_offset + 0x400);
2080 >        gen_bin_driver( ROM_BASE + sony_offset + 0x500);
2081 >        gen_bout_driver(ROM_BASE + sony_offset + 0x600);
2082  
2083          // Copy icons to ROM
2084          SonyDiskIconAddr = ROM_BASE + sony_offset + 0x800;
# Line 2175 | Line 2220 | static bool patch_68k(void)
2220          lp = (uint32 *)(ROM_BASE + ntohl(*lp));
2221          lp[0xa9fd & 0x3ff] = htonl(GET_SCRAP_PATCH_SPACE);
2222  
2178 #if __BEOS__
2223          // Patch SynchIdleTime()
2224          if (PrefsFindBool("idlewait")) {
2225                  wp = (uint16 *)(ROM_BASE + find_rom_trap(0xabf7) + 4);  // SynchIdleTime()
2226                  D(bug("SynchIdleTime at %08lx\n", wp));
2227 <                if (ntohs(*wp) == 0x2078) {
2227 >                if (ntohs(*wp) == 0x2078) {                                                             // movea.l      ExpandMem,a0
2228                          *wp++ = htons(M68K_EMUL_OP_IDLE_TIME);
2229                          *wp = htons(M68K_NOP);
2230 <                } else {
2230 >                }
2231 >                else if (ntohs(*wp) == 0x70fe)                                                  // moveq        #-2,d0
2232 >                        *wp++ = htons(M68K_EMUL_OP_IDLE_TIME_2);
2233 >                else {
2234                          D(bug("SynchIdleTime patch not installed\n"));
2235                  }
2236          }
2190 #endif
2237  
2238          // Construct list of all sifters used by sound components in ROM
2239          D(bug("Searching for sound components with type sdev in ROM\n"));
# Line 2235 | Line 2281 | void InstallDrivers(void)
2281   {
2282          D(bug("Installing drivers...\n"));
2283          M68kRegisters r;
2284 <        uint8 pb[SIZEOF_IOParam];
2284 >        SheepArray<SIZEOF_IOParam> pb_var;
2285 >        const uintptr pb = pb_var.addr();
2286  
2287          // Install floppy driver
2288 <        if (ROMType == ROMTYPE_NEWWORLD) {
2288 >        if (ROMType == ROMTYPE_NEWWORLD || ROMType == ROMTYPE_GOSSAMER) {
2289  
2290 <                // Force installation of floppy driver with NewWorld ROMs
2290 >                // Force installation of floppy driver with NewWorld and Gossamer ROMs
2291                  r.a[0] = ROM_BASE + sony_offset;
2292                  r.d[0] = (uint32)SonyRefNum;
2293                  Execute68kTrap(0xa43d, &r);             // DrvrInstallRsrvMem()
# Line 2251 | Line 2298 | void InstallDrivers(void)
2298                  WriteMacInt16(dce + dCtlFlags, SonyDriverFlags);
2299          }
2300  
2301 < #if DISABLE_SCSI && 0
2301 > #if DISABLE_SCSI && HAVE_SIGSEGV_SKIP_INSTRUCTION
2302          // Fake SCSIGlobals
2303 <        static const uint8 fake_scsi_globals[32] = {0,};
2257 <        WriteMacInt32(0xc0c, (uint32)fake_scsi_globals);
2303 >        WriteMacInt32(0xc0c, SheepMem::ZeroPage());
2304   #endif
2305  
2306          // Open .Sony driver
2307 <        WriteMacInt8((uint32)pb + ioPermssn, 0);
2308 <        WriteMacInt32((uint32)pb + ioNamePtr, (uint32)"\005.Sony");
2309 <        r.a[0] = (uint32)pb;
2307 >        SheepString sony_str("\005.Sony");
2308 >        WriteMacInt8(pb + ioPermssn, 0);
2309 >        WriteMacInt32(pb + ioNamePtr, sony_str.addr());
2310 >        r.a[0] = pb;
2311          Execute68kTrap(0xa000, &r);             // Open()
2312  
2313          // Install disk driver
# Line 2274 | Line 2321 | void InstallDrivers(void)
2321          WriteMacInt16(dce + dCtlFlags, DiskDriverFlags);
2322  
2323          // Open disk driver
2324 <        WriteMacInt32((uint32)pb + ioNamePtr, (uint32)"\005.Disk");
2325 <        r.a[0] = (uint32)pb;
2324 >        SheepString disk_str("\005.Disk");
2325 >        WriteMacInt32(pb + ioNamePtr, disk_str.addr());
2326 >        r.a[0] = pb;
2327          Execute68kTrap(0xa000, &r);             // Open()
2328  
2329          // Install CD-ROM driver unless nocdrom option given
# Line 2292 | Line 2340 | void InstallDrivers(void)
2340                  WriteMacInt16(dce + dCtlFlags, CDROMDriverFlags);
2341  
2342                  // Open CD-ROM driver
2343 <                WriteMacInt32((uint32)pb + ioNamePtr, (uint32)"\010.AppleCD");
2344 <                r.a[0] = (uint32)pb;
2343 >                SheepString apple_cd("\010.AppleCD");
2344 >                WriteMacInt32(pb + ioNamePtr, apple_cd.addr());
2345 >                r.a[0] = pb;
2346                  Execute68kTrap(0xa000, &r);             // Open()
2347          }
2348  

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