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root/cebix/SheepShaver/src/rom_patches.cpp

Comparing SheepShaver/src/rom_patches.cpp (file contents):
Revision 1.20 by gbeauche, 2003-12-14T14:23:46Z vs.
Revision 1.25 by gbeauche, 2004-01-31T11:10:48Z

#	Line 1 | Line 1
1		/*
2		*  rom_patches.cpp - ROM patches
3		*
4	<	*  SheepShaver (C) 1997-2002 Christian Bauer and Marc Hellwig
4	>	*  SheepShaver (C) 1997-2004 Christian Bauer and Marc Hellwig
5		*
6		*  This program is free software; you can redistribute it and/or modify
7		*  it under the terms of the GNU General Public License as published by
#	Line 62 | Line 62
62		const uint32 CHECK_LOAD_PATCH_SPACE = 0x2fcf00;
63		const uint32 PUT_SCRAP_PATCH_SPACE = 0x2fcf80;
64		const uint32 GET_SCRAP_PATCH_SPACE = 0x2fcfc0;
65	<	const uint32 ADDR_MAP_PATCH_SPACE = 0x2fd000;
65	>	const uint32 ADDR_MAP_PATCH_SPACE = 0x2fd100;
66
67		// Global variables
68		int ROMType;                            // ROM type
#	Line 311 | Line 311 | static uint32 find_rom_powerpc_branch(ui
311
312
313		/*
314	+	*  Check that requested ROM patch space is really available
315	+	*/
316	+
317	+	static bool check_rom_patch_space(uint32 base, uint32 size)
318	+	{
319	+	size = (size + 3) & -4;
320	+	for (int i = 0; i < size; i += 4) {
321	+	uint32 x = ntohl(*(uint32 *)(ROM_BASE + base + i));
322	+	if (x != 0x6b636b63 && x != 0)
323	+	return false;
324	+	}
325	+	return true;
326	+	}
327	+
328	+
329	+	/*
330		*  List of audio sifters installed in ROM and System file
331		*/
332
#	Line 697 | Line 713 | bool PatchROM(void)
713		return false;
714
715		// Check that other ROM addresses point to really free regions
716	<	if (ntohl(*(uint32 *)(ROM_BASE + CHECK_LOAD_PATCH_SPACE)) != 0x6b636b63)
716	>	if (!check_rom_patch_space(CHECK_LOAD_PATCH_SPACE, 0x40))
717		return false;
718	<	if (ntohl(*(uint32 *)(ROM_BASE + PUT_SCRAP_PATCH_SPACE)) != 0x6b636b63)
718	>	if (!check_rom_patch_space(PUT_SCRAP_PATCH_SPACE, 0x40))
719		return false;
720	<	if (ntohl(*(uint32 *)(ROM_BASE + GET_SCRAP_PATCH_SPACE)) != 0x6b636b63)
720	>	if (!check_rom_patch_space(GET_SCRAP_PATCH_SPACE, 0x40))
721		return false;
722	<	if (ntohl(*(uint32 *)(ROM_BASE + ADDR_MAP_PATCH_SPACE)) != 0x6b636b63)
722	>	if (!check_rom_patch_space(ADDR_MAP_PATCH_SPACE - 10 * 4, 0x100))
723		return false;
724
725		// Apply patches
#	Line 890 | Line 906 | static bool patch_nanokernel_boot(void)
906		lp[7] = htonl(0x00080008);      // Inst cache assoc/Data cache assoc
907		lp[8] = htonl(0x00800004);      // TLB total size/TLB assoc
908		break;
909	+	case 0x8000:    // 7400
910	+	case 0x800c:    // 7410
911	+	lp[0] = htonl(0x1000);          // Page size
912	+	lp[1] = htonl(0x8000);          // Data cache size
913	+	lp[2] = htonl(0x8000);          // Inst cache size
914	+	lp[3] = htonl(0x00200020);      // Coherency block size/Reservation granule size
915	+	lp[4] = htonl(0x00000020);      // Unified caches/Inst cache line size
916	+	lp[5] = htonl(0x00200020);      // Data cache line size/Data cache block size touch
917	+	lp[6] = htonl(0x00200020);      // Inst cache block size/Data cache block size
918	+	lp[7] = htonl(0x00080008);      // Inst cache assoc/Data cache assoc
919	+	lp[8] = htonl(0x00800002);      // TLB total size/TLB assoc
920	+	break;
921		default:
922		printf("WARNING: Unknown CPU type\n");
923		break;
#	Line 1646 | Line 1674 | static bool patch_68k(void)
1674		D(bug("scc_init_caller %08lx\n", base + 12));
1675		wp = (uint16 *)(ROM_BASE + base + 12);
1676		loc = ntohs(wp[1]) + ((uintptr)wp - ROM_BASE) + 2;
1677	<	static const uint8 scc_init_dat[] = {0x08, 0x38, 0x00, 0x03, 0x0d, 0xd3, 0x67, 0x12, 0x20, 0x78, 0x01, 0xdc, 0x22, 0x78, 0x01, 0xd8};
1678	<	if ((base = find_rom_data(loc, loc + 0x80, scc_init_dat, sizeof(scc_init_dat))) != loc) return false;
1677	>	static const uint8 scc_init_dat[] = {0x20, 0x78, 0x01, 0xdc, 0x22, 0x78, 0x01, 0xd8};
1678	>	if ((base = find_rom_data(loc, loc + 0x80, scc_init_dat, sizeof(scc_init_dat))) == 0) return false;
1679		D(bug("scc_init %08lx\n", base));
1680		wp = (uint16 *)(ROM_BASE + base);
1681		*wp++ = htons(M68K_EMUL_OP_RESET);

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