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root/cebix/SheepShaver/src/rom_patches.cpp
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Comparing SheepShaver/src/rom_patches.cpp (file contents):
Revision 1.24 by cebix, 2004-01-12T15:37:18Z vs.
Revision 1.25 by gbeauche, 2004-01-31T11:10:48Z

# Line 906 | Line 906 | static bool patch_nanokernel_boot(void)
906                          lp[7] = htonl(0x00080008);      // Inst cache assoc/Data cache assoc
907                          lp[8] = htonl(0x00800004);      // TLB total size/TLB assoc
908                          break;
909 +                case 0x8000:    // 7400
910 +                case 0x800c:    // 7410
911 +                        lp[0] = htonl(0x1000);          // Page size
912 +                        lp[1] = htonl(0x8000);          // Data cache size
913 +                        lp[2] = htonl(0x8000);          // Inst cache size
914 +                        lp[3] = htonl(0x00200020);      // Coherency block size/Reservation granule size
915 +                        lp[4] = htonl(0x00000020);      // Unified caches/Inst cache line size
916 +                        lp[5] = htonl(0x00200020);      // Data cache line size/Data cache block size touch
917 +                        lp[6] = htonl(0x00200020);      // Inst cache block size/Data cache block size
918 +                        lp[7] = htonl(0x00080008);      // Inst cache assoc/Data cache assoc
919 +                        lp[8] = htonl(0x00800002);      // TLB total size/TLB assoc
920 +                        break;
921                  default:
922                          printf("WARNING: Unknown CPU type\n");
923                          break;

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