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root/cebix/SheepShaver/src/rom_patches.cpp

Comparing SheepShaver/src/rom_patches.cpp (file contents):
Revision 1.1.1.1 by cebix, 2002-02-04T16:58:13Z vs.
Revision 1.25 by gbeauche, 2004-01-31T11:10:48Z

#	Line 1 | Line 1
1		/*
2		*  rom_patches.cpp - ROM patches
3		*
4	<	*  SheepShaver (C) 1997-2002 Christian Bauer and Marc Hellwig
4	>	*  SheepShaver (C) 1997-2004 Christian Bauer and Marc Hellwig
5		*
6		*  This program is free software; you can redistribute it and/or modify
7		*  it under the terms of the GNU General Public License as published by
#	Line 40 | Line 40
40		#include "audio_defs.h"
41		#include "serial.h"
42		#include "macos_util.h"
43	+	#include "thunks.h"
44
45		#define DEBUG 0
46		#include "debug.h"
#	Line 58 | Line 59
59
60
61		// Other ROM addresses
62	<	const uint32 CHECK_LOAD_PATCH_SPACE = 0x2f7f00;
63	<	const uint32 PUT_SCRAP_PATCH_SPACE = 0x2f7f80;
64	<	const uint32 GET_SCRAP_PATCH_SPACE = 0x2f7fc0;
65	<	const uint32 ADDR_MAP_PATCH_SPACE = 0x2f8000;
62	>	const uint32 CHECK_LOAD_PATCH_SPACE = 0x2fcf00;
63	>	const uint32 PUT_SCRAP_PATCH_SPACE = 0x2fcf80;
64	>	const uint32 GET_SCRAP_PATCH_SPACE = 0x2fcfc0;
65	>	const uint32 ADDR_MAP_PATCH_SPACE = 0x2fd100;
66
67		// Global variables
68		int ROMType;                            // ROM type
#	Line 74 | Line 75 | static bool patch_nanokernel(void);
75		static bool patch_68k(void);
76
77
78	+	// Decode LZSS data
79	+	static void decode_lzss(const uint8 *src, uint8 *dest, int size)
80	+	{
81	+	char dict[0x1000];
82	+	int run_mask = 0, dict_idx = 0xfee;
83	+	for (;;) {
84	+	if (run_mask < 0x100) {
85	+	// Start new run
86	+	if (--size < 0)
87	+	break;
88	+	run_mask = *src++ | 0xff00;
89	+	}
90	+	bool bit = run_mask & 1;
91	+	run_mask >>= 1;
92	+	if (bit) {
93	+	// Verbatim copy
94	+	if (--size < 0)
95	+	break;
96	+	int c = *src++;
97	+	dict[dict_idx++] = c;
98	+	*dest++ = c;
99	+	dict_idx &= 0xfff;
100	+	} else {
101	+	// Copy from dictionary
102	+	if (--size < 0)
103	+	break;
104	+	int idx = *src++;
105	+	if (--size < 0)
106	+	break;
107	+	int cnt = *src++;
108	+	idx |= (cnt << 4) & 0xf00;
109	+	cnt = (cnt & 0x0f) + 3;
110	+	while (cnt--) {
111	+	char c = dict[idx++];
112	+	dict[dict_idx++] = c;
113	+	*dest++ = c;
114	+	idx &= 0xfff;
115	+	dict_idx &= 0xfff;
116	+	}
117	+	}
118	+	}
119	+	}
120	+
121	+	// Decode parcels of ROM image (MacOS 9.X and even earlier)
122	+	void decode_parcels(const uint8 *src, uint8 *dest, int size)
123	+	{
124	+	uint32 parcel_offset = 0x14;
125	+	D(bug("Offset   Type Name\n"));
126	+	while (parcel_offset != 0) {
127	+	const uint32 *parcel_data = (uint32 *)(src + parcel_offset);
128	+	uint32 next_offset = ntohl(parcel_data[0]);
129	+	uint32 parcel_type = ntohl(parcel_data[1]);
130	+	D(bug("%08x %c%c%c%c %s\n", parcel_offset,
131	+	(parcel_type >> 24) & 0xff, (parcel_type >> 16) & 0xff,
132	+	(parcel_type >> 8) & 0xff, parcel_type & 0xff, &parcel_data[6]));
133	+	if (parcel_type == FOURCC('r','o','m',' ')) {
134	+	uint32 lzss_offset  = ntohl(parcel_data[2]);
135	+	uint32 lzss_size = ((uintptr)src + next_offset) - ((uintptr)parcel_data + lzss_offset);
136	+	decode_lzss((uint8 *)parcel_data + lzss_offset, dest, lzss_size);
137	+	}
138	+	parcel_offset = next_offset;
139	+	}
140	+	}
141	+
142	+
143	+	/*
144	+	*  Decode ROM image, 4 MB plain images or NewWorld images
145	+	*/
146	+
147	+	bool DecodeROM(uint8 *data, uint32 size)
148	+	{
149	+	if (size == ROM_SIZE) {
150	+	// Plain ROM image
151	+	memcpy((void *)ROM_BASE, data, ROM_SIZE);
152	+	return true;
153	+	}
154	+	else if (strncmp((char *)data, "<CHRP-BOOT>", 11) == 0) {
155	+	// CHRP compressed ROM image
156	+	uint32 image_offset, image_size;
157	+	bool decode_info_ok = false;
158	+
159	+	char *s = strstr((char *)data, "constant lzss-offset");
160	+	if (s != NULL) {
161	+	// Probably a plain LZSS compressed ROM image
162	+	if (sscanf(s - 7, "%06x", &image_offset) == 1) {
163	+	s = strstr((char *)data, "constant lzss-size");
164	+	if (s != NULL && (sscanf(s - 7, "%06x", &image_size) == 1))
165	+	decode_info_ok = true;
166	+	}
167	+	}
168	+	else {
169	+	// Probably a MacOS 9.2.x ROM image
170	+	s = strstr((char *)data, "constant parcels-offset");
171	+	if (s != NULL) {
172	+	if (sscanf(s - 7, "%06x", &image_offset) == 1) {
173	+	s = strstr((char *)data, "constant parcels-size");
174	+	if (s != NULL && (sscanf(s - 7, "%06x", &image_size) == 1))
175	+	decode_info_ok = true;
176	+	}
177	+	}
178	+	}
179	+
180	+	// No valid information to decode the ROM found?
181	+	if (!decode_info_ok)
182	+	return false;
183	+
184	+	// Check signature, this could be a parcels-based ROM image
185	+	uint32 rom_signature = ntohl(*(uint32 *)(data + image_offset));
186	+	if (rom_signature == FOURCC('p','r','c','l')) {
187	+	D(bug("Offset of parcels data: %08x\n", image_offset));
188	+	D(bug("Size of parcels data: %08x\n", image_size));
189	+	decode_parcels(data + image_offset, (uint8 *)ROM_BASE, image_size);
190	+	}
191	+	else {
192	+	D(bug("Offset of compressed data: %08x\n", image_offset));
193	+	D(bug("Size of compressed data: %08x\n", image_size));
194	+	decode_lzss(data + image_offset, (uint8 *)ROM_BASE, image_size);
195	+	}
196	+	return true;
197	+	}
198	+	return false;
199	+	}
200	+
201	+
202		/*
203		*  Search ROM for byte string, return ROM offset (or 0)
204		*/
#	Line 145 | Line 270 | static uint32 find_rom_trap(uint16 trap)
270
271
272		/*
273	+	*  Return target of branch instruction specified at ADDR, or 0 if
274	+	*  there is no such instruction
275	+	*/
276	+
277	+	static uint32 powerpc_branch_target(uintptr addr)
278	+	{
279	+	uint32 opcode = ntohl(*(uint32 *)addr);
280	+	uint32 primop = opcode >> 26;
281	+	uint32 target = 0;
282	+
283	+	if (primop == 18) {                     // Branch
284	+	target = opcode & 0x3fffffc;
285	+	if (target & 0x2000000)
286	+	target |= 0xfc000000;
287	+	if ((opcode & 2) == 0)
288	+	target += addr;
289	+	}
290	+	else if (primop == 16) {        // Branch Conditional
291	+	target = (int32)(int16)(opcode & 0xfffc);
292	+	if ((opcode & 2) == 0)
293	+	target += addr;
294	+	}
295	+	return target;
296	+	}
297	+
298	+
299	+	/*
300	+	*  Search ROM for instruction branching to target address, return 0 if none found
301	+	*/
302	+
303	+	static uint32 find_rom_powerpc_branch(uint32 start, uint32 end, uint32 target)
304	+	{
305	+	for (uint32 addr = start; addr < end; addr += 4) {
306	+	if (powerpc_branch_target(ROM_BASE + addr) == ROM_BASE + target)
307	+	return addr;
308	+	}
309	+	return 0;
310	+	}
311	+
312	+
313	+	/*
314	+	*  Check that requested ROM patch space is really available
315	+	*/
316	+
317	+	static bool check_rom_patch_space(uint32 base, uint32 size)
318	+	{
319	+	size = (size + 3) & -4;
320	+	for (int i = 0; i < size; i += 4) {
321	+	uint32 x = ntohl(*(uint32 *)(ROM_BASE + base + i));
322	+	if (x != 0x6b636b63 && x != 0)
323	+	return false;
324	+	}
325	+	return true;
326	+	}
327	+
328	+
329	+	/*
330		*  List of audio sifters installed in ROM and System file
331		*/
332
#	Line 323 | Line 505 | static const uint8 cdrom_driver[] = {  //
505		0x4e, 0x75                                                      //  rts
506		};
507
508	<	#ifdef __linux__
327	<	static uint32 serial_nothing_tvect[2] = {(uint32)SerialNothing, 0};
328	<	static uint32 serial_open_tvect[2] = {(uint32)SerialOpen, 0};
329	<	static uint32 serial_prime_in_tvect[2] = {(uint32)SerialPrimeIn, 0};
330	<	static uint32 serial_prime_out_tvect[2] = {(uint32)SerialPrimeOut, 0};
331	<	static uint32 serial_control_tvect[2] = {(uint32)SerialControl, 0};
332	<	static uint32 serial_status_tvect[2] = {(uint32)SerialStatus, 0};
333	<	static uint32 serial_close_tvect[2] = {(uint32)SerialClose, 0};
334	<	#endif
508	>	static uint32 long_ptr;
509
510	<	static const uint32 ain_driver[] = {    // .AIn driver header
511	<	0x4d000000, 0x00000000,
512	<	0x00200040, 0x00600080,
513	<	0x00a0042e, 0x41496e00,
514	<	0x00000000, 0x00000000,
515	<	0xaafe0700, 0x00000000,
516	<	0x00000000, 0x00179822,
517	<	#ifdef __linux__
518	<	0x00010004, (uint32)serial_nothing_tvect,
519	<	#else
520	<	0x00010004, (uint32)SerialNothing,
521	<	#endif
522	<	0x00000000, 0x00000000,
523	<	0xaafe0700, 0x00000000,
524	<	0x00000000, 0x00179822,
525	<	#ifdef __linux__
526	<	0x00010004, (uint32)serial_prime_in_tvect,
527	<	#else
528	<	0x00010004, (uint32)SerialPrimeIn,
529	<	#endif
530	<	0x00000000, 0x00000000,
531	<	0xaafe0700, 0x00000000,
532	<	0x00000000, 0x00179822,
533	<	#ifdef __linux__
534	<	0x00010004, (uint32)serial_control_tvect,
535	<	#else
536	<	0x00010004, (uint32)SerialControl,
537	<	#endif
538	<	0x00000000, 0x00000000,
539	<	0xaafe0700, 0x00000000,
540	<	0x00000000, 0x00179822,
541	<	#ifdef __linux__
542	<	0x00010004, (uint32)serial_status_tvect,
543	<	#else
544	<	0x00010004, (uint32)SerialStatus,
545	<	#endif
546	<	0x00000000, 0x00000000,
547	<	0xaafe0700, 0x00000000,
548	<	0x00000000, 0x00179822,
549	<	#ifdef __linux__
376	<	0x00010004, (uint32)serial_nothing_tvect,
377	<	#else
378	<	0x00010004, (uint32)SerialNothing,
379	<	#endif
380	<	0x00000000, 0x00000000,
510	>	static void SetLongBase(uint32 addr)
511	>	{
512	>	long_ptr = addr;
513	>	}
514	>
515	>	static void Long(uint32 value)
516	>	{
517	>	WriteMacInt32(long_ptr, value);
518	>	long_ptr += 4;
519	>	}
520	>
521	>	static void gen_ain_driver(uintptr addr)
522	>	{
523	>	SetLongBase(addr);
524	>
525	>	// .AIn driver header
526	>	Long(0x4d000000); Long(0x00000000);
527	>	Long(0x00200040); Long(0x00600080);
528	>	Long(0x00a0042e); Long(0x41496e00);
529	>	Long(0x00000000); Long(0x00000000);
530	>	Long(0xaafe0700); Long(0x00000000);
531	>	Long(0x00000000); Long(0x00179822);
532	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_NOTHING));
533	>	Long(0x00000000); Long(0x00000000);
534	>	Long(0xaafe0700); Long(0x00000000);
535	>	Long(0x00000000); Long(0x00179822);
536	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_PRIME_IN));
537	>	Long(0x00000000); Long(0x00000000);
538	>	Long(0xaafe0700); Long(0x00000000);
539	>	Long(0x00000000); Long(0x00179822);
540	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CONTROL));
541	>	Long(0x00000000); Long(0x00000000);
542	>	Long(0xaafe0700); Long(0x00000000);
543	>	Long(0x00000000); Long(0x00179822);
544	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_STATUS));
545	>	Long(0x00000000); Long(0x00000000);
546	>	Long(0xaafe0700); Long(0x00000000);
547	>	Long(0x00000000); Long(0x00179822);
548	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_NOTHING));
549	>	Long(0x00000000); Long(0x00000000);
550		};
551
552	<	static const uint32 aout_driver[] = {   // .AOut driver header
553	<	0x4d000000, 0x00000000,
554	<	0x00200040, 0x00600080,
555	<	0x00a0052e, 0x414f7574,
556	<	0x00000000, 0x00000000,
557	<	0xaafe0700, 0x00000000,
558	<	0x00000000, 0x00179822,
559	<	#ifdef __linux__
560	<	0x00010004, (uint32)serial_open_tvect,
561	<	#else
562	<	0x00010004, (uint32)SerialOpen,
563	<	#endif
564	<	0x00000000, 0x00000000,
565	<	0xaafe0700, 0x00000000,
566	<	0x00000000, 0x00179822,
567	<	#ifdef __linux__
568	<	0x00010004, (uint32)serial_prime_out_tvect,
569	<	#else
570	<	0x00010004, (uint32)SerialPrimeOut,
571	<	#endif
572	<	0x00000000, 0x00000000,
573	<	0xaafe0700, 0x00000000,
574	<	0x00000000, 0x00179822,
575	<	#ifdef __linux__
576	<	0x00010004, (uint32)serial_control_tvect,
577	<	#else
578	<	0x00010004, (uint32)SerialControl,
579	<	#endif
580	<	0x00000000, 0x00000000,
412	<	0xaafe0700, 0x00000000,
413	<	0x00000000, 0x00179822,
414	<	#ifdef __linux__
415	<	0x00010004, (uint32)serial_status_tvect,
416	<	#else
417	<	0x00010004, (uint32)SerialStatus,
418	<	#endif
419	<	0x00000000, 0x00000000,
420	<	0xaafe0700, 0x00000000,
421	<	0x00000000, 0x00179822,
422	<	#ifdef __linux__
423	<	0x00010004, (uint32)serial_close_tvect,
424	<	#else
425	<	0x00010004, (uint32)SerialClose,
426	<	#endif
427	<	0x00000000, 0x00000000,
552	>	static void gen_aout_driver(uintptr addr)
553	>	{
554	>	SetLongBase(addr);
555	>
556	>	// .AOut driver header
557	>	Long(0x4d000000); Long(0x00000000);
558	>	Long(0x00200040); Long(0x00600080);
559	>	Long(0x00a0052e); Long(0x414f7574);
560	>	Long(0x00000000); Long(0x00000000);
561	>	Long(0xaafe0700); Long(0x00000000);
562	>	Long(0x00000000); Long(0x00179822);
563	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_OPEN));
564	>	Long(0x00000000); Long(0x00000000);
565	>	Long(0xaafe0700); Long(0x00000000);
566	>	Long(0x00000000); Long(0x00179822);
567	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_PRIME_OUT));
568	>	Long(0x00000000); Long(0x00000000);
569	>	Long(0xaafe0700); Long(0x00000000);
570	>	Long(0x00000000); Long(0x00179822);
571	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CONTROL));
572	>	Long(0x00000000); Long(0x00000000);
573	>	Long(0xaafe0700); Long(0x00000000);
574	>	Long(0x00000000); Long(0x00179822);
575	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_STATUS));
576	>	Long(0x00000000); Long(0x00000000);
577	>	Long(0xaafe0700); Long(0x00000000);
578	>	Long(0x00000000); Long(0x00179822);
579	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CLOSE));
580	>	Long(0x00000000); Long(0x00000000);
581		};
582
583	<	static const uint32 bin_driver[] = {    // .BIn driver header
584	<	0x4d000000, 0x00000000,
585	<	0x00200040, 0x00600080,
586	<	0x00a0042e, 0x42496e00,
587	<	0x00000000, 0x00000000,
588	<	0xaafe0700, 0x00000000,
589	<	0x00000000, 0x00179822,
590	<	#ifdef __linux__
591	<	0x00010004, (uint32)serial_nothing_tvect,
592	<	#else
593	<	0x00010004, (uint32)SerialNothing,
594	<	#endif
595	<	0x00000000, 0x00000000,
596	<	0xaafe0700, 0x00000000,
597	<	0x00000000, 0x00179822,
598	<	#ifdef __linux__
599	<	0x00010004, (uint32)serial_prime_in_tvect,
600	<	#else
601	<	0x00010004, (uint32)SerialPrimeIn,
602	<	#endif
603	<	0x00000000, 0x00000000,
604	<	0xaafe0700, 0x00000000,
605	<	0x00000000, 0x00179822,
606	<	#ifdef __linux__
607	<	0x00010004, (uint32)serial_control_tvect,
608	<	#else
609	<	0x00010004, (uint32)SerialControl,
610	<	#endif
611	<	0x00000000, 0x00000000,
459	<	0xaafe0700, 0x00000000,
460	<	0x00000000, 0x00179822,
461	<	#ifdef __linux__
462	<	0x00010004, (uint32)serial_status_tvect,
463	<	#else
464	<	0x00010004, (uint32)SerialStatus,
465	<	#endif
466	<	0x00000000, 0x00000000,
467	<	0xaafe0700, 0x00000000,
468	<	0x00000000, 0x00179822,
469	<	#ifdef __linux__
470	<	0x00010004, (uint32)serial_nothing_tvect,
471	<	#else
472	<	0x00010004, (uint32)SerialNothing,
473	<	#endif
474	<	0x00000000, 0x00000000,
583	>	static void gen_bin_driver(uintptr addr)
584	>	{
585	>	SetLongBase(addr);
586	>
587	>	// .BIn driver header
588	>	Long(0x4d000000); Long(0x00000000);
589	>	Long(0x00200040); Long(0x00600080);
590	>	Long(0x00a0042e); Long(0x42496e00);
591	>	Long(0x00000000); Long(0x00000000);
592	>	Long(0xaafe0700); Long(0x00000000);
593	>	Long(0x00000000); Long(0x00179822);
594	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_NOTHING));
595	>	Long(0x00000000); Long(0x00000000);
596	>	Long(0xaafe0700); Long(0x00000000);
597	>	Long(0x00000000); Long(0x00179822);
598	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_PRIME_IN));
599	>	Long(0x00000000); Long(0x00000000);
600	>	Long(0xaafe0700); Long(0x00000000);
601	>	Long(0x00000000); Long(0x00179822);
602	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CONTROL));
603	>	Long(0x00000000); Long(0x00000000);
604	>	Long(0xaafe0700); Long(0x00000000);
605	>	Long(0x00000000); Long(0x00179822);
606	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_STATUS));
607	>	Long(0x00000000); Long(0x00000000);
608	>	Long(0xaafe0700); Long(0x00000000);
609	>	Long(0x00000000); Long(0x00179822);
610	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_NOTHING));
611	>	Long(0x00000000); Long(0x00000000);
612		};
613
614	<	static const uint32 bout_driver[] = {   // .BOut driver header
615	<	0x4d000000, 0x00000000,
616	<	0x00200040, 0x00600080,
617	<	0x00a0052e, 0x424f7574,
618	<	0x00000000, 0x00000000,
619	<	0xaafe0700, 0x00000000,
620	<	0x00000000, 0x00179822,
621	<	#ifdef __linux__
622	<	0x00010004, (uint32)serial_open_tvect,
623	<	#else
624	<	0x00010004, (uint32)SerialOpen,
625	<	#endif
626	<	0x00000000, 0x00000000,
627	<	0xaafe0700, 0x00000000,
628	<	0x00000000, 0x00179822,
629	<	#ifdef __linux__
630	<	0x00010004, (uint32)serial_prime_out_tvect,
631	<	#else
632	<	0x00010004, (uint32)SerialPrimeOut,
633	<	#endif
634	<	0x00000000, 0x00000000,
635	<	0xaafe0700, 0x00000000,
636	<	0x00000000, 0x00179822,
637	<	#ifdef __linux__
638	<	0x00010004, (uint32)serial_control_tvect,
639	<	#else
640	<	0x00010004, (uint32)SerialControl,
641	<	#endif
642	<	0x00000000, 0x00000000,
506	<	0xaafe0700, 0x00000000,
507	<	0x00000000, 0x00179822,
508	<	#ifdef __linux__
509	<	0x00010004, (uint32)serial_status_tvect,
510	<	#else
511	<	0x00010004, (uint32)SerialStatus,
512	<	#endif
513	<	0x00000000, 0x00000000,
514	<	0xaafe0700, 0x00000000,
515	<	0x00000000, 0x00179822,
516	<	#ifdef __linux__
517	<	0x00010004, (uint32)serial_close_tvect,
518	<	#else
519	<	0x00010004, (uint32)SerialClose,
520	<	#endif
521	<	0x00000000, 0x00000000,
614	>	static void gen_bout_driver(uintptr addr)
615	>	{
616	>	SetLongBase(addr);
617	>
618	>	// .BOut driver header
619	>	Long(0x4d000000); Long(0x00000000);
620	>	Long(0x00200040); Long(0x00600080);
621	>	Long(0x00a0052e); Long(0x424f7574);
622	>	Long(0x00000000); Long(0x00000000);
623	>	Long(0xaafe0700); Long(0x00000000);
624	>	Long(0x00000000); Long(0x00179822);
625	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_OPEN));
626	>	Long(0x00000000); Long(0x00000000);
627	>	Long(0xaafe0700); Long(0x00000000);
628	>	Long(0x00000000); Long(0x00179822);
629	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_PRIME_OUT));
630	>	Long(0x00000000); Long(0x00000000);
631	>	Long(0xaafe0700); Long(0x00000000);
632	>	Long(0x00000000); Long(0x00179822);
633	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CONTROL));
634	>	Long(0x00000000); Long(0x00000000);
635	>	Long(0xaafe0700); Long(0x00000000);
636	>	Long(0x00000000); Long(0x00179822);
637	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_STATUS));
638	>	Long(0x00000000); Long(0x00000000);
639	>	Long(0xaafe0700); Long(0x00000000);
640	>	Long(0x00000000); Long(0x00179822);
641	>	Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CLOSE));
642	>	Long(0x00000000); Long(0x00000000);
643		};
644
645		static const uint8 adbop_patch[] = {    // Call ADBOp() completion procedure
#	Line 545 | Line 666 | static const uint8 adbop_patch[] = {   //
666
667
668		/*
669	+	*  Copy PowerPC code to ROM image and reverse bytes if necessary
670	+	*/
671	+
672	+	static inline void memcpy_powerpc_code(void *dst, const void *src, size_t len)
673	+	{
674	+	#ifdef WORDS_BIGENDIAN
675	+	(void)memcpy(dst, src, len);
676	+	#else
677	+	uint32 *d = (uint32 *)dst;
678	+	uint32 *s = (uint32 *)src;
679	+	for (int i = 0; i < len/4; i++)
680	+	d[i] = htonl(s[i]);
681	+	#endif
682	+	}
683	+
684	+
685	+	/*
686		*  Install ROM patches (RAMBase and KernelDataAddr must be set)
687		*/
688
#	Line 567 | Line 705 | bool PatchROM(void)
705		ROMType = ROMTYPE_ZANZIBAR;
706		else if (!memcmp((void *)(ROM_BASE + 0x30d064), "Boot Gazelle", 12))
707		ROMType = ROMTYPE_GAZELLE;
708	+	else if (!memcmp((void *)(ROM_BASE + 0x30d064), "Boot Gossamer", 13))
709	+	ROMType = ROMTYPE_GOSSAMER;
710		else if (!memcmp((void *)(ROM_BASE + 0x30d064), "NewWorld", 8))
711		ROMType = ROMTYPE_NEWWORLD;
712		else
713		return false;
714
715	+	// Check that other ROM addresses point to really free regions
716	+	if (!check_rom_patch_space(CHECK_LOAD_PATCH_SPACE, 0x40))
717	+	return false;
718	+	if (!check_rom_patch_space(PUT_SCRAP_PATCH_SPACE, 0x40))
719	+	return false;
720	+	if (!check_rom_patch_space(GET_SCRAP_PATCH_SPACE, 0x40))
721	+	return false;
722	+	if (!check_rom_patch_space(ADDR_MAP_PATCH_SPACE - 10 * 4, 0x100))
723	+	return false;
724	+
725		// Apply patches
726		if (!patch_nanokernel_boot()) return false;
727		if (!patch_68k_emul()) return false;
#	Line 604 | Line 754 | bool PatchROM(void)
754		static bool patch_nanokernel_boot(void)
755		{
756		uint32 *lp;
757	+	uint32 base, loc;
758
759		// ROM boot structure patches
760		lp = (uint32 *)(ROM_BASE + 0x30d000);
#	Line 616 | Line 767 | static bool patch_nanokernel_boot(void)
767		lp[0xfd8 >> 2] = htonl(ROM_BASE + 0x2a);                // 68k reset vector
768
769		// Skip SR/BAT/SDR init
770	<	if (ROMType == ROMTYPE_GAZELLE || ROMType == ROMTYPE_NEWWORLD) {
771	<	lp = (uint32 *)(ROM_BASE + 0x310000);
770	>	loc = 0x310000;
771	>	if (ROMType == ROMTYPE_GAZELLE || ROMType == ROMTYPE_GOSSAMER || ROMType == ROMTYPE_NEWWORLD) {
772	>	lp = (uint32 *)(ROM_BASE + loc);
773		*lp++ = htonl(POWERPC_NOP);
774		*lp = htonl(0x38000000);
775		}
776	<	static const uint32 sr_init_loc[] = {0x3101b0, 0x3101b0, 0x3101b0, 0x3101ec, 0x310200};
777	<	lp = (uint32 *)(ROM_BASE + 0x310008);
778	<	*lp = htonl(0x48000000 | (sr_init_loc[ROMType] - 8) & 0xffff);  // b            ROM_BASE+0x3101b0
779	<	lp = (uint32 *)(ROM_BASE + sr_init_loc[ROMType]);
776	>	static const uint8 sr_init_dat[] = {0x35, 0x4a, 0xff, 0xfc, 0x7d, 0x86, 0x50, 0x2e};
777	>	if ((base = find_rom_data(0x3101b0, 0x3105b0, sr_init_dat, sizeof(sr_init_dat))) == 0) return false;
778	>	D(bug("sr_init %08lx\n", base));
779	>	lp = (uint32 *)(ROM_BASE + loc + 8);
780	>	*lp = htonl(0x48000000 | ((base - loc - 8) & 0x3fffffc));       // b            ROM_BASE+0x3101b0
781	>	lp = (uint32 *)(ROM_BASE + base);
782		*lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);            // lwz  r1,(pointer to Kernel Data)
783		*lp++ = htonl(0x3da0dead);              // lis  r13,0xdead      (start of kernel memory)
784		*lp++ = htonl(0x3dc00010);              // lis  r14,0x0010      (size of page table)
785		*lp = htonl(0x3de00010);                // lis  r15,0x0010      (size of kernel memory)
786
787		// Don't read PVR
788	<	static const uint32 pvr_loc[] = {0x3103b0, 0x3103b4, 0x3103b4, 0x310400, 0x310438};
789	<	lp = (uint32 *)(ROM_BASE + pvr_loc[ROMType]);
788	>	static const uint8 pvr_read_dat[] = {0x7d, 0x9f, 0x42, 0xa6};
789	>	if ((base = find_rom_data(0x3103b0, 0x3108b0, pvr_read_dat, sizeof(pvr_read_dat))) == 0) return false;
790	>	D(bug("pvr_read %08lx\n", base));
791	>	lp = (uint32 *)(ROM_BASE + base);
792		*lp = htonl(0x81800000 + XLM_PVR);      // lwz  r12,(theoretical PVR)
793
794		// Set CPU specific data (even if ROM doesn't have support for that CPU)
639	–	lp = (uint32 *)(ROM_BASE + pvr_loc[ROMType]);
795		if (ntohl(lp[6]) != 0x2c0c0001)
796		return false;
797		uint32 ofs = ntohl(lp[7]) & 0xffff;
798		D(bug("ofs %08lx\n", ofs));
799		lp[8] = htonl((ntohl(lp[8]) & 0xffff) | 0x48000000);    // beq -> b
800	<	uint32 loc = (ntohl(lp[8]) & 0xffff) + (uint32)(lp+8) - ROM_BASE;
800	>	loc = (ntohl(lp[8]) & 0xffff) + (uint32)(lp+8) - ROM_BASE;
801		D(bug("loc %08lx\n", loc));
802		lp = (uint32 *)(ROM_BASE + ofs + 0x310000);
803		switch (PVR >> 16) {
#	Line 751 | Line 906 | static bool patch_nanokernel_boot(void)
906		lp[7] = htonl(0x00080008);      // Inst cache assoc/Data cache assoc
907		lp[8] = htonl(0x00800004);      // TLB total size/TLB assoc
908		break;
909	+	case 0x8000:    // 7400
910	+	case 0x800c:    // 7410
911	+	lp[0] = htonl(0x1000);          // Page size
912	+	lp[1] = htonl(0x8000);          // Data cache size
913	+	lp[2] = htonl(0x8000);          // Inst cache size
914	+	lp[3] = htonl(0x00200020);      // Coherency block size/Reservation granule size
915	+	lp[4] = htonl(0x00000020);      // Unified caches/Inst cache line size
916	+	lp[5] = htonl(0x00200020);      // Data cache line size/Data cache block size touch
917	+	lp[6] = htonl(0x00200020);      // Inst cache block size/Data cache block size
918	+	lp[7] = htonl(0x00080008);      // Inst cache assoc/Data cache assoc
919	+	lp[8] = htonl(0x00800002);      // TLB total size/TLB assoc
920	+	break;
921		default:
922		printf("WARNING: Unknown CPU type\n");
923		break;
924		}
925
926		// Don't set SPRG3, don't test MQ
927	<	lp = (uint32 *)(ROM_BASE + loc + 0x20);
928	<	*lp++ = htonl(POWERPC_NOP);
929	<	lp++;
930	<	*lp++ = htonl(POWERPC_NOP);
931	<	lp++;
932	<	*lp = htonl(POWERPC_NOP);
927	>	static const uint8 sprg3_mq_dat[] = {0x7d, 0x13, 0x43, 0xa6, 0x3d, 0x00, 0x00, 0x04, 0x7d, 0x00, 0x03, 0xa6, 0x39, 0x00, 0x00, 0x00, 0x7d, 0x00, 0x02, 0xa6};
928	>	if ((base = find_rom_data(loc + 0x20, loc + 0x60, sprg3_mq_dat, sizeof(sprg3_mq_dat))) == 0) return false;
929	>	D(bug("sprg3/mq %08lx\n", base));
930	>	lp = (uint32 *)(ROM_BASE + base);
931	>	lp[0] = htonl(POWERPC_NOP);
932	>	lp[2] = htonl(POWERPC_NOP);
933	>	lp[4] = htonl(POWERPC_NOP);
934
935		// Don't read MSR
936	<	lp = (uint32 *)(ROM_BASE + loc + 0x40);
936	>	static const uint8 msr_dat[] = {0x7d, 0xc0, 0x00, 0xa6};
937	>	if ((base = find_rom_data(loc + 0x40, loc + 0x80, msr_dat, sizeof(msr_dat))) == 0) return false;
938	>	D(bug("msr %08lx\n", base));
939	>	lp = (uint32 *)(ROM_BASE + base);
940		*lp = htonl(0x39c00000);                // li   r14,0
941
942		// Don't write to DEC
#	Line 775 | Line 946 | static bool patch_nanokernel_boot(void)
946		D(bug("loc %08lx\n", loc));
947
948		// Don't set SPRG3
949	<	lp = (uint32 *)(ROM_BASE + loc + 0x2c);
949	>	static const uint8 sprg3_dat[] = {0x39, 0x21, 0x03, 0x60, 0x7d, 0x33, 0x43, 0xa6, 0x39, 0x01, 0x04, 0x20};
950	>	if ((base = find_rom_data(0x310000, 0x314000, sprg3_dat, sizeof(sprg3_dat))) == 0) return false;
951	>	D(bug("sprg3 %08lx\n", base + 4));
952	>	lp = (uint32 *)(ROM_BASE + base + 4);
953		*lp = htonl(POWERPC_NOP);
954
955		// Don't read PVR
956	<	static const uint32 pvr_ofs[] = {0x138, 0x138, 0x138, 0x140, 0x148};
957	<	lp = (uint32 *)(ROM_BASE + loc + pvr_ofs[ROMType]);
956	>	static const uint8 pvr_read2_dat[] = {0x7e, 0xff, 0x42, 0xa6, 0x56, 0xf7, 0x84, 0x3e};
957	>	if ((base = find_rom_data(0x310000, 0x320000, pvr_read2_dat, sizeof(pvr_read2_dat))) == 0) return false;
958	>	D(bug("pvr_read2 %08lx\n", base));
959	>	lp = (uint32 *)(ROM_BASE + base);
960		*lp = htonl(0x82e00000 + XLM_PVR);              // lwz  r23,(theoretical PVR)
961	<	lp = (uint32 *)(ROM_BASE + loc + 0x170);
962	<	if (ntohl(*lp) == 0x7eff42a6)   // NewWorld ROM
961	>	if ((base = find_rom_data(base + 4, 0x320000, pvr_read2_dat, sizeof(pvr_read2_dat))) != 0) {
962	>	D(bug("pvr_read2 %08lx\n", base));
963	>	lp = (uint32 *)(ROM_BASE + base);
964		*lp = htonl(0x82e00000 + XLM_PVR);      // lwz  r23,(theoretical PVR)
965	<	lp = (uint32 *)(ROM_BASE + 0x313134);
966	<	if (ntohl(*lp) == 0x7e5f42a6)
967	<	*lp = htonl(0x82400000 + XLM_PVR);      // lwz  r18,(theoretical PVR)
968	<	lp = (uint32 *)(ROM_BASE + 0x3131f4);
969	<	if (ntohl(*lp) == 0x7e5f42a6)   // NewWorld ROM
965	>	}
966	>	static const uint8 pvr_read3_dat[] = {0x7e, 0x5f, 0x42, 0xa6, 0x56, 0x52, 0x84, 0x3e};
967	>	if ((base = find_rom_data(0x310000, 0x320000, pvr_read3_dat, sizeof(pvr_read3_dat))) != 0) {
968	>	D(bug("pvr_read3 %08lx\n", base));
969	>	lp = (uint32 *)(ROM_BASE + base);
970		*lp = htonl(0x82400000 + XLM_PVR);      // lwz  r18,(theoretical PVR)
971	+	}
972	+	static const uint8 pvr_read4_dat[] = {0x7d, 0x3f, 0x42, 0xa6, 0x55, 0x29, 0x84, 0x3e};
973	+	if ((base = find_rom_data(0x310000, 0x320000, pvr_read4_dat, sizeof(pvr_read4_dat))) != 0) {
974	+	D(bug("pvr_read4 %08lx\n", base));
975	+	lp = (uint32 *)(ROM_BASE + base);
976	+	*lp = htonl(0x81200000 + XLM_PVR);      // lzw  r9,(theoritical PVR)
977	+	}
978
979		// Don't read SDR1
980	<	static const uint32 sdr1_ofs[] = {0x174, 0x174, 0x174, 0x17c, 0x19c};
981	<	lp = (uint32 *)(ROM_BASE + loc + sdr1_ofs[ROMType]);
980	>	static const uint8 sdr1_read_dat[] = {0x7d, 0x19, 0x02, 0xa6, 0x55, 0x16, 0x81, 0xde};
981	>	if ((base = find_rom_data(0x310000, 0x320000, sdr1_read_dat, sizeof(sdr1_read_dat))) == 0) return false;
982	>	D(bug("sdr1_read %08lx\n", base));
983	>	lp = (uint32 *)(ROM_BASE + base);
984		*lp++ = htonl(0x3d00dead);              // lis  r8,0xdead               (pointer to page table)
985		*lp++ = htonl(0x3ec0001f);              // lis  r22,0x001f      (size of page table)
986		*lp = htonl(POWERPC_NOP);
987
988	<	// Don't clear page table
989	<	static const uint32 pgtb_ofs[] = {0x198, 0x198, 0x198, 0x1a0, 0x1c4};
990	<	lp = (uint32 *)(ROM_BASE + loc + pgtb_ofs[ROMType]);
988	>	// Don't clear page table, don't invalidate TLB
989	>	static const uint8 pgtb_clear_dat[] = {0x36, 0xd6, 0xff, 0xfc, 0x7e, 0xe8, 0xb1, 0x2e, 0x41, 0x81, 0xff, 0xf8};
990	>	if ((base = find_rom_data(0x310000, 0x320000, pgtb_clear_dat, sizeof(pgtb_clear_dat))) == 0) return false;
991	>	D(bug("pgtb_clear %08lx\n", base + 4));
992	>	lp = (uint32 *)(ROM_BASE + base + 4);
993		*lp = htonl(POWERPC_NOP);
994	<
995	<	// Don't invalidate TLB
808	<	static const uint32 tlb_ofs[] = {0x1a0, 0x1a0, 0x1a0, 0x1a8, 0x1cc};
809	<	lp = (uint32 *)(ROM_BASE + loc + tlb_ofs[ROMType]);
994	>	D(bug("tblie %08lx\n", base + 12));
995	>	lp = (uint32 *)(ROM_BASE + base + 12);
996		*lp = htonl(POWERPC_NOP);
997
998		// Don't create RAM descriptor table
999	<	static const uint32 desc_ofs[] = {0x350, 0x350, 0x350, 0x358, 0x37c};
1000	<	lp = (uint32 *)(ROM_BASE + loc + desc_ofs[ROMType]);
999	>	static const uint8 desc_create_dat[] = {0x97, 0xfd, 0x00, 0x04, 0x3b, 0xff, 0x10, 0x00, 0x4b, 0xff, 0xff, 0xdc};
1000	>	if ((base = find_rom_data(0x310000, 0x320000, desc_create_dat, sizeof(desc_create_dat))) == 0) return false;
1001	>	D(bug("desc_create %08lx\n", base))
1002	>	lp = (uint32 *)(ROM_BASE + base);
1003		*lp = htonl(POWERPC_NOP);
1004
1005		// Don't load SRs and BATs
1006	<	static const uint32 sr_ofs[] = {0x3d8, 0x3d8, 0x3d8, 0x3e0, 0x404};
1007	<	lp = (uint32 *)(ROM_BASE + loc + sr_ofs[ROMType]);
1006	>	static const uint8 sr_load[] = {0x7c, 0x00, 0x04, 0xac, 0x83, 0x9d, 0x00, 0x00, 0x93, 0x81, 0x05, 0xe8};
1007	>	if ((loc = find_rom_data(0x310000, 0x320000, sr_load, sizeof(sr_load))) == 0) return false;
1008	>	static const uint8 sr_load_caller[] = {0x3e, 0xd6, 0xff, 0xff, 0x41, 0x81, 0xff, 0xdc, 0xb2, 0xc8, 0x00, 0x02};
1009	>	if ((base = find_rom_data(0x310000, 0x320000, sr_load_caller, sizeof(sr_load_caller))) == 0) return false;
1010	>	if ((base = find_rom_powerpc_branch(base + 12, 0x320000, loc)) == 0) return false;
1011	>	D(bug("sr_load %08lx, called from %08lx\n", loc, base));
1012	>	lp = (uint32 *)(ROM_BASE + base);
1013		*lp = htonl(POWERPC_NOP);
1014
1015		// Don't mess with SRs
1016	<	static const uint32 sr2_ofs[] = {0x312118, 0x312118, 0x312118, 0x312118, 0x3121b4};
1017	<	lp = (uint32 *)(ROM_BASE + sr2_ofs[ROMType]);
1016	>	static const uint8 sr_load2_dat[] = {0x83, 0xa1, 0x05, 0xe8, 0x57, 0x7c, 0x3e, 0x78, 0x7f, 0xbd, 0xe0, 0x2e};
1017	>	if ((base = find_rom_data(0x310000, 0x320000, sr_load2_dat, sizeof(sr_load2_dat))) == 0) return false;
1018	>	D(bug("sr_load2 %08lx\n", base));
1019	>	lp = (uint32 *)(ROM_BASE + base);
1020		*lp = htonl(POWERPC_BLR);
1021
1022		// Don't check performance monitor
1023	<	static const uint32 pm_ofs[] = {0x313148, 0x313148, 0x313148, 0x313148, 0x313218};
1024	<	lp = (uint32 *)(ROM_BASE + pm_ofs[ROMType]);
1025	<	while (ntohl(*lp) != 0x7e58eba6) lp++;
1026	<	*lp++ = htonl(POWERPC_NOP);
1027	<	while (ntohl(*lp) != 0x7e78eaa6) lp++;
1028	<	*lp++ = htonl(POWERPC_NOP);
1029	<	while (ntohl(*lp) != 0x7e59eba6) lp++;
1030	<	*lp++ = htonl(POWERPC_NOP);
1031	<	while (ntohl(*lp) != 0x7e79eaa6) lp++;
1032	<	*lp++ = htonl(POWERPC_NOP);
1033	<	while (ntohl(*lp) != 0x7e5aeba6) lp++;
1034	<	*lp++ = htonl(POWERPC_NOP);
1035	<	while (ntohl(*lp) != 0x7e7aeaa6) lp++;
1036	<	*lp++ = htonl(POWERPC_NOP);
1037	<	while (ntohl(*lp) != 0x7e5beba6) lp++;
1038	<	*lp++ = htonl(POWERPC_NOP);
1039	<	while (ntohl(*lp) != 0x7e7beaa6) lp++;
1040	<	*lp++ = htonl(POWERPC_NOP);
1041	<	while (ntohl(*lp) != 0x7e5feba6) lp++;
1042	<	*lp++ = htonl(POWERPC_NOP);
1043	<	while (ntohl(*lp) != 0x7e7feaa6) lp++;
1044	<	*lp++ = htonl(POWERPC_NOP);
1045	<	while (ntohl(*lp) != 0x7e5ceba6) lp++;
1046	<	*lp++ = htonl(POWERPC_NOP);
852	<	while (ntohl(*lp) != 0x7e7ceaa6) lp++;
853	<	*lp++ = htonl(POWERPC_NOP);
854	<	while (ntohl(*lp) != 0x7e5deba6) lp++;
855	<	*lp++ = htonl(POWERPC_NOP);
856	<	while (ntohl(*lp) != 0x7e7deaa6) lp++;
857	<	*lp++ = htonl(POWERPC_NOP);
858	<	while (ntohl(*lp) != 0x7e5eeba6) lp++;
859	<	*lp++ = htonl(POWERPC_NOP);
860	<	while (ntohl(*lp) != 0x7e7eeaa6) lp++;
861	<	*lp++ = htonl(POWERPC_NOP);
1023	>	static const uint8 pm_check_dat[] = {0x7e, 0x58, 0xeb, 0xa6, 0x7e, 0x53, 0x90, 0xf8, 0x7e, 0x78, 0xea, 0xa6};
1024	>	if ((base = find_rom_data(0x310000, 0x320000, pm_check_dat, sizeof(pm_check_dat))) == 0) return false;
1025	>	D(bug("pm_check %08lx\n", base));
1026	>	lp = (uint32 *)(ROM_BASE + base);
1027	>
1028	>	static const int spr_check_list[] = {
1029	>	952 /* mmcr0 */, 953 /* pmc1 */, 954 /* pmc2 */, 955 /* sia */,
1030	>	956 /* mmcr1 */, 957 /* pmc3 */, 958 /* pmc4 */, 959 /* sda */
1031	>	};
1032	>
1033	>	for (int i = 0; i < sizeof(spr_check_list)/sizeof(spr_check_list[0]); i++) {
1034	>	int spr = spr_check_list[i];
1035	>	uint32 mtspr = 0x7e4003a6 | ((spr & 0x1f) << 16) | ((spr & 0x3e0) << 6);
1036	>	uint32 mfspr = 0x7e6002a6 | ((spr & 0x1f) << 16) | ((spr & 0x3e0) << 6);
1037	>	for (int ofs = 0; ofs < 64; ofs++) {
1038	>	if (ntohl(lp[ofs]) == mtspr) {
1039	>	if (ntohl(lp[ofs + 2]) != mfspr)
1040	>	return false;
1041	>	D(bug("  SPR%d %08lx\n", spr, base + 4*ofs));
1042	>	lp[ofs] = htonl(POWERPC_NOP);
1043	>	lp[ofs + 2] = htonl(POWERPC_NOP);
1044	>	}
1045	>	}
1046	>	}
1047
1048		// Jump to 68k emulator
1049	<	static const uint32 jump68k_ofs[] = {0x40c, 0x40c, 0x40c, 0x414, 0x438};
1050	<	lp = (uint32 *)(ROM_BASE + loc + jump68k_ofs[ROMType]);
1049	>	static const uint8 jump68k_dat[] = {0x7d, 0x92, 0x43, 0xa6, 0x7d, 0x5a, 0x03, 0xa6, 0x7d, 0x7b, 0x03, 0xa6};
1050	>	if ((loc = find_rom_data(0x310000, 0x320000, jump68k_dat, sizeof(jump68k_dat))) == 0) return false;
1051	>	static const uint8 jump68k_caller_dat[] = {0x85, 0x13, 0x00, 0x08, 0x56, 0xbf, 0x50, 0x3e, 0x63, 0xff, 0x0c, 0x00};
1052	>	if ((base = find_rom_data(0x310000, 0x320000, jump68k_caller_dat, sizeof(jump68k_caller_dat))) == 0) return false;
1053	>	if ((base = find_rom_powerpc_branch(base + 12, 0x320000, loc)) == 0) return false;
1054	>	D(bug("jump68k %08lx, called from %08lx\n", loc, base));
1055	>	lp = (uint32 *)(ROM_BASE + base);
1056		*lp++ = htonl(0x80610634);              // lwz  r3,0x0634(r1)   (pointer to Emulator Data)
1057		*lp++ = htonl(0x8081119c);              // lwz  r4,0x119c(r1)   (pointer to opcode table)
1058		*lp++ = htonl(0x80011184);              // lwz  r0,0x1184(r1)   (pointer to emulator init routine)
#	Line 882 | Line 1072 | static bool patch_68k_emul(void)
1072		uint32 base;
1073
1074		// Overwrite twi instructions
1075	<	static const uint32 twi_loc[] = {0x36e680, 0x36e6c0, 0x36e6c0, 0x36e6c0, 0x36e740};
1076	<	base = twi_loc[ROMType];
1075	>	static const uint8 twi_dat[] = {0x0f, 0xff, 0x00, 0x00, 0x0f, 0xff, 0x00, 0x01, 0x0f, 0xff, 0x00, 0x02};
1076	>	if ((base = find_rom_data(0x36e600, 0x36ea00, twi_dat, sizeof(twi_dat))) == 0) return false;
1077	>	D(bug("twi %08lx\n", base));
1078		lp = (uint32 *)(ROM_BASE + base);
1079		*lp++ = htonl(0x48000000 + 0x36f900 - base);            // b 0x36f900 (Emulator start)
1080		*lp++ = htonl(0x48000000 + 0x36fa00 - base - 4);        // b 0x36fa00 (Mixed mode)
#	Line 903 | Line 1094 | static bool patch_68k_emul(void)
1094		*lp = htonl(POWERPC_ILLEGAL);
1095
1096		#if EMULATED_PPC
1097	<	// Install EMUL_RETURN, EXEC_RETURN and EMUL_OP opcodes
1097	>	// Install EMUL_RETURN, EXEC_RETURN, EXEC_NATIVE and EMUL_OP opcodes
1098		lp = (uint32 *)(ROM_BASE + 0x380000 + (M68K_EMUL_RETURN << 3));
1099		*lp++ = htonl(POWERPC_EMUL_OP);
1100		*lp++ = htonl(0x4bf66e80);                                                      // b    0x366084
1101		*lp++ = htonl(POWERPC_EMUL_OP | 1);
1102		*lp++ = htonl(0x4bf66e78);                                                      // b    0x366084
1103	+	*lp++ = htonl(POWERPC_EMUL_OP | 2);
1104	+	*lp++ = htonl(0x4bf66e70);                                                      // b    0x366084
1105		for (int i=0; i<OP_MAX; i++) {
1106	<	*lp++ = htonl(POWERPC_EMUL_OP | (i + 2));
1107	<	*lp++ = htonl(0x4bf66e70 - i*8);                        // b    0x366084
1106	>	*lp++ = htonl(POWERPC_EMUL_OP | (i + 3));
1107	>	*lp++ = htonl(0x4bf66e68 - i*8);                                // b    0x366084
1108		}
1109		#else
1110		// Install EMUL_RETURN, EXEC_RETURN and EMUL_OP opcodes
#	Line 920 | Line 1113 | static bool patch_68k_emul(void)
1113		*lp++ = htonl(0x4bf705fc);                                                      // b    0x36f800
1114		*lp++ = htonl(0x80000000 + XLM_EXEC_RETURN_PROC);       // lwz  r0,XLM_EXEC_RETURN_PROC
1115		*lp++ = htonl(0x4bf705f4);                                                      // b    0x36f800
1116	+	*lp++ = htonl(0x00dead00);                                                      // Let SheepShaver crash, since
1117	+	*lp++ = htonl(0x00beef00);                                                      // no native opcode is available
1118		for (int i=0; i<OP_MAX; i++) {
1119		*lp++ = htonl(0x38a00000 + i);                          // li   r5,OP_*
1120	<	*lp++ = htonl(0x4bf705f4 - i*8);                        // b    0x36f808
1120	>	*lp++ = htonl(0x4bf705ec - i*8);                        // b    0x36f808
1121		}
1122
1123		// Extra routines for EMUL_RETURN/EXEC_RETURN/EMUL_OP
#	Line 938 | Line 1133 | static bool patch_68k_emul(void)
1133		// Extra routine for 68k emulator start
1134		lp = (uint32 *)(ROM_BASE + 0x36f900);
1135		*lp++ = htonl(0x7c2903a6);                                      // mtctr        r1
1136	+	#if EMULATED_PPC
1137	+	*lp++ = htonl(NativeOpcode(NATIVE_DISABLE_INTERRUPT));
1138	+	#else
1139		*lp++ = htonl(0x80200000 + XLM_IRQ_NEST);       // lwz          r1,XLM_IRQ_NEST
1140		*lp++ = htonl(0x38210001);                                      // addi         r1,r1,1
1141		*lp++ = htonl(0x90200000 + XLM_IRQ_NEST);       // stw          r1,XLM_IRQ_NEST
1142	+	#endif
1143		*lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz              r1,XLM_KERNEL_DATA
1144		*lp++ = htonl(0x90c10018);                                      // stw          r6,0x18(r1)
1145		*lp++ = htonl(0x7cc902a6);                                      // mfctr        r6
#	Line 968 | Line 1167 | static bool patch_68k_emul(void)
1167		// Extra routine for Mixed Mode
1168		lp = (uint32 *)(ROM_BASE + 0x36fa00);
1169		*lp++ = htonl(0x7c2903a6);                                      // mtctr        r1
1170	+	#if EMULATED_PPC
1171	+	*lp++ = htonl(NativeOpcode(NATIVE_DISABLE_INTERRUPT));
1172	+	#else
1173		*lp++ = htonl(0x80200000 + XLM_IRQ_NEST);       // lwz          r1,XLM_IRQ_NEST
1174		*lp++ = htonl(0x38210001);                                      // addi         r1,r1,1
1175		*lp++ = htonl(0x90200000 + XLM_IRQ_NEST);       // stw          r1,XLM_IRQ_NEST
1176	+	#endif
1177		*lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz              r1,XLM_KERNEL_DATA
1178		*lp++ = htonl(0x90c10018);                                      // stw          r6,0x18(r1)
1179		*lp++ = htonl(0x7cc902a6);                                      // mfctr        r6
#	Line 996 | Line 1199 | static bool patch_68k_emul(void)
1199		*lp = htonl(0x4e800020);                                        // blr
1200
1201		// Extra routine for Reset/FC1E opcode
1202	<	lp = (uint32 *)(ROM_BASE + 0x36fc00);
1202	>	lp = (uint32 *)(ROM_BASE + 0x36fb00);
1203		*lp++ = htonl(0x7c2903a6);                                      // mtctr        r1
1204	+	#if EMULATED_PPC
1205	+	*lp++ = htonl(NativeOpcode(NATIVE_DISABLE_INTERRUPT));
1206	+	#else
1207		*lp++ = htonl(0x80200000 + XLM_IRQ_NEST);       // lwz          r1,XLM_IRQ_NEST
1208		*lp++ = htonl(0x38210001);                                      // addi         r1,r1,1
1209		*lp++ = htonl(0x90200000 + XLM_IRQ_NEST);       // stw          r1,XLM_IRQ_NEST
1210	+	#endif
1211		*lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz              r1,XLM_KERNEL_DATA
1212		*lp++ = htonl(0x90c10018);                                      // stw          r6,0x18(r1)
1213		*lp++ = htonl(0x7cc902a6);                                      // mfctr        r6
#	Line 1017 | Line 1224 | static bool patch_68k_emul(void)
1224		*lp++ = htonl(0x80e10660);                                      // lwz          r7,$0660(r1)
1225		*lp++ = htonl(0x7d8802a6);                                      // mflr         r12
1226		*lp++ = htonl(0x50e74001);                                      // rlwimi.      r7,r7,8,$80000000
1227	<	*lp++ = htonl(0x814105f4);                                      // lwz          r10,0x05f8(r1)
1227	>	*lp++ = htonl(0x814105f8);                                      // lwz          r10,0x05f8(r1)
1228		*lp++ = htonl(0x7d4803a6);                                      // mtlr         r10
1229		*lp++ = htonl(0x7d8a6378);                                      // mr           r10,r12
1230		*lp++ = htonl(0x3d600002);                                      // lis          r11,0x0002
#	Line 1028 | Line 1235 | static bool patch_68k_emul(void)
1235		// Extra routine for FE0A opcode (QuickDraw 3D needs this)
1236		lp = (uint32 *)(ROM_BASE + 0x36fc00);
1237		*lp++ = htonl(0x7c2903a6);                                      // mtctr        r1
1238	+	#if EMULATED_PPC
1239	+	*lp++ = htonl(NativeOpcode(NATIVE_DISABLE_INTERRUPT));
1240	+	#else
1241		*lp++ = htonl(0x80200000 + XLM_IRQ_NEST);       // lwz          r1,XLM_IRQ_NEST
1242		*lp++ = htonl(0x38210001);                                      // addi         r1,r1,1
1243		*lp++ = htonl(0x90200000 + XLM_IRQ_NEST);       // stw          r1,XLM_IRQ_NEST
1244	+	#endif
1245		*lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz              r1,XLM_KERNEL_DATA
1246		*lp++ = htonl(0x90c10018);                                      // stw          r6,0x18(r1)
1247		*lp++ = htonl(0x7cc902a6);                                      // mfctr        r6
#	Line 1047 | Line 1258 | static bool patch_68k_emul(void)
1258		*lp++ = htonl(0x80e10660);                                      // lwz          r7,$0660(r1)
1259		*lp++ = htonl(0x7d8802a6);                                      // mflr         r12
1260		*lp++ = htonl(0x50e74001);                                      // rlwimi.      r7,r7,8,$80000000
1261	<	*lp++ = htonl(0x814105f4);                                      // lwz          r10,0x05fc(r1)
1261	>	*lp++ = htonl(0x814105fc);                                      // lwz          r10,0x05fc(r1)
1262		*lp++ = htonl(0x7d4803a6);                                      // mtlr         r10
1263		*lp++ = htonl(0x7d8a6378);                                      // mr           r10,r12
1264		*lp++ = htonl(0x3d600002);                                      // lis          r11,0x0002
#	Line 1083 | Line 1294 | dr_found:
1294		static bool patch_nanokernel(void)
1295		{
1296		uint32 *lp;
1297	+	uint32 base, loc;
1298
1299		// Patch Mixed Mode trap
1300	<	lp = (uint32 *)(ROM_BASE + 0x313c90);   // Don't translate virtual->physical
1301	<	while (ntohl(*lp) != 0x3ba10320) lp++;
1302	<	lp++;
1303	<	*lp++ = htonl(0x7f7fdb78);                                      // mr           r31,r27
1304	<	lp++;
1305	<	*lp = htonl(POWERPC_NOP);
1306	<
1307	<	lp = (uint32 *)(ROM_BASE + 0x313c3c);   // Don't activate PPC exception table
1308	<	while (ntohl(*lp) != 0x39010420) lp++;
1300	>	static const uint8 virt2phys_dat[] = {0x7d, 0x1b, 0x43, 0x78, 0x3b, 0xa1, 0x03, 0x20};
1301	>	if ((base = find_rom_data(0x313000, 0x314000, virt2phys_dat, sizeof(virt2phys_dat))) == 0) return false;
1302	>	D(bug("virt2phys %08lx\n", base + 8));
1303	>	lp = (uint32 *)(ROM_BASE + base + 8);   // Don't translate virtual->physical
1304	>	lp[0] = htonl(0x7f7fdb78);                                      // mr           r31,r27
1305	>	lp[2] = htonl(POWERPC_NOP);
1306	>
1307	>	static const uint8 ppc_excp_tbl_dat[] = {0x39, 0x01, 0x04, 0x20, 0x7d, 0x13, 0x43, 0xa6};
1308	>	if ((base = find_rom_data(0x313000, 0x314000, ppc_excp_tbl_dat, sizeof(ppc_excp_tbl_dat))) == 0) return false;
1309	>	D(bug("ppc_excp_tbl %08lx\n", base));
1310	>	lp = (uint32 *)(ROM_BASE + base);               // Don't activate PPC exception table
1311		*lp++ = htonl(0x39000000 + MODE_NATIVE);        // li   r8,MODE_NATIVE
1312	<	*lp = htonl(0x91000000 + XLM_RUN_MODE); // stw  r8,XLM_RUN_MODE
1312	>	*lp = htonl(0x91000000 + XLM_RUN_MODE);         // stw  r8,XLM_RUN_MODE
1313
1314	<	lp = (uint32 *)(ROM_BASE + 0x312e88);   // Don't modify MSR to turn on FPU
1315	<	while (ntohl(*lp) != 0x556b04e2) lp++;
1316	<	lp -= 4;
1314	>	static const uint8 save_fpu_dat[] = {0x7d, 0x00, 0x00, 0xa6, 0x61, 0x08, 0x20, 0x00, 0x7d, 0x00, 0x01, 0x24};
1315	>	if ((base = find_rom_data(0x310000, 0x314000, save_fpu_dat, sizeof(save_fpu_dat))) == 0) return false;
1316	>	D(bug("save_fpu %08lx\n", base));
1317	>	lp = (uint32 *)(ROM_BASE + base);               // Don't modify MSR to turn on FPU
1318	>	if (ntohl(lp[4]) != 0x556b04e2) return false;
1319	>	loc = ROM_BASE + base;
1320	>	#if 1
1321	>	// FIXME: is that really intended?
1322		*lp++ = htonl(POWERPC_NOP);
1323		lp++;
1324		*lp++ = htonl(POWERPC_NOP);
1325		lp++;
1326		*lp = htonl(POWERPC_NOP);
1327	+	#else
1328	+	lp[0] = htonl(POWERPC_NOP);
1329	+	lp[1] = htonl(POWERPC_NOP);
1330	+	lp[2] = htonl(POWERPC_NOP);
1331	+	lp[3] = htonl(POWERPC_NOP);
1332	+	#endif
1333
1334	<	lp = (uint32 *)(ROM_BASE + 0x312b3c);   // Always save FPU state
1335	<	while (ntohl(*lp) != 0x81010668) lp++;
1336	<	lp--;
1334	>	static const uint8 save_fpu_caller_dat[] = {0x93, 0xa6, 0x01, 0xec, 0x93, 0xc6, 0x01, 0xf4, 0x93, 0xe6, 0x01, 0xfc, 0x40};
1335	>	if ((base = find_rom_data(0x310000, 0x314000, save_fpu_caller_dat, sizeof(save_fpu_caller_dat))) == 0) return false;
1336	>	D(bug("save_fpu_caller %08lx\n", base + 12));
1337	>	if (powerpc_branch_target(ROM_BASE + base + 12) != loc) return false;
1338	>	lp = (uint32 *)(ROM_BASE + base + 12);  // Always save FPU state
1339		*lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff));        // bl   0x00312e88
1340
1341	<	lp = (uint32 *)(ROM_BASE + 0x312b44);   // Don't read DEC
1342	<	while (ntohl(*lp) != 0x7ff602a6) lp++;
1343	<	*lp = htonl(0x3be00000);                                        // li   r31,0
1344	<
1345	<	lp = (uint32 *)(ROM_BASE + 0x312b50);   // Don't write DEC
1119	<	while (ntohl(*lp) != 0x7d1603a6) lp++;
1341	>	static const uint8 mdec_dat[] = {0x7f, 0xf6, 0x02, 0xa6, 0x2c, 0x08, 0x00, 0x00, 0x93, 0xe1, 0x06, 0x68, 0x7d, 0x16, 0x03, 0xa6};
1342	>	if ((base = find_rom_data(0x310000, 0x314000, mdec_dat, sizeof(mdec_dat))) == 0) return false;
1343	>	D(bug("mdec %08lx\n", base));
1344	>	lp = (uint32 *)(ROM_BASE + base);               // Don't modify DEC
1345	>	lp[0] = htonl(0x3be00000);                                      // li   r31,0
1346		#if 1
1347	<	*lp++ = htonl(POWERPC_NOP);
1348	<	*lp = htonl(POWERPC_NOP);
1347	>	lp[3] = htonl(POWERPC_NOP);
1348	>	lp[4] = htonl(POWERPC_NOP);
1349		#else
1350	<	*lp++ = htonl(0x39000040);                                      // li   r8,0x40
1351	<	*lp = htonl(0x990600e4);                                        // stb  r8,0xe4(r6)
1350	>	lp[3] = htonl(0x39000040);                                      // li   r8,0x40
1351	>	lp[4] = htonl(0x990600e4);                                      // stb  r8,0xe4(r6)
1352		#endif
1353
1354	<	lp = (uint32 *)(ROM_BASE + 0x312b9c);   // Always restore FPU state
1355	<	while (ntohl(*lp) != 0x7c00092d) lp++;
1356	<	lp--;
1354	>	static const uint8 restore_fpu_caller_dat[] = {0x81, 0x06, 0x00, 0xf4, 0x81, 0x46, 0x00, 0xfc, 0x7d, 0x09, 0x03, 0xa6, 0x40};
1355	>	if ((base = find_rom_data(0x310000, 0x314000, restore_fpu_caller_dat, sizeof(restore_fpu_caller_dat))) == 0) return false;
1356	>	D(bug("restore_fpu_caller %08lx\n", base + 12));
1357	>	lp = (uint32 *)(ROM_BASE + base + 12);  // Always restore FPU state
1358		*lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff));        // bl   0x00312ddc
1359
1360	<	lp = (uint32 *)(ROM_BASE + 0x312a68);   // Don't activate 68k exception table
1361	<	while (ntohl(*lp) != 0x39010360) lp++;
1360	>	static const uint8 m68k_excp_tbl_dat[] = {0x81, 0x21, 0x06, 0x58, 0x39, 0x01, 0x03, 0x60, 0x7d, 0x13, 0x43, 0xa6};
1361	>	if ((base = find_rom_data(0x310000, 0x314000, m68k_excp_tbl_dat, sizeof(m68k_excp_tbl_dat))) == 0) return false;
1362	>	D(bug("m68k_excp %08lx\n", base + 4));
1363	>	lp = (uint32 *)(ROM_BASE + base + 4);   // Don't activate 68k exception table
1364		*lp++ = htonl(0x39000000 + MODE_68K);           // li   r8,MODE_68K
1365		*lp = htonl(0x91000000 + XLM_RUN_MODE);         // stw  r8,XLM_RUN_MODE
1366
1367		// Patch 68k emulator trap routine
1368	<	lp = (uint32 *)(ROM_BASE + 0x312994);   // Always restore FPU state
1369	<	while (ntohl(*lp) != 0x39260040) lp++;
1370	<	lp--;
1368	>	static const uint8 restore_fpu_caller2_dat[] = {0x81, 0x86, 0x00, 0x8c, 0x80, 0x66, 0x00, 0x94, 0x80, 0x86, 0x00, 0x9c, 0x40};
1369	>	if ((base = find_rom_data(0x310000, 0x314000, restore_fpu_caller2_dat, sizeof(restore_fpu_caller2_dat))) == 0) return false;
1370	>	D(bug("restore_fpu_caller2 %08lx\n", base + 12));
1371	>	loc = powerpc_branch_target(ROM_BASE + base + 12) - ROM_BASE;
1372	>	lp = (uint32 *)(ROM_BASE + base + 12);  // Always restore FPU state
1373		*lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff));        // bl   0x00312dd4
1374
1375	<	lp = (uint32 *)(ROM_BASE + 0x312dd8);   // Don't modify MSR to turn on FPU
1376	<	while (ntohl(*lp) != 0x810600e4) lp++;
1377	<	lp--;
1375	>	static const uint8 restore_fpu_dat[] = {0x55, 0x68, 0x04, 0xa5, 0x4c, 0x82, 0x00, 0x20, 0x81, 0x06, 0x00, 0xe4};
1376	>	if ((base = find_rom_data(0x310000, 0x314000, restore_fpu_dat, sizeof(restore_fpu_dat))) == 0) return false;
1377	>	D(bug("restore_fpu %08lx\n", base));
1378	>	if (base != loc) return false;
1379	>	lp = (uint32 *)(ROM_BASE + base + 4);   // Don't modify MSR to turn on FPU
1380		*lp++ = htonl(POWERPC_NOP);
1381		lp += 2;
1382		*lp++ = htonl(POWERPC_NOP);
#	Line 1153 | Line 1386 | static bool patch_nanokernel(void)
1386		*lp = htonl(POWERPC_NOP);
1387
1388		// Patch trap return routine
1389	<	lp = (uint32 *)(ROM_BASE + 0x312c20);
1390	<	while (ntohl(*lp) != 0x7d5a03a6) lp++;
1389	>	static const uint8 trap_return_dat[] = {0x80, 0xc1, 0x00, 0x18, 0x80, 0x21, 0x00, 0x04, 0x4c, 0x00, 0x00, 0x64};
1390	>	if ((base = find_rom_data(0x312000, 0x320000, trap_return_dat, sizeof(trap_return_dat))) == 0) return false;
1391	>	D(bug("trap_return %08lx\n", base + 8));
1392	>	lp = (uint32 *)(ROM_BASE + base + 8);   // Replace rfi
1393	>	*lp = htonl(POWERPC_BCTR);
1394	>
1395	>	while (ntohl(*lp) != 0x7d5a03a6) lp--;
1396		*lp++ = htonl(0x7d4903a6);                                      // mtctr        r10
1397		*lp++ = htonl(0x7daff120);                                      // mtcr r13
1398	<	*lp = htonl(0x48000000 + 0x8000 - (((uint32)lp - ROM_BASE) & 0xffff));  // b            ROM_BASE+0x318000
1399	<	uint32 xlp = ((uint32)(lp+1) - ROM_BASE) & 0xffff;
1162	<
1163	<	lp = (uint32 *)(ROM_BASE + 0x312c50);   // Replace rfi
1164	<	while (ntohl(*lp) != 0x4c000064) lp++;
1165	<	*lp = htonl(POWERPC_BCTR);
1398	>	*lp = htonl(0x48000000 + ((0x318000 - ((uint32)lp - ROM_BASE)) & 0x03fffffc));  // b            ROM_BASE+0x318000
1399	>	uint32 npc = (uint32)(lp + 1) - ROM_BASE;
1400
1401		lp = (uint32 *)(ROM_BASE + 0x318000);
1402	+	#if EMULATED_PPC
1403	+	*lp++ = htonl(NativeOpcode(NATIVE_ENABLE_INTERRUPT));
1404	+	*lp = htonl(0x48000000 + ((npc - 0x318004) & 0x03fffffc));      // b            ROM_BASE+0x312c2c
1405	+	#else
1406		*lp++ = htonl(0x81400000 + XLM_IRQ_NEST);       // lwz  r10,XLM_IRQ_NEST
1407		*lp++ = htonl(0x394affff);                                      // subi r10,r10,1
1408		*lp++ = htonl(0x91400000 + XLM_IRQ_NEST);       // stw  r10,XLM_IRQ_NEST
1409	<	*lp = htonl(0x48000000 + ((xlp - 0x800c) & 0x03fffffc));        // b            ROM_BASE+0x312c2c
1409	>	*lp = htonl(0x48000000 + ((npc - 0x31800c) & 0x03fffffc));      // b            ROM_BASE+0x312c2c
1410	>	#endif
1411	>
1412		/*
1413		// Disable FE0A/FE06 opcodes
1414		lp = (uint32 *)(ROM_BASE + 0x3144ac);
#	Line 1188 | Line 1428 | static bool patch_68k(void)
1428		uint32 *lp;
1429		uint16 *wp;
1430		uint8 *bp;
1431	<	uint32 base;
1431	>	uint32 base, loc;
1432
1433		// Remove 68k RESET instruction
1434		static const uint8 reset_dat[] = {0x4e, 0x70};
#	Line 1214 | Line 1454 | static bool patch_68k(void)
1454		// Patch UniversalInfo
1455		if (ROMType == ROMTYPE_NEWWORLD) {
1456		static const uint8 univ_info_dat[] = {0x3f, 0xff, 0x04, 0x00};
1457	<	if ((base = find_rom_data(0x14000, 0x16000, univ_info_dat, sizeof(univ_info_dat))) == 0) return false;
1457	>	if ((base = find_rom_data(0x14000, 0x18000, univ_info_dat, sizeof(univ_info_dat))) == 0) return false;
1458		D(bug("universal_info %08lx\n", base));
1459		lp = (uint32 *)(ROM_BASE + base - 0x14);
1460		lp[0x00 >> 2] = htonl(ADDR_MAP_PATCH_SPACE - (base - 0x14));
#	Line 1238 | Line 1478 | static bool patch_68k(void)
1478		lp[0x28 >> 2] = htonl(0x00000861);
1479		lp[0x58 >> 2] = htonl(0x30200000);
1480		lp[0x60 >> 2] = htonl(0x0000003d);
1481	+	} else if (ROMType == ROMTYPE_GOSSAMER) {
1482	+	base = 0x12d20;
1483	+	lp = (uint32 *)(ROM_BASE + base - 0x14);
1484	+	lp[0x00 >> 2] = htonl(ADDR_MAP_PATCH_SPACE - (base - 0x14));
1485	+	lp[0x10 >> 2] = htonl(0xcc003d11);              // Make it like the PowerMac 9500 UniversalInfo
1486	+	lp[0x14 >> 2] = htonl(0x3fff0401);
1487	+	lp[0x18 >> 2] = htonl(0x0300001c);
1488	+	lp[0x1c >> 2] = htonl(0x000108c4);
1489	+	lp[0x24 >> 2] = htonl(0xc301bf26);
1490	+	lp[0x28 >> 2] = htonl(0x00000861);
1491	+	lp[0x58 >> 2] = htonl(0x30410000);
1492	+	lp[0x60 >> 2] = htonl(0x0000003d);
1493		}
1494
1495		// Construct AddrMap for NewWorld ROM
1496	<	if (ROMType == ROMTYPE_NEWWORLD || ROMType == ROMTYPE_ZANZIBAR) {
1496	>	if (ROMType == ROMTYPE_NEWWORLD || ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_GOSSAMER) {
1497		lp = (uint32 *)(ROM_BASE + ADDR_MAP_PATCH_SPACE);
1498		memset(lp - 10, 0, 0x128);
1499		lp[-10] = htonl(0x0300001c);
#	Line 1367 | Line 1619 | static bool patch_68k(void)
1619		*wp++ = htons(M68K_EMUL_OP_XPRAM2);
1620		*wp = htons(0x4ed3);                    // jmp  (a3)
1621
1622	<	static const uint32 nvram3_loc[] = {0x582f0, 0xa0a0, 0x7e50, 0xa1d0, 0};
1623	<	wp = (uint16 *)(ROM_BASE + nvram3_loc[ROMType]);
1622	>	static const uint8 nvram3_dat[] = {0x4e, 0xd3, 0x06, 0x41, 0x13, 0x00};
1623	>	if ((base = find_rom_data(0x7000, 0xb000, nvram3_dat, sizeof(nvram3_dat))) == 0) return false;
1624	>	D(bug("nvram3 %08lx\n", base));
1625	>	wp = (uint16 *)(ROM_BASE + base + 2);
1626	>	*wp++ = htons(M68K_EMUL_OP_XPRAM3);
1627	>	*wp = htons(0x4ed3);                    // jmp  (a3)
1628	>
1629	>	static const uint32 nvram4_loc[] = {0x582f0, 0xa0a0, 0x7e50, 0xa1d0, 0x538d0, 0};
1630	>	wp = (uint16 *)(ROM_BASE + nvram4_loc[ROMType]);
1631		*wp++ = htons(0x202f);                  // move.l       4(sp),d0
1632		*wp++ = htons(0x0004);
1633		*wp++ = htons(M68K_EMUL_OP_NVRAM1);
#	Line 1381 | Line 1640 | static bool patch_68k(void)
1640		*wp = htons(0x0004);
1641		}
1642
1643	<	static const uint32 nvram4_loc[] = {0x58460, 0xa0f0, 0x7f40, 0xa220, 0};
1644	<	wp = (uint16 *)(ROM_BASE + nvram4_loc[ROMType]);
1643	>	static const uint32 nvram5_loc[] = {0x58460, 0xa0f0, 0x7f40, 0xa220, 0x53a20, 0};
1644	>	wp = (uint16 *)(ROM_BASE + nvram5_loc[ROMType]);
1645		if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_GAZELLE) {
1646		*wp++ = htons(0x202f);                  // move.l       4(sp),d0
1647		*wp++ = htons(0x0004);
#	Line 1410 | Line 1669 | static bool patch_68k(void)
1669		*wp = htons(M68K_NOP);
1670
1671		// Don't initialize SCC (via 0x1ac)
1672	<	static const uint8 scc_init_dat[] = {0x48, 0xe7, 0x38, 0xfe};
1673	<	if ((base = find_rom_data(0x190, 0x1f0, scc_init_dat, sizeof(scc_init_dat))) == 0) return false;
1672	>	static const uint8 scc_init_caller_dat[] = {0x21, 0xce, 0x01, 0x08, 0x22, 0x78, 0x0d, 0xd8};
1673	>	if ((base = find_rom_data(0x180, 0x1f0, scc_init_caller_dat, sizeof(scc_init_caller_dat))) == 0) return false;
1674	>	D(bug("scc_init_caller %08lx\n", base + 12));
1675	>	wp = (uint16 *)(ROM_BASE + base + 12);
1676	>	loc = ntohs(wp[1]) + ((uintptr)wp - ROM_BASE) + 2;
1677	>	static const uint8 scc_init_dat[] = {0x20, 0x78, 0x01, 0xdc, 0x22, 0x78, 0x01, 0xd8};
1678	>	if ((base = find_rom_data(loc, loc + 0x80, scc_init_dat, sizeof(scc_init_dat))) == 0) return false;
1679		D(bug("scc_init %08lx\n", base));
1680	<	wp = (uint16 *)(ROM_BASE + base - 2);
1417	<	wp = (uint16 *)(ROM_BASE + ntohs(*wp) + base - 2);
1680	>	wp = (uint16 *)(ROM_BASE + base);
1681		*wp++ = htons(M68K_EMUL_OP_RESET);
1682		*wp = htons(M68K_RTS);
1683
#	Line 1559 | Line 1822 | static bool patch_68k(void)
1822		if ((base = find_rom_data(0x13000, 0x20000, gc_mask2_dat, sizeof(gc_mask2_dat))) == 0) return false;
1823		D(bug("gc_mask2 %08lx\n", base));
1824		wp = (uint16 *)(ROM_BASE + base);
1825	+	if (ROMType == ROMTYPE_GOSSAMER)
1826	+	*wp++ = htons(M68K_NOP);
1827		for (int i=0; i<5; i++) {
1828		*wp++ = htons(M68K_NOP);
1829		*wp++ = htons(M68K_NOP);
#	Line 1566 | Line 1831 | static bool patch_68k(void)
1831		*wp++ = htons(M68K_NOP);
1832		wp += 2;
1833		}
1834	<	if (ROMType == ROMTYPE_ZANZIBAR) {
1834	>	if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_GOSSAMER) {
1835		for (int i=0; i<6; i++) {
1836		*wp++ = htons(M68K_NOP);
1837		*wp++ = htons(M68K_NOP);
#	Line 1592 | Line 1857 | static bool patch_68k(void)
1857
1858		// Patch GetCPUSpeed (via 0x27a) (some ROMs have two of them)
1859		static const uint8 cpu_speed_dat[] = {0x20, 0x30, 0x81, 0xf2, 0x5f, 0xff, 0xef, 0xd8, 0x00, 0x04, 0x4c, 0x7c};
1860	<	if ((base = find_rom_data(0x6000, 0x9000, cpu_speed_dat, sizeof(cpu_speed_dat))) == 0) return false;
1860	>	if ((base = find_rom_data(0x6000, 0xa000, cpu_speed_dat, sizeof(cpu_speed_dat))) == 0) return false;
1861		D(bug("cpu_speed %08lx\n", base));
1862		wp = (uint16 *)(ROM_BASE + base);
1863		*wp++ = htons(0x203c);                  // move.l       #(MHz<<16)|MHz,d0
1864		*wp++ = htons(CPUClockSpeed / 1000000);
1865		*wp++ = htons(CPUClockSpeed / 1000000);
1866		*wp = htons(M68K_RTS);
1867	<	if ((base = find_rom_data(base, 0x9000, cpu_speed_dat, sizeof(cpu_speed_dat))) != 0) {
1867	>	if ((base = find_rom_data(base, 0xa000, cpu_speed_dat, sizeof(cpu_speed_dat))) != 0) {
1868		D(bug("cpu_speed2 %08lx\n", base));
1869		wp = (uint16 *)(ROM_BASE + base);
1870		*wp++ = htons(0x203c);                  // move.l       #(MHz<<16)|MHz,d0
#	Line 1639 | Line 1904 | static bool patch_68k(void)
1904		*wp = htons(M68K_RTS);
1905
1906		// Don't install Time Manager task for 60Hz interrupt (Enable60HzInts, via 0x2b8)
1907	<	if (ROMType == ROMTYPE_NEWWORLD) {
1907	>	if (ROMType == ROMTYPE_NEWWORLD || ROMType == ROMTYPE_GOSSAMER) {
1908		static const uint8 tm_task_dat[] = {0x30, 0x3c, 0x4e, 0x2b, 0xa9, 0xc9};
1909	<	if ((base = find_rom_data(0x2e0, 0x320, tm_task_dat, sizeof(tm_task_dat))) == 0) return false;
1909	>	if ((base = find_rom_data(0x2a0, 0x320, tm_task_dat, sizeof(tm_task_dat))) == 0) return false;
1910		D(bug("tm_task %08lx\n", base));
1911		wp = (uint16 *)(ROM_BASE + base + 28);
1912		*wp++ = htons(M68K_NOP);
#	Line 1661 | Line 1926 | static bool patch_68k(void)
1926		}
1927
1928		// Don't read PVR from 0x5fffef80 in DriverServicesLib (via 0x316)
1929	<	if (ROMType != ROMTYPE_NEWWORLD) {
1929	>	if (ROMType != ROMTYPE_NEWWORLD && ROMType != ROMTYPE_GOSSAMER) {
1930		uint32 dsl_offset = find_rom_resource(FOURCC('n','l','i','b'), -16401);
1931		if (ROMType == ROMTYPE_ZANZIBAR) {
1932		static const uint8 dsl_pvr_dat[] = {0x40, 0x82, 0x00, 0x40, 0x38, 0x60, 0xef, 0x80, 0x3c, 0x63, 0x60, 0x00, 0x80, 0x83, 0x00, 0x00, 0x54, 0x84, 0x84, 0x3e};
#	Line 1696 | Line 1961 | static bool patch_68k(void)
1961		*lp = htonl(0x38600000);                // li   r3,0
1962		}
1963
1964	+	// FIXME: Fake reading from [HpChk]+4 (the callchain reports some function from DriverServicesLib)
1965	+	if (1) {
1966	+	uint32 hpchk_offset = find_rom_resource(FOURCC('n','l','i','b'), 10);
1967	+	static const uint8 hpchk_dat[] = {0x80, 0x80, 0x03, 0x16, 0x94, 0x21, 0xff, 0xb0, 0x83, 0xc4, 0x00, 0x04};
1968	+	if ((base = find_rom_data(hpchk_offset, hpchk_offset + 0x3000, hpchk_dat, sizeof(hpchk_dat))) == 0) return false;
1969	+	D(bug("hpchk %08lx\n", base));
1970	+	lp = (uint32 *)(ROM_BASE + base);
1971	+	*lp = htonl(0x80800000 + XLM_ZERO_PAGE);                // lwz  r4,(zero page)
1972	+	}
1973	+
1974		// Patch Name Registry
1975		static const uint8 name_reg_dat[] = {0x70, 0xff, 0xab, 0xeb};
1976		if ((base = find_rom_data(0x300, 0x380, name_reg_dat, sizeof(name_reg_dat))) == 0) return false;
#	Line 1747 | Line 2022 | static bool patch_68k(void)
2022		D(bug("scsi_var2 %08lx\n", base));
2023		wp = (uint16 *)(ROM_BASE + base);
2024		*wp++ = htons(0x7000);  // moveq #0,d0
2025	<	*wp = htons(M68K_RTS);  // bra
2025	>	*wp = htons(M68K_RTS);
2026	>	}
2027	>	}
2028	>	else if (ROMType == ROMTYPE_GOSSAMER) {
2029	>	static const uint8 scsi_var_dat[] = {0x70, 0x01, 0xa0, 0x89, 0x4a, 0x6e, 0xfe, 0xac, 0x4f, 0xef, 0x00, 0x10, 0x66, 0x00};
2030	>	if ((base = find_rom_data(0x1d700, 0x1d800, scsi_var_dat, sizeof(scsi_var_dat))) != 0) {
2031	>	D(bug("scsi_var %08lx\n", base));
2032	>	wp = (uint16 *)(ROM_BASE + base + 12);
2033	>	*wp = htons(0x6000);    // bra
2034	>	}
2035	>
2036	>	static const uint8 scsi_var2_dat[] = {0x4e, 0x56, 0xfc, 0x5a, 0x48, 0xe7, 0x1f, 0x38};
2037	>	if ((base = find_rom_data(0x1d900, 0x1da00, scsi_var2_dat, sizeof(scsi_var2_dat))) != 0) {
2038	>	D(bug("scsi_var2 %08lx\n", base));
2039	>	wp = (uint16 *)(ROM_BASE + base);
2040	>	*wp++ = htons(0x7000);  // moveq #0,d0
2041	>	*wp = htons(M68K_RTS);
2042		}
2043		}
2044		#endif
#	Line 1803 | Line 2094 | static bool patch_68k(void)
2094		memcpy((void *)(ROM_BASE + sony_offset + 0x200), cdrom_driver, sizeof(cdrom_driver));
2095
2096		// Install serial drivers
2097	<	memcpy((void *)(ROM_BASE + sony_offset + 0x300), ain_driver, sizeof(ain_driver));
2098	<	memcpy((void *)(ROM_BASE + sony_offset + 0x400), aout_driver, sizeof(aout_driver));
2099	<	memcpy((void *)(ROM_BASE + sony_offset + 0x500), bin_driver, sizeof(bin_driver));
2100	<	memcpy((void *)(ROM_BASE + sony_offset + 0x600), bout_driver, sizeof(bout_driver));
2097	>	gen_ain_driver( ROM_BASE + sony_offset + 0x300);
2098	>	gen_aout_driver(ROM_BASE + sony_offset + 0x400);
2099	>	gen_bin_driver( ROM_BASE + sony_offset + 0x500);
2100	>	gen_bout_driver(ROM_BASE + sony_offset + 0x600);
2101
2102		// Copy icons to ROM
2103		SonyDiskIconAddr = ROM_BASE + sony_offset + 0x800;
#	Line 1827 | Line 2118 | static bool patch_68k(void)
2118		*wp = htons(M68K_RTS);
2119
2120		// Don't install serial drivers from ROM
2121	<	if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_NEWWORLD) {
2121	>	if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_NEWWORLD || ROMType == ROMTYPE_GOSSAMER) {
2122		wp = (uint16 *)(ROM_BASE + find_rom_resource(FOURCC('S','E','R','D'), 0));
2123		*wp = htons(M68K_RTS);
2124		} else {
#	Line 1886 | Line 2177 | static bool patch_68k(void)
2177		wp = (uint16 *)(ROM_BASE + base);
2178		if (ROMType == ROMTYPE_ZANZIBAR)
2179		*wp = htons(M68K_RTS);
2180	<	else
2180	>	else if (ntohs(wp[-4]) == 0x61ff)
2181	>	*wp = htons(M68K_RTS);
2182	>	else if (ntohs(wp[-2]) == 0x6700)
2183		wp[-2] = htons(0x6000); // bra
2184
2185		// Patch PowerOff()
#	Line 1916 | Line 2209 | static bool patch_68k(void)
2209
2210		if (ROMType == ROMTYPE_NEWWORLD) {
2211		static const uint8 via_int3_dat[] = {0x48, 0xe7, 0xf0, 0xf0, 0x76, 0x01, 0x60, 0x26};
2212	<	if ((base = find_rom_data(0x15000, 0x18000, via_int3_dat, sizeof(via_int3_dat))) == 0) return false;
2212	>	if ((base = find_rom_data(0x15000, 0x19000, via_int3_dat, sizeof(via_int3_dat))) == 0) return false;
2213		D(bug("via_int3 %08lx\n", base));
2214		wp = (uint16 *)(ROM_BASE + base);       // CHRP level 1 handler
2215		*wp++ = htons(M68K_JMP);
#	Line 2006 | Line 2299 | void InstallDrivers(void)
2299		{
2300		D(bug("Installing drivers...\n"));
2301		M68kRegisters r;
2302	<	uint8 pb[SIZEOF_IOParam];
2302	>	SheepArray<SIZEOF_IOParam> pb_var;
2303	>	const uintptr pb = pb_var.addr();
2304	>
2305	>	// Install floppy driver
2306	>	if (ROMType == ROMTYPE_NEWWORLD || ROMType == ROMTYPE_GOSSAMER) {
2307	>
2308	>	// Force installation of floppy driver with NewWorld and Gossamer ROMs
2309	>	r.a[0] = ROM_BASE + sony_offset;
2310	>	r.d[0] = (uint32)SonyRefNum;
2311	>	Execute68kTrap(0xa43d, &r);             // DrvrInstallRsrvMem()
2312	>	r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~SonyRefNum * 4);   // Get driver handle from Unit Table
2313	>	Execute68kTrap(0xa029, &r);             // HLock()
2314	>	uint32 dce = ReadMacInt32(r.a[0]);
2315	>	WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset);
2316	>	WriteMacInt16(dce + dCtlFlags, SonyDriverFlags);
2317	>	}
2318	>
2319	>	#if DISABLE_SCSI && 0
2320	>	// Fake SCSIGlobals
2321	>	WriteMacInt32(0xc0c, SheepMem::ZeroPage());
2322	>	#endif
2323
2324		// Open .Sony driver
2325	<	WriteMacInt8((uint32)pb + ioPermssn, 0);
2326	<	WriteMacInt32((uint32)pb + ioNamePtr, (uint32)"\005.Sony");
2327	<	r.a[0] = (uint32)pb;
2325	>	SheepString sony_str("\005.Sony");
2326	>	WriteMacInt8(pb + ioPermssn, 0);
2327	>	WriteMacInt32(pb + ioNamePtr, sony_str.addr());
2328	>	r.a[0] = pb;
2329		Execute68kTrap(0xa000, &r);             // Open()
2330
2331		// Install disk driver
#	Line 2025 | Line 2339 | void InstallDrivers(void)
2339		WriteMacInt16(dce + dCtlFlags, DiskDriverFlags);
2340
2341		// Open disk driver
2342	<	WriteMacInt32((uint32)pb + ioNamePtr, (uint32)"\005.Disk");
2343	<	r.a[0] = (uint32)pb;
2342	>	SheepString disk_str("\005.Disk");
2343	>	WriteMacInt32(pb + ioNamePtr, disk_str.addr());
2344	>	r.a[0] = pb;
2345		Execute68kTrap(0xa000, &r);             // Open()
2346
2347		// Install CD-ROM driver unless nocdrom option given
#	Line 2043 | Line 2358 | void InstallDrivers(void)
2358		WriteMacInt16(dce + dCtlFlags, CDROMDriverFlags);
2359
2360		// Open CD-ROM driver
2361	<	WriteMacInt32((uint32)pb + ioNamePtr, (uint32)"\010.AppleCD");
2362	<	r.a[0] = (uint32)pb;
2361	>	SheepString apple_cd("\010.AppleCD");
2362	>	WriteMacInt32(pb + ioNamePtr, apple_cd.addr());
2363	>	r.a[0] = pb;
2364		Execute68kTrap(0xa000, &r);             // Open()
2365		}
2366

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