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root/cebix/SheepShaver/src/rom_patches.cpp
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Comparing SheepShaver/src/rom_patches.cpp (file contents):
Revision 1.21 by gbeauche, 2003-12-15T15:23:59Z vs.
Revision 1.25 by gbeauche, 2004-01-31T11:10:48Z

# Line 1 | Line 1
1   /*
2   *  rom_patches.cpp - ROM patches
3   *
4 < *  SheepShaver (C) 1997-2002 Christian Bauer and Marc Hellwig
4 > *  SheepShaver (C) 1997-2004 Christian Bauer and Marc Hellwig
5   *
6   *  This program is free software; you can redistribute it and/or modify
7   *  it under the terms of the GNU General Public License as published by
# Line 319 | Line 319 | static bool check_rom_patch_space(uint32
319          size = (size + 3) & -4;
320          for (int i = 0; i < size; i += 4) {
321                  uint32 x = ntohl(*(uint32 *)(ROM_BASE + base + i));
322 –                printf("%08x\n", x);
322                  if (x != 0x6b636b63 && x != 0)
323                          return false;
324          }
# Line 907 | Line 906 | static bool patch_nanokernel_boot(void)
906                          lp[7] = htonl(0x00080008);      // Inst cache assoc/Data cache assoc
907                          lp[8] = htonl(0x00800004);      // TLB total size/TLB assoc
908                          break;
909 +                case 0x8000:    // 7400
910 +                case 0x800c:    // 7410
911 +                        lp[0] = htonl(0x1000);          // Page size
912 +                        lp[1] = htonl(0x8000);          // Data cache size
913 +                        lp[2] = htonl(0x8000);          // Inst cache size
914 +                        lp[3] = htonl(0x00200020);      // Coherency block size/Reservation granule size
915 +                        lp[4] = htonl(0x00000020);      // Unified caches/Inst cache line size
916 +                        lp[5] = htonl(0x00200020);      // Data cache line size/Data cache block size touch
917 +                        lp[6] = htonl(0x00200020);      // Inst cache block size/Data cache block size
918 +                        lp[7] = htonl(0x00080008);      // Inst cache assoc/Data cache assoc
919 +                        lp[8] = htonl(0x00800002);      // TLB total size/TLB assoc
920 +                        break;
921                  default:
922                          printf("WARNING: Unknown CPU type\n");
923                          break;
# Line 1664 | Line 1675 | static bool patch_68k(void)
1675          wp = (uint16 *)(ROM_BASE + base + 12);
1676          loc = ntohs(wp[1]) + ((uintptr)wp - ROM_BASE) + 2;
1677          static const uint8 scc_init_dat[] = {0x20, 0x78, 0x01, 0xdc, 0x22, 0x78, 0x01, 0xd8};
1678 <        if ((base = find_rom_data(loc, loc + 0x80, scc_init_dat, sizeof(scc_init_dat))) != loc) return false;
1678 >        if ((base = find_rom_data(loc, loc + 0x80, scc_init_dat, sizeof(scc_init_dat))) == 0) return false;
1679          D(bug("scc_init %08lx\n", base));
1680          wp = (uint16 *)(ROM_BASE + base);
1681          *wp++ = htons(M68K_EMUL_OP_RESET);

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