847 |
|
lp[7] = htonl(0x00040004); // Inst cache assoc/Data cache assoc |
848 |
|
lp[8] = htonl(0x00400002); // TLB total size/TLB assoc |
849 |
|
break; |
850 |
< |
case 8: // 750 |
850 |
> |
case 8: // 750, 750FX |
851 |
> |
case 0x7000: |
852 |
|
lp[0] = htonl(0x1000); // Page size |
853 |
|
lp[1] = htonl(0x8000); // Data cache size |
854 |
|
lp[2] = htonl(0x8000); // Inst cache size |
872 |
|
lp[8] = htonl(0x00800002); // TLB total size/TLB assoc |
873 |
|
break; |
874 |
|
// case 11: // X704? |
875 |
< |
case 12: // 7400, 7410 |
875 |
> |
case 12: // 7400, 7410, 7450, 7455, 7457 |
876 |
|
case 0x800c: |
877 |
+ |
case 0x8000: |
878 |
+ |
case 0x8001: |
879 |
+ |
case 0x8002: |
880 |
|
lp[0] = htonl(0x1000); // Page size |
881 |
|
lp[1] = htonl(0x8000); // Data cache size |
882 |
|
lp[2] = htonl(0x8000); // Inst cache size |
911 |
|
lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc |
912 |
|
lp[8] = htonl(0x00800004); // TLB total size/TLB assoc |
913 |
|
break; |
914 |
+ |
case 0x39: // 970 |
915 |
+ |
lp[0] = htonl(0x1000); // Page size |
916 |
+ |
lp[1] = htonl(0x8000); // Data cache size |
917 |
+ |
lp[2] = htonl(0x10000); // Inst cache size |
918 |
+ |
lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size |
919 |
+ |
lp[4] = htonl(0x00010020); // Unified caches/Inst cache line size |
920 |
+ |
lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch |
921 |
+ |
lp[6] = htonl(0x00800080); // Inst cache block size/Data cache block size |
922 |
+ |
lp[7] = htonl(0x00020002); // Inst cache assoc/Data cache assoc |
923 |
+ |
lp[8] = htonl(0x02000004); // TLB total size/TLB assoc |
924 |
+ |
break; |
925 |
|
default: |
926 |
|
printf("WARNING: Unknown CPU type\n"); |
927 |
|
break; |
1137 |
|
// Extra routine for 68k emulator start |
1138 |
|
lp = (uint32 *)(ROM_BASE + 0x36f900); |
1139 |
|
*lp++ = htonl(0x7c2903a6); // mtctr r1 |
1125 |
– |
#if EMULATED_PPC |
1126 |
– |
*lp++ = htonl(NativeOpcode(NATIVE_DISABLE_INTERRUPT)); |
1127 |
– |
#else |
1140 |
|
*lp++ = htonl(0x80200000 + XLM_IRQ_NEST); // lwz r1,XLM_IRQ_NEST |
1141 |
|
*lp++ = htonl(0x38210001); // addi r1,r1,1 |
1142 |
|
*lp++ = htonl(0x90200000 + XLM_IRQ_NEST); // stw r1,XLM_IRQ_NEST |
1131 |
– |
#endif |
1143 |
|
*lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz r1,XLM_KERNEL_DATA |
1144 |
|
*lp++ = htonl(0x90c10018); // stw r6,0x18(r1) |
1145 |
|
*lp++ = htonl(0x7cc902a6); // mfctr r6 |
1167 |
|
// Extra routine for Mixed Mode |
1168 |
|
lp = (uint32 *)(ROM_BASE + 0x36fa00); |
1169 |
|
*lp++ = htonl(0x7c2903a6); // mtctr r1 |
1159 |
– |
#if EMULATED_PPC |
1160 |
– |
*lp++ = htonl(NativeOpcode(NATIVE_DISABLE_INTERRUPT)); |
1161 |
– |
#else |
1170 |
|
*lp++ = htonl(0x80200000 + XLM_IRQ_NEST); // lwz r1,XLM_IRQ_NEST |
1171 |
|
*lp++ = htonl(0x38210001); // addi r1,r1,1 |
1172 |
|
*lp++ = htonl(0x90200000 + XLM_IRQ_NEST); // stw r1,XLM_IRQ_NEST |
1165 |
– |
#endif |
1173 |
|
*lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz r1,XLM_KERNEL_DATA |
1174 |
|
*lp++ = htonl(0x90c10018); // stw r6,0x18(r1) |
1175 |
|
*lp++ = htonl(0x7cc902a6); // mfctr r6 |
1197 |
|
// Extra routine for Reset/FC1E opcode |
1198 |
|
lp = (uint32 *)(ROM_BASE + 0x36fb00); |
1199 |
|
*lp++ = htonl(0x7c2903a6); // mtctr r1 |
1193 |
– |
#if EMULATED_PPC |
1194 |
– |
*lp++ = htonl(NativeOpcode(NATIVE_DISABLE_INTERRUPT)); |
1195 |
– |
#else |
1200 |
|
*lp++ = htonl(0x80200000 + XLM_IRQ_NEST); // lwz r1,XLM_IRQ_NEST |
1201 |
|
*lp++ = htonl(0x38210001); // addi r1,r1,1 |
1202 |
|
*lp++ = htonl(0x90200000 + XLM_IRQ_NEST); // stw r1,XLM_IRQ_NEST |
1199 |
– |
#endif |
1203 |
|
*lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz r1,XLM_KERNEL_DATA |
1204 |
|
*lp++ = htonl(0x90c10018); // stw r6,0x18(r1) |
1205 |
|
*lp++ = htonl(0x7cc902a6); // mfctr r6 |
1227 |
|
// Extra routine for FE0A opcode (QuickDraw 3D needs this) |
1228 |
|
lp = (uint32 *)(ROM_BASE + 0x36fc00); |
1229 |
|
*lp++ = htonl(0x7c2903a6); // mtctr r1 |
1227 |
– |
#if EMULATED_PPC |
1228 |
– |
*lp++ = htonl(NativeOpcode(NATIVE_DISABLE_INTERRUPT)); |
1229 |
– |
#else |
1230 |
|
*lp++ = htonl(0x80200000 + XLM_IRQ_NEST); // lwz r1,XLM_IRQ_NEST |
1231 |
|
*lp++ = htonl(0x38210001); // addi r1,r1,1 |
1232 |
|
*lp++ = htonl(0x90200000 + XLM_IRQ_NEST); // stw r1,XLM_IRQ_NEST |
1233 |
– |
#endif |
1233 |
|
*lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz r1,XLM_KERNEL_DATA |
1234 |
|
*lp++ = htonl(0x90c10018); // stw r6,0x18(r1) |
1235 |
|
*lp++ = htonl(0x7cc902a6); // mfctr r6 |
1396 |
|
uint32 npc = (uint32)(lp + 1) - ROM_BASE; |
1397 |
|
|
1398 |
|
lp = (uint32 *)(ROM_BASE + 0x318000); |
1400 |
– |
#if EMULATED_PPC |
1401 |
– |
*lp++ = htonl(NativeOpcode(NATIVE_ENABLE_INTERRUPT)); |
1402 |
– |
*lp = htonl(0x48000000 + ((npc - 0x318004) & 0x03fffffc)); // b ROM_BASE+0x312c2c |
1403 |
– |
#else |
1399 |
|
*lp++ = htonl(0x81400000 + XLM_IRQ_NEST); // lwz r10,XLM_IRQ_NEST |
1400 |
|
*lp++ = htonl(0x394affff); // subi r10,r10,1 |
1401 |
|
*lp++ = htonl(0x91400000 + XLM_IRQ_NEST); // stw r10,XLM_IRQ_NEST |
1402 |
|
*lp = htonl(0x48000000 + ((npc - 0x31800c) & 0x03fffffc)); // b ROM_BASE+0x312c2c |
1408 |
– |
#endif |
1403 |
|
|
1404 |
|
/* |
1405 |
|
// Disable FE0A/FE06 opcodes |
1761 |
|
*wp++ = htons(0x1000); |
1762 |
|
*wp++ = htons(0x001e); |
1763 |
|
*wp++ = htons(0x157c); // move.b #PVR,$1d(a2) |
1764 |
< |
*wp++ = htons(PVR >> 16); |
1764 |
> |
*wp++ = htons(((PVR & 0x80000000) ? 0x10 : 0) | ((PVR >> 16) & 0xff)); |
1765 |
|
*wp++ = htons(0x001d); |
1766 |
|
*wp++ = htons(0x263c); // move.l #RAMSize,d3 |
1767 |
|
*wp++ = htons(RAMSize >> 16); |