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root/cebix/SheepShaver/src/rom_patches.cpp

Comparing SheepShaver/src/rom_patches.cpp (file contents):
Revision 1.30 by gbeauche, 2004-06-22T17:10:06Z vs.
Revision 1.32 by gbeauche, 2004-06-30T08:17:12Z

#	Line 847 | Line 847 | static bool patch_nanokernel_boot(void)
847		lp[7] = htonl(0x00040004);      // Inst cache assoc/Data cache assoc
848		lp[8] = htonl(0x00400002);      // TLB total size/TLB assoc
849		break;
850	<	case 8:         // 750
850	>	case 8:         // 750, 750FX
851	>	case 0x7000:
852		lp[0] = htonl(0x1000);          // Page size
853		lp[1] = htonl(0x8000);          // Data cache size
854		lp[2] = htonl(0x8000);          // Inst cache size
#	Line 871 | Line 872 | static bool patch_nanokernel_boot(void)
872		lp[8] = htonl(0x00800002);      // TLB total size/TLB assoc
873		break;
874		//              case 11:        // X704?
875	<	case 12:        // 7400, 7410
875	>	case 12:        // 7400, 7410, 7450, 7455, 7457
876		case 0x800c:
877	+	case 0x8000:
878	+	case 0x8001:
879	+	case 0x8002:
880		lp[0] = htonl(0x1000);          // Page size
881		lp[1] = htonl(0x8000);          // Data cache size
882		lp[2] = htonl(0x8000);          // Inst cache size
#	Line 1746 | Line 1750 | static bool patch_68k(void)
1750		*wp++ = htons(0x1000);
1751		*wp++ = htons(0x001e);
1752		*wp++ = htons(0x157c);                  // move.b       #PVR,$1d(a2)
1753	<	*wp++ = htons(PVR >> 16);
1753	>	*wp++ = htons(((PVR & 0x80000000) ? 0x10 : 0) | ((PVR >> 16) & 0xff));
1754		*wp++ = htons(0x001d);
1755		*wp++ = htons(0x263c);                  // move.l       #RAMSize,d3
1756		*wp++ = htons(RAMSize >> 16);

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