ViewVC Help

View File | Revision Log | Show Annotations | Revision Graph | Root Listing

root/cebix/SheepShaver/src/rom_patches.cpp

Comparing SheepShaver/src/rom_patches.cpp (file contents):
Revision 1.32 by gbeauche, 2004-06-30T08:17:12Z vs.
Revision 1.33 by gbeauche, 2004-07-01T22:55:00Z

#	Line 911 | Line 911 | static bool patch_nanokernel_boot(void)
911		lp[7] = htonl(0x00080008);      // Inst cache assoc/Data cache assoc
912		lp[8] = htonl(0x00800004);      // TLB total size/TLB assoc
913		break;
914	+	case 0x39:      // 970
915	+	lp[0] = htonl(0x1000);          // Page size
916	+	lp[1] = htonl(0x8000);          // Data cache size
917	+	lp[2] = htonl(0x10000);         // Inst cache size
918	+	lp[3] = htonl(0x00200020);      // Coherency block size/Reservation granule size
919	+	lp[4] = htonl(0x00010020);      // Unified caches/Inst cache line size
920	+	lp[5] = htonl(0x00200020);      // Data cache line size/Data cache block size touch
921	+	lp[6] = htonl(0x00800080);      // Inst cache block size/Data cache block size
922	+	lp[7] = htonl(0x00020002);      // Inst cache assoc/Data cache assoc
923	+	lp[8] = htonl(0x02000004);      // TLB total size/TLB assoc
924	+	break;
925		default:
926		printf("WARNING: Unknown CPU type\n");
927		break;

Diff Legend

–	Removed lines
+	Added lines
<	Changed lines
>	Changed lines