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root/cebix/SheepShaver/src/rom_patches.cpp
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Comparing SheepShaver/src/rom_patches.cpp (file contents):
Revision 1.32 by gbeauche, 2004-06-30T08:17:12Z vs.
Revision 1.35 by gbeauche, 2004-07-14T08:24:07Z

# Line 911 | Line 911 | static bool patch_nanokernel_boot(void)
911                          lp[7] = htonl(0x00080008);      // Inst cache assoc/Data cache assoc
912                          lp[8] = htonl(0x00800004);      // TLB total size/TLB assoc
913                          break;
914 +                case 0x39:      // 970
915 +                        lp[0] = htonl(0x1000);          // Page size
916 +                        lp[1] = htonl(0x8000);          // Data cache size
917 +                        lp[2] = htonl(0x10000);         // Inst cache size
918 +                        lp[3] = htonl(0x00200020);      // Coherency block size/Reservation granule size
919 +                        lp[4] = htonl(0x00010020);      // Unified caches/Inst cache line size
920 +                        lp[5] = htonl(0x00200020);      // Data cache line size/Data cache block size touch
921 +                        lp[6] = htonl(0x00800080);      // Inst cache block size/Data cache block size
922 +                        lp[7] = htonl(0x00020002);      // Inst cache assoc/Data cache assoc
923 +                        lp[8] = htonl(0x02000004);      // TLB total size/TLB assoc
924 +                        break;
925                  default:
926                          printf("WARNING: Unknown CPU type\n");
927                          break;
# Line 1740 | Line 1751 | static bool patch_68k(void)
1751          *wp++ = htons(M68K_NOP);
1752          *wp = htons(M68K_NOP);
1753  
1754 <        // Gestalt PowerPC page size, RAM size (InitGestalt, via 0x25c)
1754 >        // Gestalt PowerPC page size, CPU type, RAM size (InitGestalt, via 0x25c)
1755          static const uint8 page_size2_dat[] = {0x26, 0x79, 0x5f, 0xff, 0xef, 0xd8, 0x25, 0x6b, 0x00, 0x10, 0x00, 0x1e};
1756          if ((base = find_rom_data(0x50000, 0x70000, page_size2_dat, sizeof(page_size2_dat))) == 0) return false;
1757          D(bug("page_size2 %08lx\n", base));
# Line 1750 | Line 1761 | static bool patch_68k(void)
1761          *wp++ = htons(0x1000);
1762          *wp++ = htons(0x001e);
1763          *wp++ = htons(0x157c);                  // move.b       #PVR,$1d(a2)
1764 <        *wp++ = htons(((PVR & 0x80000000) ? 0x10 : 0) | ((PVR >> 16) & 0xff));
1764 >        uint32 cput = (PVR >> 16);
1765 >        if (cput == 0x7000)
1766 >                cput |= 0x20;
1767 >        else if (cput >= 0x8000 && cput <= 0x8002)
1768 >                cput |= 0x10;
1769 >        cput &= 0xff;
1770 >        *wp++ = htons(cput);
1771          *wp++ = htons(0x001d);
1772          *wp++ = htons(0x263c);                  // move.l       #RAMSize,d3
1773          *wp++ = htons(RAMSize >> 16);
# Line 1803 | Line 1820 | static bool patch_68k(void)
1820                  if ((base = find_rom_data(0x13000, 0x20000, gc_mask2_dat, sizeof(gc_mask2_dat))) == 0) return false;
1821                  D(bug("gc_mask2 %08lx\n", base));
1822                  wp = (uint16 *)(ROM_BASE + base);
1823 <                if (ROMType == ROMTYPE_GOSSAMER)
1823 >                if (ROMType == ROMTYPE_GOSSAMER) {
1824 >                        *wp++ = htons(M68K_NOP);
1825 >                        *wp++ = htons(M68K_NOP);
1826                          *wp++ = htons(M68K_NOP);
1827 +                        *wp++ = htons(M68K_NOP);
1828 +                }
1829                  for (int i=0; i<5; i++) {
1830                          *wp++ = htons(M68K_NOP);
1831                          *wp++ = htons(M68K_NOP);

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