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root/cebix/SheepShaver/src/rom_patches.cpp
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Comparing SheepShaver/src/rom_patches.cpp (file contents):
Revision 1.8 by gbeauche, 2003-09-28T21:27:33Z vs.
Revision 1.20 by gbeauche, 2003-12-14T14:23:46Z

# Line 40 | Line 40
40   #include "audio_defs.h"
41   #include "serial.h"
42   #include "macos_util.h"
43 + #include "thunks.h"
44  
45   #define DEBUG 0
46   #include "debug.h"
# Line 58 | Line 59
59  
60  
61   // Other ROM addresses
62 < const uint32 CHECK_LOAD_PATCH_SPACE = 0x2f7f00;
63 < const uint32 PUT_SCRAP_PATCH_SPACE = 0x2f7f80;
64 < const uint32 GET_SCRAP_PATCH_SPACE = 0x2f7fc0;
65 < const uint32 ADDR_MAP_PATCH_SPACE = 0x2f8000;
62 > const uint32 CHECK_LOAD_PATCH_SPACE = 0x2fcf00;
63 > const uint32 PUT_SCRAP_PATCH_SPACE = 0x2fcf80;
64 > const uint32 GET_SCRAP_PATCH_SPACE = 0x2fcfc0;
65 > const uint32 ADDR_MAP_PATCH_SPACE = 0x2fd000;
66  
67   // Global variables
68   int ROMType;                            // ROM type
# Line 131 | Line 132 | void decode_parcels(const uint8 *src, ui
132                            (parcel_type >> 8) & 0xff, parcel_type & 0xff, &parcel_data[6]));
133                  if (parcel_type == FOURCC('r','o','m',' ')) {
134                          uint32 lzss_offset  = ntohl(parcel_data[2]);
135 <                        uint32 lzss_size = ((uint32)src + parcel_offset) - ((uint32)parcel_data + lzss_offset);
135 >                        uint32 lzss_size = ((uintptr)src + next_offset) - ((uintptr)parcel_data + lzss_offset);
136                          decode_lzss((uint8 *)parcel_data + lzss_offset, dest, lzss_size);
137                  }
138                  parcel_offset = next_offset;
# Line 269 | Line 270 | static uint32 find_rom_trap(uint16 trap)
270  
271  
272   /*
273 + *  Return target of branch instruction specified at ADDR, or 0 if
274 + *  there is no such instruction
275 + */
276 +
277 + static uint32 powerpc_branch_target(uintptr addr)
278 + {
279 +        uint32 opcode = ntohl(*(uint32 *)addr);
280 +        uint32 primop = opcode >> 26;
281 +        uint32 target = 0;
282 +
283 +        if (primop == 18) {                     // Branch
284 +                target = opcode & 0x3fffffc;
285 +                if (target & 0x2000000)
286 +                        target |= 0xfc000000;
287 +                if ((opcode & 2) == 0)
288 +                        target += addr;
289 +        }
290 +        else if (primop == 16) {        // Branch Conditional
291 +                target = (int32)(int16)(opcode & 0xfffc);
292 +                if ((opcode & 2) == 0)
293 +                        target += addr;
294 +        }
295 +        return target;
296 + }
297 +
298 +
299 + /*
300 + *  Search ROM for instruction branching to target address, return 0 if none found
301 + */
302 +
303 + static uint32 find_rom_powerpc_branch(uint32 start, uint32 end, uint32 target)
304 + {
305 +        for (uint32 addr = start; addr < end; addr += 4) {
306 +                if (powerpc_branch_target(ROM_BASE + addr) == ROM_BASE + target)
307 +                        return addr;
308 +        }
309 +        return 0;
310 + }
311 +
312 +
313 + /*
314   *  List of audio sifters installed in ROM and System file
315   */
316  
# Line 447 | Line 489 | static const uint8 cdrom_driver[] = {  //
489          0x4e, 0x75                                                      //  rts
490   };
491  
492 < #if EMULATED_PPC
451 < #define SERIAL_TRAMPOLINES 1
452 < static uint32 serial_nothing_tvect[2] = {POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_NOTHING), 0};
453 < static uint32 serial_open_tvect[2] = {POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_OPEN), 0};
454 < static uint32 serial_prime_in_tvect[2] = {POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_PRIME_IN), 0};
455 < static uint32 serial_prime_out_tvect[2] = {POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_PRIME_OUT), 0};
456 < static uint32 serial_control_tvect[2] = {POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_CONTROL), 0};
457 < static uint32 serial_status_tvect[2] = {POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_STATUS), 0};
458 < static uint32 serial_close_tvect[2] = {POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_CLOSE), 0};
459 < #elif defined(__linux__)
460 < #define SERIAL_TRAMPOLINES 1
461 < static uint32 serial_nothing_tvect[2] = {(uint32)SerialNothing, 0};
462 < static uint32 serial_open_tvect[2] = {(uint32)SerialOpen, 0};
463 < static uint32 serial_prime_in_tvect[2] = {(uint32)SerialPrimeIn, 0};
464 < static uint32 serial_prime_out_tvect[2] = {(uint32)SerialPrimeOut, 0};
465 < static uint32 serial_control_tvect[2] = {(uint32)SerialControl, 0};
466 < static uint32 serial_status_tvect[2] = {(uint32)SerialStatus, 0};
467 < static uint32 serial_close_tvect[2] = {(uint32)SerialClose, 0};
468 < #endif
492 > static uint32 long_ptr;
493  
494 < static const uint32 ain_driver[] = {    // .AIn driver header
495 <        0x4d000000, 0x00000000,
496 <        0x00200040, 0x00600080,
497 <        0x00a0042e, 0x41496e00,
498 <        0x00000000, 0x00000000,
499 <        0xaafe0700, 0x00000000,
500 <        0x00000000, 0x00179822,
501 < #ifdef SERIAL_TRAMPOLINES
502 <        0x00010004, (uint32)serial_nothing_tvect,
503 < #else
504 <        0x00010004, (uint32)SerialNothing,
505 < #endif
506 <        0x00000000, 0x00000000,
507 <        0xaafe0700, 0x00000000,
508 <        0x00000000, 0x00179822,
509 < #ifdef SERIAL_TRAMPOLINES
510 <        0x00010004, (uint32)serial_prime_in_tvect,
511 < #else
512 <        0x00010004, (uint32)SerialPrimeIn,
513 < #endif
514 <        0x00000000, 0x00000000,
515 <        0xaafe0700, 0x00000000,
516 <        0x00000000, 0x00179822,
517 < #ifdef SERIAL_TRAMPOLINES
518 <        0x00010004, (uint32)serial_control_tvect,
519 < #else
520 <        0x00010004, (uint32)SerialControl,
521 < #endif
522 <        0x00000000, 0x00000000,
523 <        0xaafe0700, 0x00000000,
524 <        0x00000000, 0x00179822,
525 < #ifdef SERIAL_TRAMPOLINES
526 <        0x00010004, (uint32)serial_status_tvect,
527 < #else
528 <        0x00010004, (uint32)SerialStatus,
529 < #endif
530 <        0x00000000, 0x00000000,
531 <        0xaafe0700, 0x00000000,
532 <        0x00000000, 0x00179822,
533 < #ifdef SERIAL_TRAMPOLINES
510 <        0x00010004, (uint32)serial_nothing_tvect,
511 < #else
512 <        0x00010004, (uint32)SerialNothing,
513 < #endif
514 <        0x00000000, 0x00000000,
494 > static void SetLongBase(uint32 addr)
495 > {
496 >        long_ptr = addr;
497 > }
498 >
499 > static void Long(uint32 value)
500 > {
501 >        WriteMacInt32(long_ptr, value);
502 >        long_ptr += 4;
503 > }
504 >
505 > static void gen_ain_driver(uintptr addr)
506 > {
507 >        SetLongBase(addr);
508 >
509 >        // .AIn driver header
510 >        Long(0x4d000000); Long(0x00000000);
511 >        Long(0x00200040); Long(0x00600080);
512 >        Long(0x00a0042e); Long(0x41496e00);
513 >        Long(0x00000000); Long(0x00000000);
514 >        Long(0xaafe0700); Long(0x00000000);
515 >        Long(0x00000000); Long(0x00179822);
516 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_NOTHING));
517 >        Long(0x00000000); Long(0x00000000);
518 >        Long(0xaafe0700); Long(0x00000000);
519 >        Long(0x00000000); Long(0x00179822);
520 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_PRIME_IN));
521 >        Long(0x00000000); Long(0x00000000);
522 >        Long(0xaafe0700); Long(0x00000000);
523 >        Long(0x00000000); Long(0x00179822);
524 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CONTROL));
525 >        Long(0x00000000); Long(0x00000000);
526 >        Long(0xaafe0700); Long(0x00000000);
527 >        Long(0x00000000); Long(0x00179822);
528 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_STATUS));
529 >        Long(0x00000000); Long(0x00000000);
530 >        Long(0xaafe0700); Long(0x00000000);
531 >        Long(0x00000000); Long(0x00179822);
532 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_NOTHING));
533 >        Long(0x00000000); Long(0x00000000);
534   };
535  
536 < static const uint32 aout_driver[] = {   // .AOut driver header
537 <        0x4d000000, 0x00000000,
538 <        0x00200040, 0x00600080,
539 <        0x00a0052e, 0x414f7574,
540 <        0x00000000, 0x00000000,
541 <        0xaafe0700, 0x00000000,
542 <        0x00000000, 0x00179822,
543 < #ifdef SERIAL_TRAMPOLINES
544 <        0x00010004, (uint32)serial_open_tvect,
545 < #else
546 <        0x00010004, (uint32)SerialOpen,
547 < #endif
548 <        0x00000000, 0x00000000,
549 <        0xaafe0700, 0x00000000,
550 <        0x00000000, 0x00179822,
551 < #ifdef SERIAL_TRAMPOLINES
552 <        0x00010004, (uint32)serial_prime_out_tvect,
553 < #else
554 <        0x00010004, (uint32)SerialPrimeOut,
555 < #endif
556 <        0x00000000, 0x00000000,
557 <        0xaafe0700, 0x00000000,
558 <        0x00000000, 0x00179822,
559 < #ifdef SERIAL_TRAMPOLINES
560 <        0x00010004, (uint32)serial_control_tvect,
561 < #else
562 <        0x00010004, (uint32)SerialControl,
563 < #endif
564 <        0x00000000, 0x00000000,
546 <        0xaafe0700, 0x00000000,
547 <        0x00000000, 0x00179822,
548 < #ifdef SERIAL_TRAMPOLINES
549 <        0x00010004, (uint32)serial_status_tvect,
550 < #else
551 <        0x00010004, (uint32)SerialStatus,
552 < #endif
553 <        0x00000000, 0x00000000,
554 <        0xaafe0700, 0x00000000,
555 <        0x00000000, 0x00179822,
556 < #ifdef SERIAL_TRAMPOLINES
557 <        0x00010004, (uint32)serial_close_tvect,
558 < #else
559 <        0x00010004, (uint32)SerialClose,
560 < #endif
561 <        0x00000000, 0x00000000,
536 > static void gen_aout_driver(uintptr addr)
537 > {
538 >        SetLongBase(addr);
539 >
540 >        // .AOut driver header
541 >        Long(0x4d000000); Long(0x00000000);
542 >        Long(0x00200040); Long(0x00600080);
543 >        Long(0x00a0052e); Long(0x414f7574);
544 >        Long(0x00000000); Long(0x00000000);
545 >        Long(0xaafe0700); Long(0x00000000);
546 >        Long(0x00000000); Long(0x00179822);
547 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_OPEN));
548 >        Long(0x00000000); Long(0x00000000);
549 >        Long(0xaafe0700); Long(0x00000000);
550 >        Long(0x00000000); Long(0x00179822);
551 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_PRIME_OUT));
552 >        Long(0x00000000); Long(0x00000000);
553 >        Long(0xaafe0700); Long(0x00000000);
554 >        Long(0x00000000); Long(0x00179822);
555 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CONTROL));
556 >        Long(0x00000000); Long(0x00000000);
557 >        Long(0xaafe0700); Long(0x00000000);
558 >        Long(0x00000000); Long(0x00179822);
559 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_STATUS));
560 >        Long(0x00000000); Long(0x00000000);
561 >        Long(0xaafe0700); Long(0x00000000);
562 >        Long(0x00000000); Long(0x00179822);
563 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CLOSE));
564 >        Long(0x00000000); Long(0x00000000);
565   };
566  
567 < static const uint32 bin_driver[] = {    // .BIn driver header
568 <        0x4d000000, 0x00000000,
569 <        0x00200040, 0x00600080,
570 <        0x00a0042e, 0x42496e00,
571 <        0x00000000, 0x00000000,
572 <        0xaafe0700, 0x00000000,
573 <        0x00000000, 0x00179822,
574 < #ifdef SERIAL_TRAMPOLINES
575 <        0x00010004, (uint32)serial_nothing_tvect,
576 < #else
577 <        0x00010004, (uint32)SerialNothing,
578 < #endif
579 <        0x00000000, 0x00000000,
580 <        0xaafe0700, 0x00000000,
581 <        0x00000000, 0x00179822,
582 < #ifdef SERIAL_TRAMPOLINES
583 <        0x00010004, (uint32)serial_prime_in_tvect,
584 < #else
585 <        0x00010004, (uint32)SerialPrimeIn,
586 < #endif
587 <        0x00000000, 0x00000000,
588 <        0xaafe0700, 0x00000000,
589 <        0x00000000, 0x00179822,
590 < #ifdef SERIAL_TRAMPOLINES
591 <        0x00010004, (uint32)serial_control_tvect,
592 < #else
593 <        0x00010004, (uint32)SerialControl,
594 < #endif
595 <        0x00000000, 0x00000000,
593 <        0xaafe0700, 0x00000000,
594 <        0x00000000, 0x00179822,
595 < #ifdef SERIAL_TRAMPOLINES
596 <        0x00010004, (uint32)serial_status_tvect,
597 < #else
598 <        0x00010004, (uint32)SerialStatus,
599 < #endif
600 <        0x00000000, 0x00000000,
601 <        0xaafe0700, 0x00000000,
602 <        0x00000000, 0x00179822,
603 < #ifdef SERIAL_TRAMPOLINES
604 <        0x00010004, (uint32)serial_nothing_tvect,
605 < #else
606 <        0x00010004, (uint32)SerialNothing,
607 < #endif
608 <        0x00000000, 0x00000000,
567 > static void gen_bin_driver(uintptr addr)
568 > {
569 >        SetLongBase(addr);
570 >
571 >        // .BIn driver header
572 >        Long(0x4d000000); Long(0x00000000);
573 >        Long(0x00200040); Long(0x00600080);
574 >        Long(0x00a0042e); Long(0x42496e00);
575 >        Long(0x00000000); Long(0x00000000);
576 >        Long(0xaafe0700); Long(0x00000000);
577 >        Long(0x00000000); Long(0x00179822);
578 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_NOTHING));
579 >        Long(0x00000000); Long(0x00000000);
580 >        Long(0xaafe0700); Long(0x00000000);
581 >        Long(0x00000000); Long(0x00179822);
582 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_PRIME_IN));
583 >        Long(0x00000000); Long(0x00000000);
584 >        Long(0xaafe0700); Long(0x00000000);
585 >        Long(0x00000000); Long(0x00179822);
586 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CONTROL));
587 >        Long(0x00000000); Long(0x00000000);
588 >        Long(0xaafe0700); Long(0x00000000);
589 >        Long(0x00000000); Long(0x00179822);
590 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_STATUS));
591 >        Long(0x00000000); Long(0x00000000);
592 >        Long(0xaafe0700); Long(0x00000000);
593 >        Long(0x00000000); Long(0x00179822);
594 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_NOTHING));
595 >        Long(0x00000000); Long(0x00000000);
596   };
597  
598 < static const uint32 bout_driver[] = {   // .BOut driver header
599 <        0x4d000000, 0x00000000,
600 <        0x00200040, 0x00600080,
601 <        0x00a0052e, 0x424f7574,
602 <        0x00000000, 0x00000000,
603 <        0xaafe0700, 0x00000000,
604 <        0x00000000, 0x00179822,
605 < #ifdef SERIAL_TRAMPOLINES
606 <        0x00010004, (uint32)serial_open_tvect,
607 < #else
608 <        0x00010004, (uint32)SerialOpen,
609 < #endif
610 <        0x00000000, 0x00000000,
611 <        0xaafe0700, 0x00000000,
612 <        0x00000000, 0x00179822,
613 < #ifdef SERIAL_TRAMPOLINES
614 <        0x00010004, (uint32)serial_prime_out_tvect,
615 < #else
616 <        0x00010004, (uint32)SerialPrimeOut,
617 < #endif
618 <        0x00000000, 0x00000000,
619 <        0xaafe0700, 0x00000000,
620 <        0x00000000, 0x00179822,
621 < #ifdef SERIAL_TRAMPOLINES
622 <        0x00010004, (uint32)serial_control_tvect,
623 < #else
624 <        0x00010004, (uint32)SerialControl,
625 < #endif
626 <        0x00000000, 0x00000000,
640 <        0xaafe0700, 0x00000000,
641 <        0x00000000, 0x00179822,
642 < #ifdef SERIAL_TRAMPOLINES
643 <        0x00010004, (uint32)serial_status_tvect,
644 < #else
645 <        0x00010004, (uint32)SerialStatus,
646 < #endif
647 <        0x00000000, 0x00000000,
648 <        0xaafe0700, 0x00000000,
649 <        0x00000000, 0x00179822,
650 < #ifdef SERIAL_TRAMPOLINES
651 <        0x00010004, (uint32)serial_close_tvect,
652 < #else
653 <        0x00010004, (uint32)SerialClose,
654 < #endif
655 <        0x00000000, 0x00000000,
598 > static void gen_bout_driver(uintptr addr)
599 > {
600 >        SetLongBase(addr);
601 >
602 >        // .BOut driver header
603 >        Long(0x4d000000); Long(0x00000000);
604 >        Long(0x00200040); Long(0x00600080);
605 >        Long(0x00a0052e); Long(0x424f7574);
606 >        Long(0x00000000); Long(0x00000000);
607 >        Long(0xaafe0700); Long(0x00000000);
608 >        Long(0x00000000); Long(0x00179822);
609 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_OPEN));
610 >        Long(0x00000000); Long(0x00000000);
611 >        Long(0xaafe0700); Long(0x00000000);
612 >        Long(0x00000000); Long(0x00179822);
613 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_PRIME_OUT));
614 >        Long(0x00000000); Long(0x00000000);
615 >        Long(0xaafe0700); Long(0x00000000);
616 >        Long(0x00000000); Long(0x00179822);
617 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CONTROL));
618 >        Long(0x00000000); Long(0x00000000);
619 >        Long(0xaafe0700); Long(0x00000000);
620 >        Long(0x00000000); Long(0x00179822);
621 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_STATUS));
622 >        Long(0x00000000); Long(0x00000000);
623 >        Long(0xaafe0700); Long(0x00000000);
624 >        Long(0x00000000); Long(0x00179822);
625 >        Long(0x00010004); Long(NativeTVECT(NATIVE_SERIAL_CLOSE));
626 >        Long(0x00000000); Long(0x00000000);
627   };
628  
629   static const uint8 adbop_patch[] = {    // Call ADBOp() completion procedure
# Line 679 | Line 650 | static const uint8 adbop_patch[] = {   //
650  
651  
652   /*
653 + *  Copy PowerPC code to ROM image and reverse bytes if necessary
654 + */
655 +
656 + static inline void memcpy_powerpc_code(void *dst, const void *src, size_t len)
657 + {
658 + #ifdef WORDS_BIGENDIAN
659 +        (void)memcpy(dst, src, len);
660 + #else
661 +        uint32 *d = (uint32 *)dst;
662 +        uint32 *s = (uint32 *)src;
663 +        for (int i = 0; i < len/4; i++)
664 +                d[i] = htonl(s[i]);
665 + #endif
666 + }
667 +
668 +
669 + /*
670   *  Install ROM patches (RAMBase and KernelDataAddr must be set)
671   */
672  
# Line 701 | Line 689 | bool PatchROM(void)
689                  ROMType = ROMTYPE_ZANZIBAR;
690          else if (!memcmp((void *)(ROM_BASE + 0x30d064), "Boot Gazelle", 12))
691                  ROMType = ROMTYPE_GAZELLE;
692 +        else if (!memcmp((void *)(ROM_BASE + 0x30d064), "Boot Gossamer", 13))
693 +                ROMType = ROMTYPE_GOSSAMER;
694          else if (!memcmp((void *)(ROM_BASE + 0x30d064), "NewWorld", 8))
695                  ROMType = ROMTYPE_NEWWORLD;
696          else
697                  return false;
698  
699 +        // Check that other ROM addresses point to really free regions
700 +        if (ntohl(*(uint32 *)(ROM_BASE + CHECK_LOAD_PATCH_SPACE)) != 0x6b636b63)
701 +                return false;
702 +        if (ntohl(*(uint32 *)(ROM_BASE + PUT_SCRAP_PATCH_SPACE)) != 0x6b636b63)
703 +                return false;
704 +        if (ntohl(*(uint32 *)(ROM_BASE + GET_SCRAP_PATCH_SPACE)) != 0x6b636b63)
705 +                return false;
706 +        if (ntohl(*(uint32 *)(ROM_BASE + ADDR_MAP_PATCH_SPACE)) != 0x6b636b63)
707 +                return false;
708 +
709          // Apply patches
710          if (!patch_nanokernel_boot()) return false;
711          if (!patch_68k_emul()) return false;
# Line 738 | Line 738 | bool PatchROM(void)
738   static bool patch_nanokernel_boot(void)
739   {
740          uint32 *lp;
741 +        uint32 base, loc;
742  
743          // ROM boot structure patches
744          lp = (uint32 *)(ROM_BASE + 0x30d000);
# Line 750 | Line 751 | static bool patch_nanokernel_boot(void)
751          lp[0xfd8 >> 2] = htonl(ROM_BASE + 0x2a);                // 68k reset vector
752  
753          // Skip SR/BAT/SDR init
754 <        if (ROMType == ROMTYPE_GAZELLE || ROMType == ROMTYPE_NEWWORLD) {
755 <                lp = (uint32 *)(ROM_BASE + 0x310000);
754 >        loc = 0x310000;
755 >        if (ROMType == ROMTYPE_GAZELLE || ROMType == ROMTYPE_GOSSAMER || ROMType == ROMTYPE_NEWWORLD) {
756 >                lp = (uint32 *)(ROM_BASE + loc);
757                  *lp++ = htonl(POWERPC_NOP);
758                  *lp = htonl(0x38000000);
759          }
760 <        static const uint32 sr_init_loc[] = {0x3101b0, 0x3101b0, 0x3101b0, 0x3101ec, 0x310200};
761 <        lp = (uint32 *)(ROM_BASE + 0x310008);
762 <        *lp = htonl(0x48000000 | (sr_init_loc[ROMType] - 8) & 0xffff);  // b            ROM_BASE+0x3101b0
763 <        lp = (uint32 *)(ROM_BASE + sr_init_loc[ROMType]);
760 >        static const uint8 sr_init_dat[] = {0x35, 0x4a, 0xff, 0xfc, 0x7d, 0x86, 0x50, 0x2e};
761 >        if ((base = find_rom_data(0x3101b0, 0x3105b0, sr_init_dat, sizeof(sr_init_dat))) == 0) return false;
762 >        D(bug("sr_init %08lx\n", base));
763 >        lp = (uint32 *)(ROM_BASE + loc + 8);
764 >        *lp = htonl(0x48000000 | ((base - loc - 8) & 0x3fffffc));       // b            ROM_BASE+0x3101b0
765 >        lp = (uint32 *)(ROM_BASE + base);
766          *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);            // lwz  r1,(pointer to Kernel Data)
767          *lp++ = htonl(0x3da0dead);              // lis  r13,0xdead      (start of kernel memory)
768          *lp++ = htonl(0x3dc00010);              // lis  r14,0x0010      (size of page table)
769          *lp = htonl(0x3de00010);                // lis  r15,0x0010      (size of kernel memory)
770  
771          // Don't read PVR
772 <        static const uint32 pvr_loc[] = {0x3103b0, 0x3103b4, 0x3103b4, 0x310400, 0x310438};
773 <        lp = (uint32 *)(ROM_BASE + pvr_loc[ROMType]);
772 >        static const uint8 pvr_read_dat[] = {0x7d, 0x9f, 0x42, 0xa6};
773 >        if ((base = find_rom_data(0x3103b0, 0x3108b0, pvr_read_dat, sizeof(pvr_read_dat))) == 0) return false;
774 >        D(bug("pvr_read %08lx\n", base));
775 >        lp = (uint32 *)(ROM_BASE + base);
776          *lp = htonl(0x81800000 + XLM_PVR);      // lwz  r12,(theoretical PVR)
777  
778          // Set CPU specific data (even if ROM doesn't have support for that CPU)
773        lp = (uint32 *)(ROM_BASE + pvr_loc[ROMType]);
779          if (ntohl(lp[6]) != 0x2c0c0001)
780                  return false;
781          uint32 ofs = ntohl(lp[7]) & 0xffff;
782          D(bug("ofs %08lx\n", ofs));
783          lp[8] = htonl((ntohl(lp[8]) & 0xffff) | 0x48000000);    // beq -> b
784 <        uint32 loc = (ntohl(lp[8]) & 0xffff) + (uint32)(lp+8) - ROM_BASE;
784 >        loc = (ntohl(lp[8]) & 0xffff) + (uint32)(lp+8) - ROM_BASE;
785          D(bug("loc %08lx\n", loc));
786          lp = (uint32 *)(ROM_BASE + ofs + 0x310000);
787          switch (PVR >> 16) {
# Line 891 | Line 896 | static bool patch_nanokernel_boot(void)
896          }
897  
898          // Don't set SPRG3, don't test MQ
899 <        lp = (uint32 *)(ROM_BASE + loc + 0x20);
900 <        *lp++ = htonl(POWERPC_NOP);
901 <        lp++;
902 <        *lp++ = htonl(POWERPC_NOP);
903 <        lp++;
904 <        *lp = htonl(POWERPC_NOP);
899 >        static const uint8 sprg3_mq_dat[] = {0x7d, 0x13, 0x43, 0xa6, 0x3d, 0x00, 0x00, 0x04, 0x7d, 0x00, 0x03, 0xa6, 0x39, 0x00, 0x00, 0x00, 0x7d, 0x00, 0x02, 0xa6};
900 >        if ((base = find_rom_data(loc + 0x20, loc + 0x60, sprg3_mq_dat, sizeof(sprg3_mq_dat))) == 0) return false;
901 >        D(bug("sprg3/mq %08lx\n", base));
902 >        lp = (uint32 *)(ROM_BASE + base);
903 >        lp[0] = htonl(POWERPC_NOP);
904 >        lp[2] = htonl(POWERPC_NOP);
905 >        lp[4] = htonl(POWERPC_NOP);
906  
907          // Don't read MSR
908 <        lp = (uint32 *)(ROM_BASE + loc + 0x40);
908 >        static const uint8 msr_dat[] = {0x7d, 0xc0, 0x00, 0xa6};
909 >        if ((base = find_rom_data(loc + 0x40, loc + 0x80, msr_dat, sizeof(msr_dat))) == 0) return false;
910 >        D(bug("msr %08lx\n", base));
911 >        lp = (uint32 *)(ROM_BASE + base);
912          *lp = htonl(0x39c00000);                // li   r14,0
913  
914          // Don't write to DEC
# Line 909 | Line 918 | static bool patch_nanokernel_boot(void)
918          D(bug("loc %08lx\n", loc));
919  
920          // Don't set SPRG3
921 <        lp = (uint32 *)(ROM_BASE + loc + 0x2c);
921 >        static const uint8 sprg3_dat[] = {0x39, 0x21, 0x03, 0x60, 0x7d, 0x33, 0x43, 0xa6, 0x39, 0x01, 0x04, 0x20};
922 >        if ((base = find_rom_data(0x310000, 0x314000, sprg3_dat, sizeof(sprg3_dat))) == 0) return false;
923 >        D(bug("sprg3 %08lx\n", base + 4));
924 >        lp = (uint32 *)(ROM_BASE + base + 4);
925          *lp = htonl(POWERPC_NOP);
926  
927          // Don't read PVR
928 <        static const uint32 pvr_ofs[] = {0x138, 0x138, 0x138, 0x140, 0x148};
929 <        lp = (uint32 *)(ROM_BASE + loc + pvr_ofs[ROMType]);
928 >        static const uint8 pvr_read2_dat[] = {0x7e, 0xff, 0x42, 0xa6, 0x56, 0xf7, 0x84, 0x3e};
929 >        if ((base = find_rom_data(0x310000, 0x320000, pvr_read2_dat, sizeof(pvr_read2_dat))) == 0) return false;
930 >        D(bug("pvr_read2 %08lx\n", base));
931 >        lp = (uint32 *)(ROM_BASE + base);
932          *lp = htonl(0x82e00000 + XLM_PVR);              // lwz  r23,(theoretical PVR)
933 <        lp = (uint32 *)(ROM_BASE + loc + 0x170);
934 <        if (ntohl(*lp) == 0x7eff42a6)   // NewWorld ROM
933 >        if ((base = find_rom_data(base + 4, 0x320000, pvr_read2_dat, sizeof(pvr_read2_dat))) != 0) {
934 >                D(bug("pvr_read2 %08lx\n", base));
935 >                lp = (uint32 *)(ROM_BASE + base);
936                  *lp = htonl(0x82e00000 + XLM_PVR);      // lwz  r23,(theoretical PVR)
937 <        lp = (uint32 *)(ROM_BASE + 0x313134);
938 <        if (ntohl(*lp) == 0x7e5f42a6)
939 <                *lp = htonl(0x82400000 + XLM_PVR);      // lwz  r18,(theoretical PVR)
940 <        lp = (uint32 *)(ROM_BASE + 0x3131f4);
941 <        if (ntohl(*lp) == 0x7e5f42a6)   // NewWorld ROM
937 >        }
938 >        static const uint8 pvr_read3_dat[] = {0x7e, 0x5f, 0x42, 0xa6, 0x56, 0x52, 0x84, 0x3e};
939 >        if ((base = find_rom_data(0x310000, 0x320000, pvr_read3_dat, sizeof(pvr_read3_dat))) != 0) {
940 >                D(bug("pvr_read3 %08lx\n", base));
941 >                lp = (uint32 *)(ROM_BASE + base);
942                  *lp = htonl(0x82400000 + XLM_PVR);      // lwz  r18,(theoretical PVR)
943 <        lp = (uint32 *)(ROM_BASE + 0x314600);
944 <        if (ntohl(*lp) == 0x7d3f42a6)
943 >        }
944 >        static const uint8 pvr_read4_dat[] = {0x7d, 0x3f, 0x42, 0xa6, 0x55, 0x29, 0x84, 0x3e};
945 >        if ((base = find_rom_data(0x310000, 0x320000, pvr_read4_dat, sizeof(pvr_read4_dat))) != 0) {
946 >                D(bug("pvr_read4 %08lx\n", base));
947 >                lp = (uint32 *)(ROM_BASE + base);
948                  *lp = htonl(0x81200000 + XLM_PVR);      // lzw  r9,(theoritical PVR)
949 +        }
950  
951          // Don't read SDR1
952 <        static const uint32 sdr1_ofs[] = {0x174, 0x174, 0x174, 0x17c, 0x19c};
953 <        lp = (uint32 *)(ROM_BASE + loc + sdr1_ofs[ROMType]);
952 >        static const uint8 sdr1_read_dat[] = {0x7d, 0x19, 0x02, 0xa6, 0x55, 0x16, 0x81, 0xde};
953 >        if ((base = find_rom_data(0x310000, 0x320000, sdr1_read_dat, sizeof(sdr1_read_dat))) == 0) return false;
954 >        D(bug("sdr1_read %08lx\n", base));
955 >        lp = (uint32 *)(ROM_BASE + base);
956          *lp++ = htonl(0x3d00dead);              // lis  r8,0xdead               (pointer to page table)
957          *lp++ = htonl(0x3ec0001f);              // lis  r22,0x001f      (size of page table)
958          *lp = htonl(POWERPC_NOP);
959  
960 <        // Don't clear page table
961 <        static const uint32 pgtb_ofs[] = {0x198, 0x198, 0x198, 0x1a0, 0x1c4};
962 <        lp = (uint32 *)(ROM_BASE + loc + pgtb_ofs[ROMType]);
960 >        // Don't clear page table, don't invalidate TLB
961 >        static const uint8 pgtb_clear_dat[] = {0x36, 0xd6, 0xff, 0xfc, 0x7e, 0xe8, 0xb1, 0x2e, 0x41, 0x81, 0xff, 0xf8};
962 >        if ((base = find_rom_data(0x310000, 0x320000, pgtb_clear_dat, sizeof(pgtb_clear_dat))) == 0) return false;
963 >        D(bug("pgtb_clear %08lx\n", base + 4));
964 >        lp = (uint32 *)(ROM_BASE + base + 4);
965          *lp = htonl(POWERPC_NOP);
966 <
967 <        // Don't invalidate TLB
945 <        static const uint32 tlb_ofs[] = {0x1a0, 0x1a0, 0x1a0, 0x1a8, 0x1cc};
946 <        lp = (uint32 *)(ROM_BASE + loc + tlb_ofs[ROMType]);
966 >        D(bug("tblie %08lx\n", base + 12));
967 >        lp = (uint32 *)(ROM_BASE + base + 12);
968          *lp = htonl(POWERPC_NOP);
969  
970          // Don't create RAM descriptor table
971 <        static const uint32 desc_ofs[] = {0x350, 0x350, 0x350, 0x358, 0x37c};
972 <        lp = (uint32 *)(ROM_BASE + loc + desc_ofs[ROMType]);
971 >        static const uint8 desc_create_dat[] = {0x97, 0xfd, 0x00, 0x04, 0x3b, 0xff, 0x10, 0x00, 0x4b, 0xff, 0xff, 0xdc};
972 >        if ((base = find_rom_data(0x310000, 0x320000, desc_create_dat, sizeof(desc_create_dat))) == 0) return false;
973 >        D(bug("desc_create %08lx\n", base))
974 >        lp = (uint32 *)(ROM_BASE + base);
975          *lp = htonl(POWERPC_NOP);
976  
977          // Don't load SRs and BATs
978 <        static const uint32 sr_ofs[] = {0x3d8, 0x3d8, 0x3d8, 0x3e0, 0x404};
979 <        lp = (uint32 *)(ROM_BASE + loc + sr_ofs[ROMType]);
978 >        static const uint8 sr_load[] = {0x7c, 0x00, 0x04, 0xac, 0x83, 0x9d, 0x00, 0x00, 0x93, 0x81, 0x05, 0xe8};
979 >        if ((loc = find_rom_data(0x310000, 0x320000, sr_load, sizeof(sr_load))) == 0) return false;
980 >        static const uint8 sr_load_caller[] = {0x3e, 0xd6, 0xff, 0xff, 0x41, 0x81, 0xff, 0xdc, 0xb2, 0xc8, 0x00, 0x02};
981 >        if ((base = find_rom_data(0x310000, 0x320000, sr_load_caller, sizeof(sr_load_caller))) == 0) return false;
982 >        if ((base = find_rom_powerpc_branch(base + 12, 0x320000, loc)) == 0) return false;
983 >        D(bug("sr_load %08lx, called from %08lx\n", loc, base));
984 >        lp = (uint32 *)(ROM_BASE + base);
985          *lp = htonl(POWERPC_NOP);
986  
987          // Don't mess with SRs
988 <        static const uint32 sr2_ofs[] = {0x312118, 0x312118, 0x312118, 0x312118, 0x3121b4};
989 <        lp = (uint32 *)(ROM_BASE + sr2_ofs[ROMType]);
988 >        static const uint8 sr_load2_dat[] = {0x83, 0xa1, 0x05, 0xe8, 0x57, 0x7c, 0x3e, 0x78, 0x7f, 0xbd, 0xe0, 0x2e};
989 >        if ((base = find_rom_data(0x310000, 0x320000, sr_load2_dat, sizeof(sr_load2_dat))) == 0) return false;
990 >        D(bug("sr_load2 %08lx\n", base));
991 >        lp = (uint32 *)(ROM_BASE + base);
992          *lp = htonl(POWERPC_BLR);
993  
994          // Don't check performance monitor
995 <        static const uint32 pm_ofs[] = {0x313148, 0x313148, 0x313148, 0x313148, 0x313218};
996 <        lp = (uint32 *)(ROM_BASE + pm_ofs[ROMType]);
997 <        while (ntohl(*lp) != 0x7e58eba6) lp++;
998 <        *lp++ = htonl(POWERPC_NOP);
999 <        while (ntohl(*lp) != 0x7e78eaa6) lp++;
1000 <        *lp++ = htonl(POWERPC_NOP);
1001 <        while (ntohl(*lp) != 0x7e59eba6) lp++;
1002 <        *lp++ = htonl(POWERPC_NOP);
1003 <        while (ntohl(*lp) != 0x7e79eaa6) lp++;
1004 <        *lp++ = htonl(POWERPC_NOP);
1005 <        while (ntohl(*lp) != 0x7e5aeba6) lp++;
1006 <        *lp++ = htonl(POWERPC_NOP);
1007 <        while (ntohl(*lp) != 0x7e7aeaa6) lp++;
1008 <        *lp++ = htonl(POWERPC_NOP);
1009 <        while (ntohl(*lp) != 0x7e5beba6) lp++;
1010 <        *lp++ = htonl(POWERPC_NOP);
1011 <        while (ntohl(*lp) != 0x7e7beaa6) lp++;
1012 <        *lp++ = htonl(POWERPC_NOP);
1013 <        while (ntohl(*lp) != 0x7e5feba6) lp++;
1014 <        *lp++ = htonl(POWERPC_NOP);
1015 <        while (ntohl(*lp) != 0x7e7feaa6) lp++;
1016 <        *lp++ = htonl(POWERPC_NOP);
1017 <        while (ntohl(*lp) != 0x7e5ceba6) lp++;
1018 <        *lp++ = htonl(POWERPC_NOP);
989 <        while (ntohl(*lp) != 0x7e7ceaa6) lp++;
990 <        *lp++ = htonl(POWERPC_NOP);
991 <        while (ntohl(*lp) != 0x7e5deba6) lp++;
992 <        *lp++ = htonl(POWERPC_NOP);
993 <        while (ntohl(*lp) != 0x7e7deaa6) lp++;
994 <        *lp++ = htonl(POWERPC_NOP);
995 <        while (ntohl(*lp) != 0x7e5eeba6) lp++;
996 <        *lp++ = htonl(POWERPC_NOP);
997 <        while (ntohl(*lp) != 0x7e7eeaa6) lp++;
998 <        *lp++ = htonl(POWERPC_NOP);
995 >        static const uint8 pm_check_dat[] = {0x7e, 0x58, 0xeb, 0xa6, 0x7e, 0x53, 0x90, 0xf8, 0x7e, 0x78, 0xea, 0xa6};
996 >        if ((base = find_rom_data(0x310000, 0x320000, pm_check_dat, sizeof(pm_check_dat))) == 0) return false;
997 >        D(bug("pm_check %08lx\n", base));
998 >        lp = (uint32 *)(ROM_BASE + base);
999 >        
1000 >        static const int spr_check_list[] = {
1001 >                952 /* mmcr0 */, 953 /* pmc1 */, 954 /* pmc2 */, 955 /* sia */,
1002 >                956 /* mmcr1 */, 957 /* pmc3 */, 958 /* pmc4 */, 959 /* sda */
1003 >        };
1004 >
1005 >        for (int i = 0; i < sizeof(spr_check_list)/sizeof(spr_check_list[0]); i++) {
1006 >                int spr = spr_check_list[i];
1007 >                uint32 mtspr = 0x7e4003a6 | ((spr & 0x1f) << 16) | ((spr & 0x3e0) << 6);
1008 >                uint32 mfspr = 0x7e6002a6 | ((spr & 0x1f) << 16) | ((spr & 0x3e0) << 6);
1009 >                for (int ofs = 0; ofs < 64; ofs++) {
1010 >                        if (ntohl(lp[ofs]) == mtspr) {
1011 >                                if (ntohl(lp[ofs + 2]) != mfspr)
1012 >                                        return false;
1013 >                                D(bug("  SPR%d %08lx\n", spr, base + 4*ofs));
1014 >                                lp[ofs] = htonl(POWERPC_NOP);
1015 >                                lp[ofs + 2] = htonl(POWERPC_NOP);
1016 >                        }
1017 >                }
1018 >        }
1019  
1020          // Jump to 68k emulator
1021 <        static const uint32 jump68k_ofs[] = {0x40c, 0x40c, 0x40c, 0x414, 0x438};
1022 <        lp = (uint32 *)(ROM_BASE + loc + jump68k_ofs[ROMType]);
1021 >        static const uint8 jump68k_dat[] = {0x7d, 0x92, 0x43, 0xa6, 0x7d, 0x5a, 0x03, 0xa6, 0x7d, 0x7b, 0x03, 0xa6};
1022 >        if ((loc = find_rom_data(0x310000, 0x320000, jump68k_dat, sizeof(jump68k_dat))) == 0) return false;
1023 >        static const uint8 jump68k_caller_dat[] = {0x85, 0x13, 0x00, 0x08, 0x56, 0xbf, 0x50, 0x3e, 0x63, 0xff, 0x0c, 0x00};
1024 >        if ((base = find_rom_data(0x310000, 0x320000, jump68k_caller_dat, sizeof(jump68k_caller_dat))) == 0) return false;
1025 >        if ((base = find_rom_powerpc_branch(base + 12, 0x320000, loc)) == 0) return false;
1026 >        D(bug("jump68k %08lx, called from %08lx\n", loc, base));
1027 >        lp = (uint32 *)(ROM_BASE + base);
1028          *lp++ = htonl(0x80610634);              // lwz  r3,0x0634(r1)   (pointer to Emulator Data)
1029          *lp++ = htonl(0x8081119c);              // lwz  r4,0x119c(r1)   (pointer to opcode table)
1030          *lp++ = htonl(0x80011184);              // lwz  r0,0x1184(r1)   (pointer to emulator init routine)
# Line 1019 | Line 1044 | static bool patch_68k_emul(void)
1044          uint32 base;
1045  
1046          // Overwrite twi instructions
1047 <        static const uint32 twi_loc[] = {0x36e680, 0x36e6c0, 0x36e6c0, 0x36e6c0, 0x36e740};
1048 <        base = twi_loc[ROMType];
1047 >        static const uint8 twi_dat[] = {0x0f, 0xff, 0x00, 0x00, 0x0f, 0xff, 0x00, 0x01, 0x0f, 0xff, 0x00, 0x02};
1048 >        if ((base = find_rom_data(0x36e600, 0x36ea00, twi_dat, sizeof(twi_dat))) == 0) return false;
1049 >        D(bug("twi %08lx\n", base));
1050          lp = (uint32 *)(ROM_BASE + base);
1051          *lp++ = htonl(0x48000000 + 0x36f900 - base);            // b 0x36f900 (Emulator start)
1052          *lp++ = htonl(0x48000000 + 0x36fa00 - base - 4);        // b 0x36fa00 (Mixed mode)
# Line 1080 | Line 1106 | static bool patch_68k_emul(void)
1106          lp = (uint32 *)(ROM_BASE + 0x36f900);
1107          *lp++ = htonl(0x7c2903a6);                                      // mtctr        r1
1108   #if EMULATED_PPC
1109 <        *lp++ = POWERPC_NATIVE_OP(NATIVE_DISABLE_INTERRUPT);
1109 >        *lp++ = htonl(NativeOpcode(NATIVE_DISABLE_INTERRUPT));
1110   #else
1111          *lp++ = htonl(0x80200000 + XLM_IRQ_NEST);       // lwz          r1,XLM_IRQ_NEST
1112          *lp++ = htonl(0x38210001);                                      // addi         r1,r1,1
# Line 1114 | Line 1140 | static bool patch_68k_emul(void)
1140          lp = (uint32 *)(ROM_BASE + 0x36fa00);
1141          *lp++ = htonl(0x7c2903a6);                                      // mtctr        r1
1142   #if EMULATED_PPC
1143 <        *lp++ = POWERPC_NATIVE_OP(NATIVE_DISABLE_INTERRUPT);
1143 >        *lp++ = htonl(NativeOpcode(NATIVE_DISABLE_INTERRUPT));
1144   #else
1145          *lp++ = htonl(0x80200000 + XLM_IRQ_NEST);       // lwz          r1,XLM_IRQ_NEST
1146          *lp++ = htonl(0x38210001);                                      // addi         r1,r1,1
# Line 1148 | Line 1174 | static bool patch_68k_emul(void)
1174          lp = (uint32 *)(ROM_BASE + 0x36fb00);
1175          *lp++ = htonl(0x7c2903a6);                                      // mtctr        r1
1176   #if EMULATED_PPC
1177 <        *lp++ = POWERPC_NATIVE_OP(NATIVE_DISABLE_INTERRUPT);
1177 >        *lp++ = htonl(NativeOpcode(NATIVE_DISABLE_INTERRUPT));
1178   #else
1179          *lp++ = htonl(0x80200000 + XLM_IRQ_NEST);       // lwz          r1,XLM_IRQ_NEST
1180          *lp++ = htonl(0x38210001);                                      // addi         r1,r1,1
# Line 1182 | Line 1208 | static bool patch_68k_emul(void)
1208          lp = (uint32 *)(ROM_BASE + 0x36fc00);
1209          *lp++ = htonl(0x7c2903a6);                                      // mtctr        r1
1210   #if EMULATED_PPC
1211 <        *lp++ = POWERPC_NATIVE_OP(NATIVE_DISABLE_INTERRUPT);
1211 >        *lp++ = htonl(NativeOpcode(NATIVE_DISABLE_INTERRUPT));
1212   #else
1213          *lp++ = htonl(0x80200000 + XLM_IRQ_NEST);       // lwz          r1,XLM_IRQ_NEST
1214          *lp++ = htonl(0x38210001);                                      // addi         r1,r1,1
# Line 1240 | Line 1266 | dr_found:
1266   static bool patch_nanokernel(void)
1267   {
1268          uint32 *lp;
1269 +        uint32 base, loc;
1270  
1271          // Patch Mixed Mode trap
1272 <        lp = (uint32 *)(ROM_BASE + 0x313c90);   // Don't translate virtual->physical
1273 <        while (ntohl(*lp) != 0x3ba10320) lp++;
1274 <        lp++;
1275 <        *lp++ = htonl(0x7f7fdb78);                                      // mr           r31,r27
1276 <        lp++;
1277 <        *lp = htonl(POWERPC_NOP);
1278 <
1279 <        lp = (uint32 *)(ROM_BASE + 0x313c3c);   // Don't activate PPC exception table
1280 <        while (ntohl(*lp) != 0x39010420) lp++;
1272 >        static const uint8 virt2phys_dat[] = {0x7d, 0x1b, 0x43, 0x78, 0x3b, 0xa1, 0x03, 0x20};
1273 >        if ((base = find_rom_data(0x313000, 0x314000, virt2phys_dat, sizeof(virt2phys_dat))) == 0) return false;
1274 >        D(bug("virt2phys %08lx\n", base + 8));
1275 >        lp = (uint32 *)(ROM_BASE + base + 8);   // Don't translate virtual->physical
1276 >        lp[0] = htonl(0x7f7fdb78);                                      // mr           r31,r27
1277 >        lp[2] = htonl(POWERPC_NOP);
1278 >
1279 >        static const uint8 ppc_excp_tbl_dat[] = {0x39, 0x01, 0x04, 0x20, 0x7d, 0x13, 0x43, 0xa6};
1280 >        if ((base = find_rom_data(0x313000, 0x314000, ppc_excp_tbl_dat, sizeof(ppc_excp_tbl_dat))) == 0) return false;
1281 >        D(bug("ppc_excp_tbl %08lx\n", base));
1282 >        lp = (uint32 *)(ROM_BASE + base);               // Don't activate PPC exception table
1283          *lp++ = htonl(0x39000000 + MODE_NATIVE);        // li   r8,MODE_NATIVE
1284 <        *lp = htonl(0x91000000 + XLM_RUN_MODE); // stw  r8,XLM_RUN_MODE
1284 >        *lp = htonl(0x91000000 + XLM_RUN_MODE);         // stw  r8,XLM_RUN_MODE
1285  
1286 <        lp = (uint32 *)(ROM_BASE + 0x312e88);   // Don't modify MSR to turn on FPU
1287 <        while (ntohl(*lp) != 0x556b04e2) lp++;
1288 <        lp -= 4;
1286 >        static const uint8 save_fpu_dat[] = {0x7d, 0x00, 0x00, 0xa6, 0x61, 0x08, 0x20, 0x00, 0x7d, 0x00, 0x01, 0x24};
1287 >        if ((base = find_rom_data(0x310000, 0x314000, save_fpu_dat, sizeof(save_fpu_dat))) == 0) return false;
1288 >        D(bug("save_fpu %08lx\n", base));
1289 >        lp = (uint32 *)(ROM_BASE + base);               // Don't modify MSR to turn on FPU
1290 >        if (ntohl(lp[4]) != 0x556b04e2) return false;
1291 >        loc = ROM_BASE + base;
1292 > #if 1
1293 >        // FIXME: is that really intended?
1294          *lp++ = htonl(POWERPC_NOP);
1295          lp++;
1296          *lp++ = htonl(POWERPC_NOP);
1297          lp++;
1298          *lp = htonl(POWERPC_NOP);
1299 + #else
1300 +        lp[0] = htonl(POWERPC_NOP);
1301 +        lp[1] = htonl(POWERPC_NOP);
1302 +        lp[2] = htonl(POWERPC_NOP);
1303 +        lp[3] = htonl(POWERPC_NOP);
1304 + #endif
1305  
1306 <        lp = (uint32 *)(ROM_BASE + 0x312b3c);   // Always save FPU state
1307 <        while (ntohl(*lp) != 0x81010668) lp++;
1308 <        lp--;
1306 >        static const uint8 save_fpu_caller_dat[] = {0x93, 0xa6, 0x01, 0xec, 0x93, 0xc6, 0x01, 0xf4, 0x93, 0xe6, 0x01, 0xfc, 0x40};
1307 >        if ((base = find_rom_data(0x310000, 0x314000, save_fpu_caller_dat, sizeof(save_fpu_caller_dat))) == 0) return false;
1308 >        D(bug("save_fpu_caller %08lx\n", base + 12));
1309 >        if (powerpc_branch_target(ROM_BASE + base + 12) != loc) return false;
1310 >        lp = (uint32 *)(ROM_BASE + base + 12);  // Always save FPU state
1311          *lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff));        // bl   0x00312e88
1312  
1313 <        lp = (uint32 *)(ROM_BASE + 0x312b44);   // Don't read DEC
1314 <        while (ntohl(*lp) != 0x7ff602a6) lp++;
1315 <        *lp = htonl(0x3be00000);                                        // li   r31,0
1316 <
1317 <        lp = (uint32 *)(ROM_BASE + 0x312b50);   // Don't write DEC
1276 <        while (ntohl(*lp) != 0x7d1603a6) lp++;
1313 >        static const uint8 mdec_dat[] = {0x7f, 0xf6, 0x02, 0xa6, 0x2c, 0x08, 0x00, 0x00, 0x93, 0xe1, 0x06, 0x68, 0x7d, 0x16, 0x03, 0xa6};
1314 >        if ((base = find_rom_data(0x310000, 0x314000, mdec_dat, sizeof(mdec_dat))) == 0) return false;
1315 >        D(bug("mdec %08lx\n", base));
1316 >        lp = (uint32 *)(ROM_BASE + base);               // Don't modify DEC
1317 >        lp[0] = htonl(0x3be00000);                                      // li   r31,0
1318   #if 1
1319 <        *lp++ = htonl(POWERPC_NOP);
1320 <        *lp = htonl(POWERPC_NOP);
1319 >        lp[3] = htonl(POWERPC_NOP);
1320 >        lp[4] = htonl(POWERPC_NOP);
1321   #else
1322 <        *lp++ = htonl(0x39000040);                                      // li   r8,0x40
1323 <        *lp = htonl(0x990600e4);                                        // stb  r8,0xe4(r6)
1322 >        lp[3] = htonl(0x39000040);                                      // li   r8,0x40
1323 >        lp[4] = htonl(0x990600e4);                                      // stb  r8,0xe4(r6)
1324   #endif
1325  
1326 <        lp = (uint32 *)(ROM_BASE + 0x312b9c);   // Always restore FPU state
1327 <        while (ntohl(*lp) != 0x7c00092d) lp++;
1328 <        lp--;
1326 >        static const uint8 restore_fpu_caller_dat[] = {0x81, 0x06, 0x00, 0xf4, 0x81, 0x46, 0x00, 0xfc, 0x7d, 0x09, 0x03, 0xa6, 0x40};
1327 >        if ((base = find_rom_data(0x310000, 0x314000, restore_fpu_caller_dat, sizeof(restore_fpu_caller_dat))) == 0) return false;
1328 >        D(bug("restore_fpu_caller %08lx\n", base + 12));
1329 >        lp = (uint32 *)(ROM_BASE + base + 12);  // Always restore FPU state
1330          *lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff));        // bl   0x00312ddc
1331  
1332 <        lp = (uint32 *)(ROM_BASE + 0x312a68);   // Don't activate 68k exception table
1333 <        while (ntohl(*lp) != 0x39010360) lp++;
1332 >        static const uint8 m68k_excp_tbl_dat[] = {0x81, 0x21, 0x06, 0x58, 0x39, 0x01, 0x03, 0x60, 0x7d, 0x13, 0x43, 0xa6};
1333 >        if ((base = find_rom_data(0x310000, 0x314000, m68k_excp_tbl_dat, sizeof(m68k_excp_tbl_dat))) == 0) return false;
1334 >        D(bug("m68k_excp %08lx\n", base + 4));
1335 >        lp = (uint32 *)(ROM_BASE + base + 4);   // Don't activate 68k exception table
1336          *lp++ = htonl(0x39000000 + MODE_68K);           // li   r8,MODE_68K
1337          *lp = htonl(0x91000000 + XLM_RUN_MODE);         // stw  r8,XLM_RUN_MODE
1338  
1339          // Patch 68k emulator trap routine
1340 <        lp = (uint32 *)(ROM_BASE + 0x312994);   // Always restore FPU state
1341 <        while (ntohl(*lp) != 0x39260040) lp++;
1342 <        lp--;
1340 >        static const uint8 restore_fpu_caller2_dat[] = {0x81, 0x86, 0x00, 0x8c, 0x80, 0x66, 0x00, 0x94, 0x80, 0x86, 0x00, 0x9c, 0x40};
1341 >        if ((base = find_rom_data(0x310000, 0x314000, restore_fpu_caller2_dat, sizeof(restore_fpu_caller2_dat))) == 0) return false;
1342 >        D(bug("restore_fpu_caller2 %08lx\n", base + 12));
1343 >        loc = powerpc_branch_target(ROM_BASE + base + 12) - ROM_BASE;
1344 >        lp = (uint32 *)(ROM_BASE + base + 12);  // Always restore FPU state
1345          *lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff));        // bl   0x00312dd4
1346  
1347 <        lp = (uint32 *)(ROM_BASE + 0x312dd8);   // Don't modify MSR to turn on FPU
1348 <        while (ntohl(*lp) != 0x810600e4) lp++;
1349 <        lp--;
1347 >        static const uint8 restore_fpu_dat[] = {0x55, 0x68, 0x04, 0xa5, 0x4c, 0x82, 0x00, 0x20, 0x81, 0x06, 0x00, 0xe4};
1348 >        if ((base = find_rom_data(0x310000, 0x314000, restore_fpu_dat, sizeof(restore_fpu_dat))) == 0) return false;
1349 >        D(bug("restore_fpu %08lx\n", base));
1350 >        if (base != loc) return false;
1351 >        lp = (uint32 *)(ROM_BASE + base + 4);   // Don't modify MSR to turn on FPU
1352          *lp++ = htonl(POWERPC_NOP);
1353          lp += 2;
1354          *lp++ = htonl(POWERPC_NOP);
# Line 1310 | Line 1358 | static bool patch_nanokernel(void)
1358          *lp = htonl(POWERPC_NOP);
1359  
1360          // Patch trap return routine
1361 <        lp = (uint32 *)(ROM_BASE + 0x312c20);
1362 <        while (ntohl(*lp) != 0x7d5a03a6) lp++;
1361 >        static const uint8 trap_return_dat[] = {0x80, 0xc1, 0x00, 0x18, 0x80, 0x21, 0x00, 0x04, 0x4c, 0x00, 0x00, 0x64};
1362 >        if ((base = find_rom_data(0x312000, 0x320000, trap_return_dat, sizeof(trap_return_dat))) == 0) return false;
1363 >        D(bug("trap_return %08lx\n", base + 8));
1364 >        lp = (uint32 *)(ROM_BASE + base + 8);   // Replace rfi
1365 >        *lp = htonl(POWERPC_BCTR);
1366 >
1367 >        while (ntohl(*lp) != 0x7d5a03a6) lp--;
1368          *lp++ = htonl(0x7d4903a6);                                      // mtctr        r10
1369          *lp++ = htonl(0x7daff120);                                      // mtcr r13
1370 <        *lp = htonl(0x48000000 + 0x8000 - (((uint32)lp - ROM_BASE) & 0xffff));  // b            ROM_BASE+0x318000
1371 <        uint32 xlp = ((uint32)(lp+1) - ROM_BASE) & 0xffff;
1319 <
1320 <        lp = (uint32 *)(ROM_BASE + 0x312c50);   // Replace rfi
1321 <        while (ntohl(*lp) != 0x4c000064) lp++;
1322 <        *lp = htonl(POWERPC_BCTR);
1370 >        *lp = htonl(0x48000000 + ((0x318000 - ((uint32)lp - ROM_BASE)) & 0x03fffffc));  // b            ROM_BASE+0x318000
1371 >        uint32 npc = (uint32)(lp + 1) - ROM_BASE;
1372  
1373          lp = (uint32 *)(ROM_BASE + 0x318000);
1374   #if EMULATED_PPC
1375 <        *lp++ = POWERPC_NATIVE_OP(NATIVE_ENABLE_INTERRUPT);
1376 <        *lp = htonl(0x48000000 + ((xlp - 0x8004) & 0x03fffffc));        // b            ROM_BASE+0x312c2c
1375 >        *lp++ = htonl(NativeOpcode(NATIVE_ENABLE_INTERRUPT));
1376 >        *lp = htonl(0x48000000 + ((npc - 0x318004) & 0x03fffffc));      // b            ROM_BASE+0x312c2c
1377   #else
1378          *lp++ = htonl(0x81400000 + XLM_IRQ_NEST);       // lwz  r10,XLM_IRQ_NEST
1379          *lp++ = htonl(0x394affff);                                      // subi r10,r10,1
1380          *lp++ = htonl(0x91400000 + XLM_IRQ_NEST);       // stw  r10,XLM_IRQ_NEST
1381 <        *lp = htonl(0x48000000 + ((xlp - 0x800c) & 0x03fffffc));        // b            ROM_BASE+0x312c2c
1381 >        *lp = htonl(0x48000000 + ((npc - 0x31800c) & 0x03fffffc));      // b            ROM_BASE+0x312c2c
1382   #endif
1383  
1384   /*
# Line 1351 | Line 1400 | static bool patch_68k(void)
1400          uint32 *lp;
1401          uint16 *wp;
1402          uint8 *bp;
1403 <        uint32 base;
1403 >        uint32 base, loc;
1404  
1405          // Remove 68k RESET instruction
1406          static const uint8 reset_dat[] = {0x4e, 0x70};
# Line 1401 | Line 1450 | static bool patch_68k(void)
1450                  lp[0x28 >> 2] = htonl(0x00000861);
1451                  lp[0x58 >> 2] = htonl(0x30200000);
1452                  lp[0x60 >> 2] = htonl(0x0000003d);
1453 +        } else if (ROMType == ROMTYPE_GOSSAMER) {
1454 +                base = 0x12d20;
1455 +                lp = (uint32 *)(ROM_BASE + base - 0x14);
1456 +                lp[0x00 >> 2] = htonl(ADDR_MAP_PATCH_SPACE - (base - 0x14));
1457 +                lp[0x10 >> 2] = htonl(0xcc003d11);              // Make it like the PowerMac 9500 UniversalInfo
1458 +                lp[0x14 >> 2] = htonl(0x3fff0401);
1459 +                lp[0x18 >> 2] = htonl(0x0300001c);
1460 +                lp[0x1c >> 2] = htonl(0x000108c4);
1461 +                lp[0x24 >> 2] = htonl(0xc301bf26);
1462 +                lp[0x28 >> 2] = htonl(0x00000861);
1463 +                lp[0x58 >> 2] = htonl(0x30410000);
1464 +                lp[0x60 >> 2] = htonl(0x0000003d);
1465          }
1466  
1467          // Construct AddrMap for NewWorld ROM
1468 <        if (ROMType == ROMTYPE_NEWWORLD || ROMType == ROMTYPE_ZANZIBAR) {
1468 >        if (ROMType == ROMTYPE_NEWWORLD || ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_GOSSAMER) {
1469                  lp = (uint32 *)(ROM_BASE + ADDR_MAP_PATCH_SPACE);
1470                  memset(lp - 10, 0, 0x128);
1471                  lp[-10] = htonl(0x0300001c);
# Line 1530 | Line 1591 | static bool patch_68k(void)
1591                  *wp++ = htons(M68K_EMUL_OP_XPRAM2);
1592                  *wp = htons(0x4ed3);                    // jmp  (a3)
1593  
1594 <                static const uint32 nvram3_loc[] = {0x582f0, 0xa0a0, 0x7e50, 0xa1d0, 0};
1595 <                wp = (uint16 *)(ROM_BASE + nvram3_loc[ROMType]);
1594 >                static const uint8 nvram3_dat[] = {0x4e, 0xd3, 0x06, 0x41, 0x13, 0x00};
1595 >                if ((base = find_rom_data(0x7000, 0xb000, nvram3_dat, sizeof(nvram3_dat))) == 0) return false;
1596 >                D(bug("nvram3 %08lx\n", base));
1597 >                wp = (uint16 *)(ROM_BASE + base + 2);
1598 >                *wp++ = htons(M68K_EMUL_OP_XPRAM3);
1599 >                *wp = htons(0x4ed3);                    // jmp  (a3)
1600 >
1601 >                static const uint32 nvram4_loc[] = {0x582f0, 0xa0a0, 0x7e50, 0xa1d0, 0x538d0, 0};
1602 >                wp = (uint16 *)(ROM_BASE + nvram4_loc[ROMType]);
1603                  *wp++ = htons(0x202f);                  // move.l       4(sp),d0
1604                  *wp++ = htons(0x0004);
1605                  *wp++ = htons(M68K_EMUL_OP_NVRAM1);
# Line 1544 | Line 1612 | static bool patch_68k(void)
1612                          *wp = htons(0x0004);
1613                  }
1614  
1615 <                static const uint32 nvram4_loc[] = {0x58460, 0xa0f0, 0x7f40, 0xa220, 0};
1616 <                wp = (uint16 *)(ROM_BASE + nvram4_loc[ROMType]);
1615 >                static const uint32 nvram5_loc[] = {0x58460, 0xa0f0, 0x7f40, 0xa220, 0x53a20, 0};
1616 >                wp = (uint16 *)(ROM_BASE + nvram5_loc[ROMType]);
1617                  if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_GAZELLE) {
1618                          *wp++ = htons(0x202f);                  // move.l       4(sp),d0
1619                          *wp++ = htons(0x0004);
# Line 1573 | Line 1641 | static bool patch_68k(void)
1641          *wp = htons(M68K_NOP);
1642  
1643          // Don't initialize SCC (via 0x1ac)
1644 <        static const uint8 scc_init_dat[] = {0x48, 0xe7, 0x38, 0xfe};
1645 <        if ((base = find_rom_data(0x190, 0x1f0, scc_init_dat, sizeof(scc_init_dat))) == 0) return false;
1644 >        static const uint8 scc_init_caller_dat[] = {0x21, 0xce, 0x01, 0x08, 0x22, 0x78, 0x0d, 0xd8};
1645 >        if ((base = find_rom_data(0x180, 0x1f0, scc_init_caller_dat, sizeof(scc_init_caller_dat))) == 0) return false;
1646 >        D(bug("scc_init_caller %08lx\n", base + 12));
1647 >        wp = (uint16 *)(ROM_BASE + base + 12);
1648 >        loc = ntohs(wp[1]) + ((uintptr)wp - ROM_BASE) + 2;
1649 >        static const uint8 scc_init_dat[] = {0x08, 0x38, 0x00, 0x03, 0x0d, 0xd3, 0x67, 0x12, 0x20, 0x78, 0x01, 0xdc, 0x22, 0x78, 0x01, 0xd8};
1650 >        if ((base = find_rom_data(loc, loc + 0x80, scc_init_dat, sizeof(scc_init_dat))) != loc) return false;
1651          D(bug("scc_init %08lx\n", base));
1652 <        wp = (uint16 *)(ROM_BASE + base - 2);
1580 <        wp = (uint16 *)(ROM_BASE + ntohs(*wp) + base - 2);
1652 >        wp = (uint16 *)(ROM_BASE + base);
1653          *wp++ = htons(M68K_EMUL_OP_RESET);
1654          *wp = htons(M68K_RTS);
1655  
# Line 1722 | Line 1794 | static bool patch_68k(void)
1794                  if ((base = find_rom_data(0x13000, 0x20000, gc_mask2_dat, sizeof(gc_mask2_dat))) == 0) return false;
1795                  D(bug("gc_mask2 %08lx\n", base));
1796                  wp = (uint16 *)(ROM_BASE + base);
1797 +                if (ROMType == ROMTYPE_GOSSAMER)
1798 +                        *wp++ = htons(M68K_NOP);
1799                  for (int i=0; i<5; i++) {
1800                          *wp++ = htons(M68K_NOP);
1801                          *wp++ = htons(M68K_NOP);
# Line 1729 | Line 1803 | static bool patch_68k(void)
1803                          *wp++ = htons(M68K_NOP);
1804                          wp += 2;
1805                  }
1806 <                if (ROMType == ROMTYPE_ZANZIBAR) {
1806 >                if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_GOSSAMER) {
1807                          for (int i=0; i<6; i++) {
1808                                  *wp++ = htons(M68K_NOP);
1809                                  *wp++ = htons(M68K_NOP);
# Line 1802 | Line 1876 | static bool patch_68k(void)
1876          *wp = htons(M68K_RTS);
1877  
1878          // Don't install Time Manager task for 60Hz interrupt (Enable60HzInts, via 0x2b8)
1879 <        if (ROMType == ROMTYPE_NEWWORLD) {
1879 >        if (ROMType == ROMTYPE_NEWWORLD || ROMType == ROMTYPE_GOSSAMER) {
1880                  static const uint8 tm_task_dat[] = {0x30, 0x3c, 0x4e, 0x2b, 0xa9, 0xc9};
1881 <                if ((base = find_rom_data(0x2e0, 0x320, tm_task_dat, sizeof(tm_task_dat))) == 0) return false;
1881 >                if ((base = find_rom_data(0x2a0, 0x320, tm_task_dat, sizeof(tm_task_dat))) == 0) return false;
1882                  D(bug("tm_task %08lx\n", base));
1883                  wp = (uint16 *)(ROM_BASE + base + 28);
1884                  *wp++ = htons(M68K_NOP);
# Line 1824 | Line 1898 | static bool patch_68k(void)
1898          }
1899  
1900          // Don't read PVR from 0x5fffef80 in DriverServicesLib (via 0x316)
1901 <        if (ROMType != ROMTYPE_NEWWORLD) {
1901 >        if (ROMType != ROMTYPE_NEWWORLD && ROMType != ROMTYPE_GOSSAMER) {
1902                  uint32 dsl_offset = find_rom_resource(FOURCC('n','l','i','b'), -16401);
1903                  if (ROMType == ROMTYPE_ZANZIBAR) {
1904                          static const uint8 dsl_pvr_dat[] = {0x40, 0x82, 0x00, 0x40, 0x38, 0x60, 0xef, 0x80, 0x3c, 0x63, 0x60, 0x00, 0x80, 0x83, 0x00, 0x00, 0x54, 0x84, 0x84, 0x3e};
# Line 1859 | Line 1933 | static bool patch_68k(void)
1933                  *lp = htonl(0x38600000);                // li   r3,0
1934          }
1935  
1936 +        // FIXME: Fake reading from [HpChk]+4 (the callchain reports some function from DriverServicesLib)
1937 +        if (1) {
1938 +                uint32 hpchk_offset = find_rom_resource(FOURCC('n','l','i','b'), 10);
1939 +                static const uint8 hpchk_dat[] = {0x80, 0x80, 0x03, 0x16, 0x94, 0x21, 0xff, 0xb0, 0x83, 0xc4, 0x00, 0x04};
1940 +                if ((base = find_rom_data(hpchk_offset, hpchk_offset + 0x3000, hpchk_dat, sizeof(hpchk_dat))) == 0) return false;
1941 +                D(bug("hpchk %08lx\n", base));
1942 +                lp = (uint32 *)(ROM_BASE + base);
1943 +                *lp = htonl(0x80800000 + XLM_ZERO_PAGE);                // lwz  r4,(zero page)
1944 +        }
1945 +
1946          // Patch Name Registry
1947          static const uint8 name_reg_dat[] = {0x70, 0xff, 0xab, 0xeb};
1948          if ((base = find_rom_data(0x300, 0x380, name_reg_dat, sizeof(name_reg_dat))) == 0) return false;
# Line 1910 | Line 1994 | static bool patch_68k(void)
1994                          D(bug("scsi_var2 %08lx\n", base));
1995                          wp = (uint16 *)(ROM_BASE + base);
1996                          *wp++ = htons(0x7000);  // moveq #0,d0
1997 <                        *wp = htons(M68K_RTS);  // bra
1997 >                        *wp = htons(M68K_RTS);
1998 >                }
1999 >        }
2000 >        else if (ROMType == ROMTYPE_GOSSAMER) {
2001 >                static const uint8 scsi_var_dat[] = {0x70, 0x01, 0xa0, 0x89, 0x4a, 0x6e, 0xfe, 0xac, 0x4f, 0xef, 0x00, 0x10, 0x66, 0x00};
2002 >                if ((base = find_rom_data(0x1d700, 0x1d800, scsi_var_dat, sizeof(scsi_var_dat))) != 0) {
2003 >                        D(bug("scsi_var %08lx\n", base));
2004 >                        wp = (uint16 *)(ROM_BASE + base + 12);
2005 >                        *wp = htons(0x6000);    // bra
2006 >                }
2007 >
2008 >                static const uint8 scsi_var2_dat[] = {0x4e, 0x56, 0xfc, 0x5a, 0x48, 0xe7, 0x1f, 0x38};
2009 >                if ((base = find_rom_data(0x1d900, 0x1da00, scsi_var2_dat, sizeof(scsi_var2_dat))) != 0) {
2010 >                        D(bug("scsi_var2 %08lx\n", base));
2011 >                        wp = (uint16 *)(ROM_BASE + base);
2012 >                        *wp++ = htons(0x7000);  // moveq #0,d0
2013 >                        *wp = htons(M68K_RTS);
2014                  }
2015          }
2016   #endif
# Line 1966 | Line 2066 | static bool patch_68k(void)
2066          memcpy((void *)(ROM_BASE + sony_offset + 0x200), cdrom_driver, sizeof(cdrom_driver));
2067  
2068          // Install serial drivers
2069 <        memcpy((void *)(ROM_BASE + sony_offset + 0x300), ain_driver, sizeof(ain_driver));
2070 <        memcpy((void *)(ROM_BASE + sony_offset + 0x400), aout_driver, sizeof(aout_driver));
2071 <        memcpy((void *)(ROM_BASE + sony_offset + 0x500), bin_driver, sizeof(bin_driver));
2072 <        memcpy((void *)(ROM_BASE + sony_offset + 0x600), bout_driver, sizeof(bout_driver));
2069 >        gen_ain_driver( ROM_BASE + sony_offset + 0x300);
2070 >        gen_aout_driver(ROM_BASE + sony_offset + 0x400);
2071 >        gen_bin_driver( ROM_BASE + sony_offset + 0x500);
2072 >        gen_bout_driver(ROM_BASE + sony_offset + 0x600);
2073  
2074          // Copy icons to ROM
2075          SonyDiskIconAddr = ROM_BASE + sony_offset + 0x800;
# Line 1990 | Line 2090 | static bool patch_68k(void)
2090          *wp = htons(M68K_RTS);
2091  
2092          // Don't install serial drivers from ROM
2093 <        if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_NEWWORLD) {
2093 >        if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_NEWWORLD || ROMType == ROMTYPE_GOSSAMER) {
2094                  wp = (uint16 *)(ROM_BASE + find_rom_resource(FOURCC('S','E','R','D'), 0));
2095                  *wp = htons(M68K_RTS);
2096          } else {
# Line 2171 | Line 2271 | void InstallDrivers(void)
2271   {
2272          D(bug("Installing drivers...\n"));
2273          M68kRegisters r;
2274 <        uint8 pb[SIZEOF_IOParam];
2274 >        SheepArray<SIZEOF_IOParam> pb_var;
2275 >        const uintptr pb = pb_var.addr();
2276  
2277          // Install floppy driver
2278 <        if (ROMType == ROMTYPE_NEWWORLD) {
2278 >        if (ROMType == ROMTYPE_NEWWORLD || ROMType == ROMTYPE_GOSSAMER) {
2279  
2280 <                // Force installation of floppy driver with NewWorld ROMs
2280 >                // Force installation of floppy driver with NewWorld and Gossamer ROMs
2281                  r.a[0] = ROM_BASE + sony_offset;
2282                  r.d[0] = (uint32)SonyRefNum;
2283                  Execute68kTrap(0xa43d, &r);             // DrvrInstallRsrvMem()
# Line 2189 | Line 2290 | void InstallDrivers(void)
2290  
2291   #if DISABLE_SCSI && 0
2292          // Fake SCSIGlobals
2293 <        static const uint8 fake_scsi_globals[32] = {0,};
2193 <        WriteMacInt32(0xc0c, (uint32)fake_scsi_globals);
2293 >        WriteMacInt32(0xc0c, SheepMem::ZeroPage());
2294   #endif
2295  
2296          // Open .Sony driver
2297 <        WriteMacInt8((uint32)pb + ioPermssn, 0);
2298 <        WriteMacInt32((uint32)pb + ioNamePtr, (uint32)"\005.Sony");
2299 <        r.a[0] = (uint32)pb;
2297 >        SheepString sony_str("\005.Sony");
2298 >        WriteMacInt8(pb + ioPermssn, 0);
2299 >        WriteMacInt32(pb + ioNamePtr, sony_str.addr());
2300 >        r.a[0] = pb;
2301          Execute68kTrap(0xa000, &r);             // Open()
2302  
2303          // Install disk driver
# Line 2210 | Line 2311 | void InstallDrivers(void)
2311          WriteMacInt16(dce + dCtlFlags, DiskDriverFlags);
2312  
2313          // Open disk driver
2314 <        WriteMacInt32((uint32)pb + ioNamePtr, (uint32)"\005.Disk");
2315 <        r.a[0] = (uint32)pb;
2314 >        SheepString disk_str("\005.Disk");
2315 >        WriteMacInt32(pb + ioNamePtr, disk_str.addr());
2316 >        r.a[0] = pb;
2317          Execute68kTrap(0xa000, &r);             // Open()
2318  
2319          // Install CD-ROM driver unless nocdrom option given
# Line 2228 | Line 2330 | void InstallDrivers(void)
2330                  WriteMacInt16(dce + dCtlFlags, CDROMDriverFlags);
2331  
2332                  // Open CD-ROM driver
2333 <                WriteMacInt32((uint32)pb + ioNamePtr, (uint32)"\010.AppleCD");
2334 <                r.a[0] = (uint32)pb;
2333 >                SheepString apple_cd("\010.AppleCD");
2334 >                WriteMacInt32(pb + ioNamePtr, apple_cd.addr());
2335 >                r.a[0] = pb;
2336                  Execute68kTrap(0xa000, &r);             // Open()
2337          }
2338  

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