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root/cebix/SheepShaver/src/rom_patches.cpp
Revision: 1.7
Committed: 2003-09-07T14:33:51Z (20 years, 8 months ago) by gbeauche
Branch: MAIN
Changes since 1.6: +45 -25 lines
Log Message: 
- Integrate new NativeOp instructions to be used as trampolines to call
  native functions from ppc code.
- Little endian fixes in emul_op.cpp
- Add new 'gpch' 750 patch to workaround crash with MacOS 8.6
- Don't crash in Process Manager on reset/shutdown with MacOS 8.6
- We also have an experimental interrupt thread in emulation mode

File Contents

# Content
1 /*
2 * rom_patches.cpp - ROM patches
3 *
4 * SheepShaver (C) 1997-2002 Christian Bauer and Marc Hellwig
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21 /*
22 * TODO:
23 * IRQ_NEST must be handled atomically
24 * Don't use r1 in extra routines
25 */
26
27 #include <string.h>
28
29 #include "sysdeps.h"
30 #include "rom_patches.h"
31 #include "main.h"
32 #include "prefs.h"
33 #include "cpu_emulation.h"
34 #include "emul_op.h"
35 #include "xlowmem.h"
36 #include "sony.h"
37 #include "disk.h"
38 #include "cdrom.h"
39 #include "audio.h"
40 #include "audio_defs.h"
41 #include "serial.h"
42 #include "macos_util.h"
43
44 #define DEBUG 0
45 #include "debug.h"
46
47
48 // 68k breakpoint address
49 //#define M68K_BREAK_POINT 0x29e0 // BootMe
50 //#define M68K_BREAK_POINT 0x2a1e // Boot block code returned
51 //#define M68K_BREAK_POINT 0x3150 // CritError
52 //#define M68K_BREAK_POINT 0x187ce // Unimplemented trap
53
54 // PowerPC breakpoint address
55 //#define POWERPC_BREAK_POINT 0x36e6c0 // 68k emulator start
56
57 #define DISABLE_SCSI 1
58
59
60 // Other ROM addresses
61 const uint32 CHECK_LOAD_PATCH_SPACE = 0x2f7f00;
62 const uint32 PUT_SCRAP_PATCH_SPACE = 0x2f7f80;
63 const uint32 GET_SCRAP_PATCH_SPACE = 0x2f7fc0;
64 const uint32 ADDR_MAP_PATCH_SPACE = 0x2f8000;
65
66 // Global variables
67 int ROMType; // ROM type
68 static uint32 sony_offset; // Offset of .Sony driver resource
69
70 // Prototypes
71 static bool patch_nanokernel_boot(void);
72 static bool patch_68k_emul(void);
73 static bool patch_nanokernel(void);
74 static bool patch_68k(void);
75
76
77 // Decode LZSS data
78 static void decode_lzss(const uint8 *src, uint8 *dest, int size)
79 {
80 char dict[0x1000];
81 int run_mask = 0, dict_idx = 0xfee;
82 for (;;) {
83 if (run_mask < 0x100) {
84 // Start new run
85 if (--size < 0)
86 break;
87 run_mask = *src++ | 0xff00;
88 }
89 bool bit = run_mask & 1;
90 run_mask >>= 1;
91 if (bit) {
92 // Verbatim copy
93 if (--size < 0)
94 break;
95 int c = *src++;
96 dict[dict_idx++] = c;
97 *dest++ = c;
98 dict_idx &= 0xfff;
99 } else {
100 // Copy from dictionary
101 if (--size < 0)
102 break;
103 int idx = *src++;
104 if (--size < 0)
105 break;
106 int cnt = *src++;
107 idx |= (cnt << 4) & 0xf00;
108 cnt = (cnt & 0x0f) + 3;
109 while (cnt--) {
110 char c = dict[idx++];
111 dict[dict_idx++] = c;
112 *dest++ = c;
113 idx &= 0xfff;
114 dict_idx &= 0xfff;
115 }
116 }
117 }
118 }
119
120 // Decode parcels of ROM image (MacOS 9.X and even earlier)
121 void decode_parcels(const uint8 *src, uint8 *dest, int size)
122 {
123 uint32 parcel_offset = 0x14;
124 D(bug("Offset Type Name\n"));
125 while (parcel_offset != 0) {
126 const uint32 *parcel_data = (uint32 *)(src + parcel_offset);
127 uint32 next_offset = ntohl(parcel_data[0]);
128 uint32 parcel_type = ntohl(parcel_data[1]);
129 D(bug("%08x %c%c%c%c %s\n", parcel_offset,
130 (parcel_type >> 24) & 0xff, (parcel_type >> 16) & 0xff,
131 (parcel_type >> 8) & 0xff, parcel_type & 0xff, &parcel_data[6]));
132 if (parcel_type == FOURCC('r','o','m',' ')) {
133 uint32 lzss_offset = ntohl(parcel_data[2]);
134 uint32 lzss_size = ((uint32)src + parcel_offset) - ((uint32)parcel_data + lzss_offset);
135 decode_lzss((uint8 *)parcel_data + lzss_offset, dest, lzss_size);
136 }
137 parcel_offset = next_offset;
138 }
139 }
140
141
142 /*
143 * Decode ROM image, 4 MB plain images or NewWorld images
144 */
145
146 bool DecodeROM(uint8 *data, uint32 size)
147 {
148 if (size == ROM_SIZE) {
149 // Plain ROM image
150 memcpy((void *)ROM_BASE, data, ROM_SIZE);
151 return true;
152 }
153 else if (strncmp((char *)data, "<CHRP-BOOT>", 11) == 0) {
154 // CHRP compressed ROM image
155 uint32 image_offset, image_size;
156 bool decode_info_ok = false;
157
158 char *s = strstr((char *)data, "constant lzss-offset");
159 if (s != NULL) {
160 // Probably a plain LZSS compressed ROM image
161 if (sscanf(s - 7, "%06x", &image_offset) == 1) {
162 s = strstr((char *)data, "constant lzss-size");
163 if (s != NULL && (sscanf(s - 7, "%06x", &image_size) == 1))
164 decode_info_ok = true;
165 }
166 }
167 else {
168 // Probably a MacOS 9.2.x ROM image
169 s = strstr((char *)data, "constant parcels-offset");
170 if (s != NULL) {
171 if (sscanf(s - 7, "%06x", &image_offset) == 1) {
172 s = strstr((char *)data, "constant parcels-size");
173 if (s != NULL && (sscanf(s - 7, "%06x", &image_size) == 1))
174 decode_info_ok = true;
175 }
176 }
177 }
178
179 // No valid information to decode the ROM found?
180 if (!decode_info_ok)
181 return false;
182
183 // Check signature, this could be a parcels-based ROM image
184 uint32 rom_signature = ntohl(*(uint32 *)(data + image_offset));
185 if (rom_signature == FOURCC('p','r','c','l')) {
186 D(bug("Offset of parcels data: %08x\n", image_offset));
187 D(bug("Size of parcels data: %08x\n", image_size));
188 decode_parcels(data + image_offset, (uint8 *)ROM_BASE, image_size);
189 }
190 else {
191 D(bug("Offset of compressed data: %08x\n", image_offset));
192 D(bug("Size of compressed data: %08x\n", image_size));
193 decode_lzss(data + image_offset, (uint8 *)ROM_BASE, image_size);
194 }
195 return true;
196 }
197 return false;
198 }
199
200
201 /*
202 * Search ROM for byte string, return ROM offset (or 0)
203 */
204
205 static uint32 find_rom_data(uint32 start, uint32 end, const uint8 *data, uint32 data_len)
206 {
207 uint32 ofs = start;
208 while (ofs < end) {
209 if (!memcmp((void *)(ROM_BASE + ofs), data, data_len))
210 return ofs;
211 ofs++;
212 }
213 return 0;
214 }
215
216
217 /*
218 * Search ROM resource by type/ID, return ROM offset of resource data
219 */
220
221 static uint32 rsrc_ptr = 0;
222
223 // id = 4711 means "find any ID"
224 static uint32 find_rom_resource(uint32 s_type, int16 s_id = 4711, bool cont = false)
225 {
226 uint32 *lp = (uint32 *)(ROM_BASE + 0x1a);
227 uint32 x = ntohl(*lp);
228 uint8 *bp = (uint8 *)(ROM_BASE + x + 5);
229 uint32 header_size = *bp;
230
231 if (!cont)
232 rsrc_ptr = x;
233 else if (rsrc_ptr == 0)
234 return 0;
235
236 for (;;) {
237 lp = (uint32 *)(ROM_BASE + rsrc_ptr);
238 rsrc_ptr = ntohl(*lp);
239 if (rsrc_ptr == 0)
240 break;
241
242 rsrc_ptr += header_size;
243
244 lp = (uint32 *)(ROM_BASE + rsrc_ptr + 4);
245 uint32 data = ntohl(*lp); lp++;
246 uint32 type = ntohl(*lp); lp++;
247 int16 id = ntohs(*(int16 *)lp);
248 if (type == s_type && (id == s_id || s_id == 4711))
249 return data;
250 }
251 return 0;
252 }
253
254
255 /*
256 * Search offset of A-Trap routine in ROM
257 */
258
259 static uint32 find_rom_trap(uint16 trap)
260 {
261 uint32 *lp = (uint32 *)(ROM_BASE + 0x22);
262 lp = (uint32 *)(ROM_BASE + ntohl(*lp));
263
264 if (trap > 0xa800)
265 return ntohl(lp[trap & 0x3ff]);
266 else
267 return ntohl(lp[(trap & 0xff) + 0x400]);
268 }
269
270
271 /*
272 * List of audio sifters installed in ROM and System file
273 */
274
275 struct sift_entry {
276 uint32 type;
277 int16 id;
278 };
279 static sift_entry sifter_list[32];
280 static int num_sifters;
281
282 void AddSifter(uint32 type, int16 id)
283 {
284 if (FindSifter(type, id))
285 return;
286 D(bug(" adding sifter type %c%c%c%c (%08x), id %d\n", type >> 24, (type >> 16) & 0xff, (type >> 8) & 0xff, type & 0xff, type, id));
287 sifter_list[num_sifters].type = type;
288 sifter_list[num_sifters].id = id;
289 num_sifters++;
290 }
291
292 bool FindSifter(uint32 type, int16 id)
293 {
294 for (int i=0; i<num_sifters; i++) {
295 if (sifter_list[i].type == type && sifter_list[i].id == id)
296 return true;
297 }
298 return false;
299 }
300
301
302 /*
303 * Driver stubs
304 */
305
306 static const uint8 sony_driver[] = { // Replacement for .Sony driver
307 // Driver header
308 SonyDriverFlags >> 8, SonyDriverFlags & 0xff, 0, 0, 0, 0, 0, 0,
309 0x00, 0x18, // Open() offset
310 0x00, 0x1c, // Prime() offset
311 0x00, 0x20, // Control() offset
312 0x00, 0x2c, // Status() offset
313 0x00, 0x52, // Close() offset
314 0x05, 0x2e, 0x53, 0x6f, 0x6e, 0x79, // ".Sony"
315
316 // Open()
317 M68K_EMUL_OP_SONY_OPEN >> 8, M68K_EMUL_OP_SONY_OPEN & 0xff,
318 0x4e, 0x75, // rts
319
320 // Prime()
321 M68K_EMUL_OP_SONY_PRIME >> 8, M68K_EMUL_OP_SONY_PRIME & 0xff,
322 0x60, 0x0e, // bra IOReturn
323
324 // Control()
325 M68K_EMUL_OP_SONY_CONTROL >> 8, M68K_EMUL_OP_SONY_CONTROL & 0xff,
326 0x0c, 0x68, 0x00, 0x01, 0x00, 0x1a, // cmp.w #1,$1a(a0)
327 0x66, 0x04, // bne IOReturn
328 0x4e, 0x75, // rts
329
330 // Status()
331 M68K_EMUL_OP_SONY_STATUS >> 8, M68K_EMUL_OP_SONY_STATUS & 0xff,
332
333 // IOReturn
334 0x32, 0x28, 0x00, 0x06, // move.w 6(a0),d1
335 0x08, 0x01, 0x00, 0x09, // btst #9,d1
336 0x67, 0x0c, // beq 1
337 0x4a, 0x40, // tst.w d0
338 0x6f, 0x02, // ble 2
339 0x42, 0x40, // clr.w d0
340 0x31, 0x40, 0x00, 0x10, //2 move.w d0,$10(a0)
341 0x4e, 0x75, // rts
342 0x4a, 0x40, //1 tst.w d0
343 0x6f, 0x04, // ble 3
344 0x42, 0x40, // clr.w d0
345 0x4e, 0x75, // rts
346 0x2f, 0x38, 0x08, 0xfc, //3 move.l $8fc,-(sp)
347 0x4e, 0x75, // rts
348
349 // Close()
350 0x70, 0xe8, // moveq #-24,d0
351 0x4e, 0x75 // rts
352 };
353
354 static const uint8 disk_driver[] = { // Generic disk driver
355 // Driver header
356 DiskDriverFlags >> 8, DiskDriverFlags & 0xff, 0, 0, 0, 0, 0, 0,
357 0x00, 0x18, // Open() offset
358 0x00, 0x1c, // Prime() offset
359 0x00, 0x20, // Control() offset
360 0x00, 0x2c, // Status() offset
361 0x00, 0x52, // Close() offset
362 0x05, 0x2e, 0x44, 0x69, 0x73, 0x6b, // ".Disk"
363
364 // Open()
365 M68K_EMUL_OP_DISK_OPEN >> 8, M68K_EMUL_OP_DISK_OPEN & 0xff,
366 0x4e, 0x75, // rts
367
368 // Prime()
369 M68K_EMUL_OP_DISK_PRIME >> 8, M68K_EMUL_OP_DISK_PRIME & 0xff,
370 0x60, 0x0e, // bra IOReturn
371
372 // Control()
373 M68K_EMUL_OP_DISK_CONTROL >> 8, M68K_EMUL_OP_DISK_CONTROL & 0xff,
374 0x0c, 0x68, 0x00, 0x01, 0x00, 0x1a, // cmp.w #1,$1a(a0)
375 0x66, 0x04, // bne IOReturn
376 0x4e, 0x75, // rts
377
378 // Status()
379 M68K_EMUL_OP_DISK_STATUS >> 8, M68K_EMUL_OP_DISK_STATUS & 0xff,
380
381 // IOReturn
382 0x32, 0x28, 0x00, 0x06, // move.w 6(a0),d1
383 0x08, 0x01, 0x00, 0x09, // btst #9,d1
384 0x67, 0x0c, // beq 1
385 0x4a, 0x40, // tst.w d0
386 0x6f, 0x02, // ble 2
387 0x42, 0x40, // clr.w d0
388 0x31, 0x40, 0x00, 0x10, //2 move.w d0,$10(a0)
389 0x4e, 0x75, // rts
390 0x4a, 0x40, //1 tst.w d0
391 0x6f, 0x04, // ble 3
392 0x42, 0x40, // clr.w d0
393 0x4e, 0x75, // rts
394 0x2f, 0x38, 0x08, 0xfc, //3 move.l $8fc,-(sp)
395 0x4e, 0x75, // rts
396
397 // Close()
398 0x70, 0xe8, // moveq #-24,d0
399 0x4e, 0x75 // rts
400 };
401
402 static const uint8 cdrom_driver[] = { // CD-ROM driver
403 // Driver header
404 CDROMDriverFlags >> 8, CDROMDriverFlags & 0xff, 0, 0, 0, 0, 0, 0,
405 0x00, 0x1c, // Open() offset
406 0x00, 0x20, // Prime() offset
407 0x00, 0x24, // Control() offset
408 0x00, 0x30, // Status() offset
409 0x00, 0x56, // Close() offset
410 0x08, 0x2e, 0x41, 0x70, 0x70, 0x6c, 0x65, 0x43, 0x44, 0x00, // ".AppleCD"
411
412 // Open()
413 M68K_EMUL_OP_CDROM_OPEN >> 8, M68K_EMUL_OP_CDROM_OPEN & 0xff,
414 0x4e, 0x75, // rts
415
416 // Prime()
417 M68K_EMUL_OP_CDROM_PRIME >> 8, M68K_EMUL_OP_CDROM_PRIME & 0xff,
418 0x60, 0x0e, // bra IOReturn
419
420 // Control()
421 M68K_EMUL_OP_CDROM_CONTROL >> 8, M68K_EMUL_OP_CDROM_CONTROL & 0xff,
422 0x0c, 0x68, 0x00, 0x01, 0x00, 0x1a, // cmp.w #1,$1a(a0)
423 0x66, 0x04, // bne IOReturn
424 0x4e, 0x75, // rts
425
426 // Status()
427 M68K_EMUL_OP_CDROM_STATUS >> 8, M68K_EMUL_OP_CDROM_STATUS & 0xff,
428
429 // IOReturn
430 0x32, 0x28, 0x00, 0x06, // move.w 6(a0),d1
431 0x08, 0x01, 0x00, 0x09, // btst #9,d1
432 0x67, 0x0c, // beq 1
433 0x4a, 0x40, // tst.w d0
434 0x6f, 0x02, // ble 2
435 0x42, 0x40, // clr.w d0
436 0x31, 0x40, 0x00, 0x10, //2 move.w d0,$10(a0)
437 0x4e, 0x75, // rts
438 0x4a, 0x40, //1 tst.w d0
439 0x6f, 0x04, // ble 3
440 0x42, 0x40, // clr.w d0
441 0x4e, 0x75, // rts
442 0x2f, 0x38, 0x08, 0xfc, //3 move.l $8fc,-(sp)
443 0x4e, 0x75, // rts
444
445 // Close()
446 0x70, 0xe8, // moveq #-24,d0
447 0x4e, 0x75 // rts
448 };
449
450 #if EMULATED_PPC
451 #define SERIAL_TRAMPOLINES 1
452 static uint32 serial_nothing_tvect[2] = {POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_NOTHING), 0};
453 static uint32 serial_open_tvect[2] = {POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_OPEN), 0};
454 static uint32 serial_prime_in_tvect[2] = {POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_PRIME_IN), 0};
455 static uint32 serial_prime_out_tvect[2] = {POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_PRIME_OUT), 0};
456 static uint32 serial_control_tvect[2] = {POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_CONTROL), 0};
457 static uint32 serial_status_tvect[2] = {POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_STATUS), 0};
458 static uint32 serial_close_tvect[2] = {POWERPC_NATIVE_OP_FUNC(NATIVE_SERIAL_CLOSE), 0};
459 #elif defined(__linux__)
460 #define SERIAL_TRAMPOLINES 1
461 static uint32 serial_nothing_tvect[2] = {(uint32)SerialNothing, 0};
462 static uint32 serial_open_tvect[2] = {(uint32)SerialOpen, 0};
463 static uint32 serial_prime_in_tvect[2] = {(uint32)SerialPrimeIn, 0};
464 static uint32 serial_prime_out_tvect[2] = {(uint32)SerialPrimeOut, 0};
465 static uint32 serial_control_tvect[2] = {(uint32)SerialControl, 0};
466 static uint32 serial_status_tvect[2] = {(uint32)SerialStatus, 0};
467 static uint32 serial_close_tvect[2] = {(uint32)SerialClose, 0};
468 #endif
469
470 static const uint32 ain_driver[] = { // .AIn driver header
471 0x4d000000, 0x00000000,
472 0x00200040, 0x00600080,
473 0x00a0042e, 0x41496e00,
474 0x00000000, 0x00000000,
475 0xaafe0700, 0x00000000,
476 0x00000000, 0x00179822,
477 #ifdef SERIAL_TRAMPOLINES
478 0x00010004, (uint32)serial_nothing_tvect,
479 #else
480 0x00010004, (uint32)SerialNothing,
481 #endif
482 0x00000000, 0x00000000,
483 0xaafe0700, 0x00000000,
484 0x00000000, 0x00179822,
485 #ifdef SERIAL_TRAMPOLINES
486 0x00010004, (uint32)serial_prime_in_tvect,
487 #else
488 0x00010004, (uint32)SerialPrimeIn,
489 #endif
490 0x00000000, 0x00000000,
491 0xaafe0700, 0x00000000,
492 0x00000000, 0x00179822,
493 #ifdef SERIAL_TRAMPOLINES
494 0x00010004, (uint32)serial_control_tvect,
495 #else
496 0x00010004, (uint32)SerialControl,
497 #endif
498 0x00000000, 0x00000000,
499 0xaafe0700, 0x00000000,
500 0x00000000, 0x00179822,
501 #ifdef SERIAL_TRAMPOLINES
502 0x00010004, (uint32)serial_status_tvect,
503 #else
504 0x00010004, (uint32)SerialStatus,
505 #endif
506 0x00000000, 0x00000000,
507 0xaafe0700, 0x00000000,
508 0x00000000, 0x00179822,
509 #ifdef SERIAL_TRAMPOLINES
510 0x00010004, (uint32)serial_nothing_tvect,
511 #else
512 0x00010004, (uint32)SerialNothing,
513 #endif
514 0x00000000, 0x00000000,
515 };
516
517 static const uint32 aout_driver[] = { // .AOut driver header
518 0x4d000000, 0x00000000,
519 0x00200040, 0x00600080,
520 0x00a0052e, 0x414f7574,
521 0x00000000, 0x00000000,
522 0xaafe0700, 0x00000000,
523 0x00000000, 0x00179822,
524 #ifdef SERIAL_TRAMPOLINES
525 0x00010004, (uint32)serial_open_tvect,
526 #else
527 0x00010004, (uint32)SerialOpen,
528 #endif
529 0x00000000, 0x00000000,
530 0xaafe0700, 0x00000000,
531 0x00000000, 0x00179822,
532 #ifdef SERIAL_TRAMPOLINES
533 0x00010004, (uint32)serial_prime_out_tvect,
534 #else
535 0x00010004, (uint32)SerialPrimeOut,
536 #endif
537 0x00000000, 0x00000000,
538 0xaafe0700, 0x00000000,
539 0x00000000, 0x00179822,
540 #ifdef SERIAL_TRAMPOLINES
541 0x00010004, (uint32)serial_control_tvect,
542 #else
543 0x00010004, (uint32)SerialControl,
544 #endif
545 0x00000000, 0x00000000,
546 0xaafe0700, 0x00000000,
547 0x00000000, 0x00179822,
548 #ifdef SERIAL_TRAMPOLINES
549 0x00010004, (uint32)serial_status_tvect,
550 #else
551 0x00010004, (uint32)SerialStatus,
552 #endif
553 0x00000000, 0x00000000,
554 0xaafe0700, 0x00000000,
555 0x00000000, 0x00179822,
556 #ifdef SERIAL_TRAMPOLINES
557 0x00010004, (uint32)serial_close_tvect,
558 #else
559 0x00010004, (uint32)SerialClose,
560 #endif
561 0x00000000, 0x00000000,
562 };
563
564 static const uint32 bin_driver[] = { // .BIn driver header
565 0x4d000000, 0x00000000,
566 0x00200040, 0x00600080,
567 0x00a0042e, 0x42496e00,
568 0x00000000, 0x00000000,
569 0xaafe0700, 0x00000000,
570 0x00000000, 0x00179822,
571 #ifdef SERIAL_TRAMPOLINES
572 0x00010004, (uint32)serial_nothing_tvect,
573 #else
574 0x00010004, (uint32)SerialNothing,
575 #endif
576 0x00000000, 0x00000000,
577 0xaafe0700, 0x00000000,
578 0x00000000, 0x00179822,
579 #ifdef SERIAL_TRAMPOLINES
580 0x00010004, (uint32)serial_prime_in_tvect,
581 #else
582 0x00010004, (uint32)SerialPrimeIn,
583 #endif
584 0x00000000, 0x00000000,
585 0xaafe0700, 0x00000000,
586 0x00000000, 0x00179822,
587 #ifdef SERIAL_TRAMPOLINES
588 0x00010004, (uint32)serial_control_tvect,
589 #else
590 0x00010004, (uint32)SerialControl,
591 #endif
592 0x00000000, 0x00000000,
593 0xaafe0700, 0x00000000,
594 0x00000000, 0x00179822,
595 #ifdef SERIAL_TRAMPOLINES
596 0x00010004, (uint32)serial_status_tvect,
597 #else
598 0x00010004, (uint32)SerialStatus,
599 #endif
600 0x00000000, 0x00000000,
601 0xaafe0700, 0x00000000,
602 0x00000000, 0x00179822,
603 #ifdef SERIAL_TRAMPOLINES
604 0x00010004, (uint32)serial_nothing_tvect,
605 #else
606 0x00010004, (uint32)SerialNothing,
607 #endif
608 0x00000000, 0x00000000,
609 };
610
611 static const uint32 bout_driver[] = { // .BOut driver header
612 0x4d000000, 0x00000000,
613 0x00200040, 0x00600080,
614 0x00a0052e, 0x424f7574,
615 0x00000000, 0x00000000,
616 0xaafe0700, 0x00000000,
617 0x00000000, 0x00179822,
618 #ifdef SERIAL_TRAMPOLINES
619 0x00010004, (uint32)serial_open_tvect,
620 #else
621 0x00010004, (uint32)SerialOpen,
622 #endif
623 0x00000000, 0x00000000,
624 0xaafe0700, 0x00000000,
625 0x00000000, 0x00179822,
626 #ifdef SERIAL_TRAMPOLINES
627 0x00010004, (uint32)serial_prime_out_tvect,
628 #else
629 0x00010004, (uint32)SerialPrimeOut,
630 #endif
631 0x00000000, 0x00000000,
632 0xaafe0700, 0x00000000,
633 0x00000000, 0x00179822,
634 #ifdef SERIAL_TRAMPOLINES
635 0x00010004, (uint32)serial_control_tvect,
636 #else
637 0x00010004, (uint32)SerialControl,
638 #endif
639 0x00000000, 0x00000000,
640 0xaafe0700, 0x00000000,
641 0x00000000, 0x00179822,
642 #ifdef SERIAL_TRAMPOLINES
643 0x00010004, (uint32)serial_status_tvect,
644 #else
645 0x00010004, (uint32)SerialStatus,
646 #endif
647 0x00000000, 0x00000000,
648 0xaafe0700, 0x00000000,
649 0x00000000, 0x00179822,
650 #ifdef SERIAL_TRAMPOLINES
651 0x00010004, (uint32)serial_close_tvect,
652 #else
653 0x00010004, (uint32)SerialClose,
654 #endif
655 0x00000000, 0x00000000,
656 };
657
658 static const uint8 adbop_patch[] = { // Call ADBOp() completion procedure
659 // The completion procedure may call ADBOp() again!
660 0x40, 0xe7, // move sr,-(sp)
661 0x00, 0x7c, 0x07, 0x00, // ori #$0700,sr
662 M68K_EMUL_OP_ADBOP >> 8, M68K_EMUL_OP_ADBOP & 0xff,
663 0x48, 0xe7, 0x70, 0xf0, // movem.l d1-d3/a0-a3,-(sp)
664 0x26, 0x48, // move.l a0,a3
665 0x4a, 0xab, 0x00, 0x04, // tst.l 4(a3)
666 0x67, 0x00, 0x00, 0x18, // beq 1
667 0x20, 0x53, // move.l (a3),a0
668 0x22, 0x6b, 0x00, 0x04, // move.l 4(a3),a1
669 0x24, 0x6b, 0x00, 0x08, // move.l 8(a3),a2
670 0x26, 0x78, 0x0c, 0xf8, // move.l $cf8,a3
671 0x4e, 0x91, // jsr (a1)
672 0x70, 0x00, // moveq #0,d0
673 0x60, 0x00, 0x00, 0x04, // bra 2
674 0x70, 0xff, //1 moveq #-1,d0
675 0x4c, 0xdf, 0x0f, 0x0e, //2 movem.l (sp)+,d1-d3/a0-a3
676 0x46, 0xdf, // move (sp)+,sr
677 0x4e, 0x75 // rts
678 };
679
680
681 /*
682 * Install ROM patches (RAMBase and KernelDataAddr must be set)
683 */
684
685 bool PatchROM(void)
686 {
687 // Print ROM info
688 D(bug("Checksum: %08lx\n", ntohl(*(uint32 *)ROM_BASE)));
689 D(bug("Version: %04x\n", ntohs(*(uint16 *)(ROM_BASE + 8))));
690 D(bug("Sub Version: %04x\n", ntohs(*(uint16 *)(ROM_BASE + 18))));
691 D(bug("Nanokernel ID: %s\n", (char *)ROM_BASE + 0x30d064));
692 D(bug("Resource Map at %08lx\n", ntohl(*(uint32 *)(ROM_BASE + 26))));
693 D(bug("Trap Tables at %08lx\n\n", ntohl(*(uint32 *)(ROM_BASE + 34))));
694
695 // Detect ROM type
696 if (!memcmp((void *)(ROM_BASE + 0x30d064), "Boot TNT", 8))
697 ROMType = ROMTYPE_TNT;
698 else if (!memcmp((void *)(ROM_BASE + 0x30d064), "Boot Alchemy", 12))
699 ROMType = ROMTYPE_ALCHEMY;
700 else if (!memcmp((void *)(ROM_BASE + 0x30d064), "Boot Zanzibar", 13))
701 ROMType = ROMTYPE_ZANZIBAR;
702 else if (!memcmp((void *)(ROM_BASE + 0x30d064), "Boot Gazelle", 12))
703 ROMType = ROMTYPE_GAZELLE;
704 else if (!memcmp((void *)(ROM_BASE + 0x30d064), "NewWorld", 8))
705 ROMType = ROMTYPE_NEWWORLD;
706 else
707 return false;
708
709 // Apply patches
710 if (!patch_nanokernel_boot()) return false;
711 if (!patch_68k_emul()) return false;
712 if (!patch_nanokernel()) return false;
713 if (!patch_68k()) return false;
714
715 #ifdef M68K_BREAK_POINT
716 // Install 68k breakpoint
717 uint16 *wp = (uint16 *)(ROM_BASE + M68K_BREAK_POINT);
718 *wp++ = htons(M68K_EMUL_BREAK);
719 *wp = htons(M68K_EMUL_RETURN);
720 #endif
721
722 #ifdef POWERPC_BREAK_POINT
723 // Install PowerPC breakpoint
724 uint32 *lp = (uint32 *)(ROM_BASE + POWERPC_BREAK_POINT);
725 *lp = htonl(0);
726 #endif
727
728 // Copy 68k emulator to 2MB boundary
729 memcpy((void *)(ROM_BASE + ROM_SIZE), (void *)(ROM_BASE + ROM_SIZE - 0x100000), 0x100000);
730 return true;
731 }
732
733
734 /*
735 * Nanokernel boot routine patches
736 */
737
738 static bool patch_nanokernel_boot(void)
739 {
740 uint32 *lp;
741
742 // ROM boot structure patches
743 lp = (uint32 *)(ROM_BASE + 0x30d000);
744 lp[0x9c >> 2] = htonl(KernelDataAddr); // LA_InfoRecord
745 lp[0xa0 >> 2] = htonl(KernelDataAddr); // LA_KernelData
746 lp[0xa4 >> 2] = htonl(KernelDataAddr + 0x1000); // LA_EmulatorData
747 lp[0xa8 >> 2] = htonl(ROM_BASE + 0x480000); // LA_DispatchTable
748 lp[0xac >> 2] = htonl(ROM_BASE + 0x460000); // LA_EmulatorCode
749 lp[0x360 >> 2] = htonl(0); // Physical RAM base (? on NewWorld ROM, this contains -1)
750 lp[0xfd8 >> 2] = htonl(ROM_BASE + 0x2a); // 68k reset vector
751
752 // Skip SR/BAT/SDR init
753 if (ROMType == ROMTYPE_GAZELLE || ROMType == ROMTYPE_NEWWORLD) {
754 lp = (uint32 *)(ROM_BASE + 0x310000);
755 *lp++ = htonl(POWERPC_NOP);
756 *lp = htonl(0x38000000);
757 }
758 static const uint32 sr_init_loc[] = {0x3101b0, 0x3101b0, 0x3101b0, 0x3101ec, 0x310200};
759 lp = (uint32 *)(ROM_BASE + 0x310008);
760 *lp = htonl(0x48000000 | (sr_init_loc[ROMType] - 8) & 0xffff); // b ROM_BASE+0x3101b0
761 lp = (uint32 *)(ROM_BASE + sr_init_loc[ROMType]);
762 *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA); // lwz r1,(pointer to Kernel Data)
763 *lp++ = htonl(0x3da0dead); // lis r13,0xdead (start of kernel memory)
764 *lp++ = htonl(0x3dc00010); // lis r14,0x0010 (size of page table)
765 *lp = htonl(0x3de00010); // lis r15,0x0010 (size of kernel memory)
766
767 // Don't read PVR
768 static const uint32 pvr_loc[] = {0x3103b0, 0x3103b4, 0x3103b4, 0x310400, 0x310438};
769 lp = (uint32 *)(ROM_BASE + pvr_loc[ROMType]);
770 *lp = htonl(0x81800000 + XLM_PVR); // lwz r12,(theoretical PVR)
771
772 // Set CPU specific data (even if ROM doesn't have support for that CPU)
773 lp = (uint32 *)(ROM_BASE + pvr_loc[ROMType]);
774 if (ntohl(lp[6]) != 0x2c0c0001)
775 return false;
776 uint32 ofs = ntohl(lp[7]) & 0xffff;
777 D(bug("ofs %08lx\n", ofs));
778 lp[8] = htonl((ntohl(lp[8]) & 0xffff) | 0x48000000); // beq -> b
779 uint32 loc = (ntohl(lp[8]) & 0xffff) + (uint32)(lp+8) - ROM_BASE;
780 D(bug("loc %08lx\n", loc));
781 lp = (uint32 *)(ROM_BASE + ofs + 0x310000);
782 switch (PVR >> 16) {
783 case 1: // 601
784 lp[0] = htonl(0x1000); // Page size
785 lp[1] = htonl(0x8000); // Data cache size
786 lp[2] = htonl(0x8000); // Inst cache size
787 lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
788 lp[4] = htonl(0x00010040); // Unified caches/Inst cache line size
789 lp[5] = htonl(0x00400020); // Data cache line size/Data cache block size touch
790 lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
791 lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc
792 lp[8] = htonl(0x01000002); // TLB total size/TLB assoc
793 break;
794 case 3: // 603
795 lp[0] = htonl(0x1000); // Page size
796 lp[1] = htonl(0x2000); // Data cache size
797 lp[2] = htonl(0x2000); // Inst cache size
798 lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
799 lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
800 lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
801 lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
802 lp[7] = htonl(0x00020002); // Inst cache assoc/Data cache assoc
803 lp[8] = htonl(0x00400002); // TLB total size/TLB assoc
804 break;
805 case 4: // 604
806 lp[0] = htonl(0x1000); // Page size
807 lp[1] = htonl(0x4000); // Data cache size
808 lp[2] = htonl(0x4000); // Inst cache size
809 lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
810 lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
811 lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
812 lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
813 lp[7] = htonl(0x00040004); // Inst cache assoc/Data cache assoc
814 lp[8] = htonl(0x00800002); // TLB total size/TLB assoc
815 break;
816 // case 5: // 740?
817 case 6: // 603e
818 case 7: // 603ev
819 lp[0] = htonl(0x1000); // Page size
820 lp[1] = htonl(0x4000); // Data cache size
821 lp[2] = htonl(0x4000); // Inst cache size
822 lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
823 lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
824 lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
825 lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
826 lp[7] = htonl(0x00040004); // Inst cache assoc/Data cache assoc
827 lp[8] = htonl(0x00400002); // TLB total size/TLB assoc
828 break;
829 case 8: // 750
830 lp[0] = htonl(0x1000); // Page size
831 lp[1] = htonl(0x8000); // Data cache size
832 lp[2] = htonl(0x8000); // Inst cache size
833 lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
834 lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
835 lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
836 lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
837 lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc
838 lp[8] = htonl(0x00800002); // TLB total size/TLB assoc
839 break;
840 case 9: // 604e
841 case 10: // 604ev5
842 lp[0] = htonl(0x1000); // Page size
843 lp[1] = htonl(0x8000); // Data cache size
844 lp[2] = htonl(0x8000); // Inst cache size
845 lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
846 lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
847 lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
848 lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
849 lp[7] = htonl(0x00040004); // Inst cache assoc/Data cache assoc
850 lp[8] = htonl(0x00800002); // TLB total size/TLB assoc
851 break;
852 // case 11: // X704?
853 case 12: // ???
854 lp[0] = htonl(0x1000); // Page size
855 lp[1] = htonl(0x8000); // Data cache size
856 lp[2] = htonl(0x8000); // Inst cache size
857 lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
858 lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
859 lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
860 lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
861 lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc
862 lp[8] = htonl(0x00800002); // TLB total size/TLB assoc
863 break;
864 case 13: // ???
865 lp[0] = htonl(0x1000); // Page size
866 lp[1] = htonl(0x8000); // Data cache size
867 lp[2] = htonl(0x8000); // Inst cache size
868 lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
869 lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
870 lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
871 lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
872 lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc
873 lp[8] = htonl(0x01000004); // TLB total size/TLB assoc
874 break;
875 // case 50: // 821
876 // case 80: // 860
877 case 96: // ???
878 lp[0] = htonl(0x1000); // Page size
879 lp[1] = htonl(0x8000); // Data cache size
880 lp[2] = htonl(0x8000); // Inst cache size
881 lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
882 lp[4] = htonl(0x00010020); // Unified caches/Inst cache line size
883 lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
884 lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
885 lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc
886 lp[8] = htonl(0x00800004); // TLB total size/TLB assoc
887 break;
888 default:
889 printf("WARNING: Unknown CPU type\n");
890 break;
891 }
892
893 // Don't set SPRG3, don't test MQ
894 lp = (uint32 *)(ROM_BASE + loc + 0x20);
895 *lp++ = htonl(POWERPC_NOP);
896 lp++;
897 *lp++ = htonl(POWERPC_NOP);
898 lp++;
899 *lp = htonl(POWERPC_NOP);
900
901 // Don't read MSR
902 lp = (uint32 *)(ROM_BASE + loc + 0x40);
903 *lp = htonl(0x39c00000); // li r14,0
904
905 // Don't write to DEC
906 lp = (uint32 *)(ROM_BASE + loc + 0x70);
907 *lp++ = htonl(POWERPC_NOP);
908 loc = (ntohl(lp[0]) & 0xffff) + (uint32)lp - ROM_BASE;
909 D(bug("loc %08lx\n", loc));
910
911 // Don't set SPRG3
912 lp = (uint32 *)(ROM_BASE + loc + 0x2c);
913 *lp = htonl(POWERPC_NOP);
914
915 // Don't read PVR
916 static const uint32 pvr_ofs[] = {0x138, 0x138, 0x138, 0x140, 0x148};
917 lp = (uint32 *)(ROM_BASE + loc + pvr_ofs[ROMType]);
918 *lp = htonl(0x82e00000 + XLM_PVR); // lwz r23,(theoretical PVR)
919 lp = (uint32 *)(ROM_BASE + loc + 0x170);
920 if (ntohl(*lp) == 0x7eff42a6) // NewWorld ROM
921 *lp = htonl(0x82e00000 + XLM_PVR); // lwz r23,(theoretical PVR)
922 lp = (uint32 *)(ROM_BASE + 0x313134);
923 if (ntohl(*lp) == 0x7e5f42a6)
924 *lp = htonl(0x82400000 + XLM_PVR); // lwz r18,(theoretical PVR)
925 lp = (uint32 *)(ROM_BASE + 0x3131f4);
926 if (ntohl(*lp) == 0x7e5f42a6) // NewWorld ROM
927 *lp = htonl(0x82400000 + XLM_PVR); // lwz r18,(theoretical PVR)
928 lp = (uint32 *)(ROM_BASE + 0x314600);
929 if (ntohl(*lp) == 0x7d3f42a6)
930 *lp = htonl(0x81200000 + XLM_PVR); // lzw r9,(theoritical PVR)
931
932 // Don't read SDR1
933 static const uint32 sdr1_ofs[] = {0x174, 0x174, 0x174, 0x17c, 0x19c};
934 lp = (uint32 *)(ROM_BASE + loc + sdr1_ofs[ROMType]);
935 *lp++ = htonl(0x3d00dead); // lis r8,0xdead (pointer to page table)
936 *lp++ = htonl(0x3ec0001f); // lis r22,0x001f (size of page table)
937 *lp = htonl(POWERPC_NOP);
938
939 // Don't clear page table
940 static const uint32 pgtb_ofs[] = {0x198, 0x198, 0x198, 0x1a0, 0x1c4};
941 lp = (uint32 *)(ROM_BASE + loc + pgtb_ofs[ROMType]);
942 *lp = htonl(POWERPC_NOP);
943
944 // Don't invalidate TLB
945 static const uint32 tlb_ofs[] = {0x1a0, 0x1a0, 0x1a0, 0x1a8, 0x1cc};
946 lp = (uint32 *)(ROM_BASE + loc + tlb_ofs[ROMType]);
947 *lp = htonl(POWERPC_NOP);
948
949 // Don't create RAM descriptor table
950 static const uint32 desc_ofs[] = {0x350, 0x350, 0x350, 0x358, 0x37c};
951 lp = (uint32 *)(ROM_BASE + loc + desc_ofs[ROMType]);
952 *lp = htonl(POWERPC_NOP);
953
954 // Don't load SRs and BATs
955 static const uint32 sr_ofs[] = {0x3d8, 0x3d8, 0x3d8, 0x3e0, 0x404};
956 lp = (uint32 *)(ROM_BASE + loc + sr_ofs[ROMType]);
957 *lp = htonl(POWERPC_NOP);
958
959 // Don't mess with SRs
960 static const uint32 sr2_ofs[] = {0x312118, 0x312118, 0x312118, 0x312118, 0x3121b4};
961 lp = (uint32 *)(ROM_BASE + sr2_ofs[ROMType]);
962 *lp = htonl(POWERPC_BLR);
963
964 // Don't check performance monitor
965 static const uint32 pm_ofs[] = {0x313148, 0x313148, 0x313148, 0x313148, 0x313218};
966 lp = (uint32 *)(ROM_BASE + pm_ofs[ROMType]);
967 while (ntohl(*lp) != 0x7e58eba6) lp++;
968 *lp++ = htonl(POWERPC_NOP);
969 while (ntohl(*lp) != 0x7e78eaa6) lp++;
970 *lp++ = htonl(POWERPC_NOP);
971 while (ntohl(*lp) != 0x7e59eba6) lp++;
972 *lp++ = htonl(POWERPC_NOP);
973 while (ntohl(*lp) != 0x7e79eaa6) lp++;
974 *lp++ = htonl(POWERPC_NOP);
975 while (ntohl(*lp) != 0x7e5aeba6) lp++;
976 *lp++ = htonl(POWERPC_NOP);
977 while (ntohl(*lp) != 0x7e7aeaa6) lp++;
978 *lp++ = htonl(POWERPC_NOP);
979 while (ntohl(*lp) != 0x7e5beba6) lp++;
980 *lp++ = htonl(POWERPC_NOP);
981 while (ntohl(*lp) != 0x7e7beaa6) lp++;
982 *lp++ = htonl(POWERPC_NOP);
983 while (ntohl(*lp) != 0x7e5feba6) lp++;
984 *lp++ = htonl(POWERPC_NOP);
985 while (ntohl(*lp) != 0x7e7feaa6) lp++;
986 *lp++ = htonl(POWERPC_NOP);
987 while (ntohl(*lp) != 0x7e5ceba6) lp++;
988 *lp++ = htonl(POWERPC_NOP);
989 while (ntohl(*lp) != 0x7e7ceaa6) lp++;
990 *lp++ = htonl(POWERPC_NOP);
991 while (ntohl(*lp) != 0x7e5deba6) lp++;
992 *lp++ = htonl(POWERPC_NOP);
993 while (ntohl(*lp) != 0x7e7deaa6) lp++;
994 *lp++ = htonl(POWERPC_NOP);
995 while (ntohl(*lp) != 0x7e5eeba6) lp++;
996 *lp++ = htonl(POWERPC_NOP);
997 while (ntohl(*lp) != 0x7e7eeaa6) lp++;
998 *lp++ = htonl(POWERPC_NOP);
999
1000 // Jump to 68k emulator
1001 static const uint32 jump68k_ofs[] = {0x40c, 0x40c, 0x40c, 0x414, 0x438};
1002 lp = (uint32 *)(ROM_BASE + loc + jump68k_ofs[ROMType]);
1003 *lp++ = htonl(0x80610634); // lwz r3,0x0634(r1) (pointer to Emulator Data)
1004 *lp++ = htonl(0x8081119c); // lwz r4,0x119c(r1) (pointer to opcode table)
1005 *lp++ = htonl(0x80011184); // lwz r0,0x1184(r1) (pointer to emulator init routine)
1006 *lp++ = htonl(0x7c0903a6); // mtctr r0
1007 *lp = htonl(POWERPC_BCTR);
1008 return true;
1009 }
1010
1011
1012 /*
1013 * 68k emulator patches
1014 */
1015
1016 static bool patch_68k_emul(void)
1017 {
1018 uint32 *lp;
1019 uint32 base;
1020
1021 // Overwrite twi instructions
1022 static const uint32 twi_loc[] = {0x36e680, 0x36e6c0, 0x36e6c0, 0x36e6c0, 0x36e740};
1023 base = twi_loc[ROMType];
1024 lp = (uint32 *)(ROM_BASE + base);
1025 *lp++ = htonl(0x48000000 + 0x36f900 - base); // b 0x36f900 (Emulator start)
1026 *lp++ = htonl(0x48000000 + 0x36fa00 - base - 4); // b 0x36fa00 (Mixed mode)
1027 *lp++ = htonl(0x48000000 + 0x36fb00 - base - 8); // b 0x36fb00 (Reset/FC1E opcode)
1028 *lp++ = htonl(0x48000000 + 0x36fc00 - base - 12); // FE0A opcode
1029 *lp++ = htonl(POWERPC_ILLEGAL); // Interrupt
1030 *lp++ = htonl(POWERPC_ILLEGAL); // ?
1031 *lp++ = htonl(POWERPC_ILLEGAL);
1032 *lp++ = htonl(POWERPC_ILLEGAL);
1033 *lp++ = htonl(POWERPC_ILLEGAL);
1034 *lp++ = htonl(POWERPC_ILLEGAL);
1035 *lp++ = htonl(POWERPC_ILLEGAL);
1036 *lp++ = htonl(POWERPC_ILLEGAL);
1037 *lp++ = htonl(POWERPC_ILLEGAL);
1038 *lp++ = htonl(POWERPC_ILLEGAL);
1039 *lp++ = htonl(POWERPC_ILLEGAL);
1040 *lp = htonl(POWERPC_ILLEGAL);
1041
1042 #if EMULATED_PPC
1043 // Install EMUL_RETURN, EXEC_RETURN, EXEC_NATIVE and EMUL_OP opcodes
1044 lp = (uint32 *)(ROM_BASE + 0x380000 + (M68K_EMUL_RETURN << 3));
1045 *lp++ = htonl(POWERPC_EMUL_OP);
1046 *lp++ = htonl(0x4bf66e80); // b 0x366084
1047 *lp++ = htonl(POWERPC_EMUL_OP | 1);
1048 *lp++ = htonl(0x4bf66e78); // b 0x366084
1049 *lp++ = htonl(POWERPC_EMUL_OP | 2);
1050 *lp++ = htonl(0x4bf66e70); // b 0x366084
1051 for (int i=0; i<OP_MAX; i++) {
1052 *lp++ = htonl(POWERPC_EMUL_OP | (i + 3));
1053 *lp++ = htonl(0x4bf66e68 - i*8); // b 0x366084
1054 }
1055 #else
1056 // Install EMUL_RETURN, EXEC_RETURN and EMUL_OP opcodes
1057 lp = (uint32 *)(ROM_BASE + 0x380000 + (M68K_EMUL_RETURN << 3));
1058 *lp++ = htonl(0x80000000 + XLM_EMUL_RETURN_PROC); // lwz r0,XLM_EMUL_RETURN_PROC
1059 *lp++ = htonl(0x4bf705fc); // b 0x36f800
1060 *lp++ = htonl(0x80000000 + XLM_EXEC_RETURN_PROC); // lwz r0,XLM_EXEC_RETURN_PROC
1061 *lp++ = htonl(0x4bf705f4); // b 0x36f800
1062 *lp++ = htonl(0x00dead00); // Let SheepShaver crash, since
1063 *lp++ = htonl(0x00beef00); // no native opcode is available
1064 for (int i=0; i<OP_MAX; i++) {
1065 *lp++ = htonl(0x38a00000 + i); // li r5,OP_*
1066 *lp++ = htonl(0x4bf705ec - i*8); // b 0x36f808
1067 }
1068
1069 // Extra routines for EMUL_RETURN/EXEC_RETURN/EMUL_OP
1070 lp = (uint32 *)(ROM_BASE + 0x36f800);
1071 *lp++ = htonl(0x7c0803a6); // mtlr r0
1072 *lp++ = htonl(0x4e800020); // blr
1073
1074 *lp++ = htonl(0x80000000 + XLM_EMUL_OP_PROC); // lwz r0,XLM_EMUL_OP_PROC
1075 *lp++ = htonl(0x7c0803a6); // mtlr r0
1076 *lp = htonl(0x4e800020); // blr
1077 #endif
1078
1079 // Extra routine for 68k emulator start
1080 lp = (uint32 *)(ROM_BASE + 0x36f900);
1081 *lp++ = htonl(0x7c2903a6); // mtctr r1
1082 *lp++ = htonl(0x80200000 + XLM_IRQ_NEST); // lwz r1,XLM_IRQ_NEST
1083 *lp++ = htonl(0x38210001); // addi r1,r1,1
1084 *lp++ = htonl(0x90200000 + XLM_IRQ_NEST); // stw r1,XLM_IRQ_NEST
1085 *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz r1,XLM_KERNEL_DATA
1086 *lp++ = htonl(0x90c10018); // stw r6,0x18(r1)
1087 *lp++ = htonl(0x7cc902a6); // mfctr r6
1088 *lp++ = htonl(0x90c10004); // stw r6,$0004(r1)
1089 *lp++ = htonl(0x80c1065c); // lwz r6,$065c(r1)
1090 *lp++ = htonl(0x90e6013c); // stw r7,$013c(r6)
1091 *lp++ = htonl(0x91060144); // stw r8,$0144(r6)
1092 *lp++ = htonl(0x9126014c); // stw r9,$014c(r6)
1093 *lp++ = htonl(0x91460154); // stw r10,$0154(r6)
1094 *lp++ = htonl(0x9166015c); // stw r11,$015c(r6)
1095 *lp++ = htonl(0x91860164); // stw r12,$0164(r6)
1096 *lp++ = htonl(0x91a6016c); // stw r13,$016c(r6)
1097 *lp++ = htonl(0x7da00026); // mfcr r13
1098 *lp++ = htonl(0x80e10660); // lwz r7,$0660(r1)
1099 *lp++ = htonl(0x7d8802a6); // mflr r12
1100 *lp++ = htonl(0x50e74001); // rlwimi. r7,r7,8,$80000000
1101 *lp++ = htonl(0x814105f0); // lwz r10,0x05f0(r1)
1102 *lp++ = htonl(0x7d4803a6); // mtlr r10
1103 *lp++ = htonl(0x7d8a6378); // mr r10,r12
1104 *lp++ = htonl(0x3d600002); // lis r11,0x0002
1105 *lp++ = htonl(0x616bf072); // ori r11,r11,0xf072 (MSR)
1106 *lp++ = htonl(0x50e7deb4); // rlwimi r7,r7,27,$00000020
1107 *lp = htonl(0x4e800020); // blr
1108
1109 // Extra routine for Mixed Mode
1110 lp = (uint32 *)(ROM_BASE + 0x36fa00);
1111 *lp++ = htonl(0x7c2903a6); // mtctr r1
1112 *lp++ = htonl(0x80200000 + XLM_IRQ_NEST); // lwz r1,XLM_IRQ_NEST
1113 *lp++ = htonl(0x38210001); // addi r1,r1,1
1114 *lp++ = htonl(0x90200000 + XLM_IRQ_NEST); // stw r1,XLM_IRQ_NEST
1115 *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz r1,XLM_KERNEL_DATA
1116 *lp++ = htonl(0x90c10018); // stw r6,0x18(r1)
1117 *lp++ = htonl(0x7cc902a6); // mfctr r6
1118 *lp++ = htonl(0x90c10004); // stw r6,$0004(r1)
1119 *lp++ = htonl(0x80c1065c); // lwz r6,$065c(r1)
1120 *lp++ = htonl(0x90e6013c); // stw r7,$013c(r6)
1121 *lp++ = htonl(0x91060144); // stw r8,$0144(r6)
1122 *lp++ = htonl(0x9126014c); // stw r9,$014c(r6)
1123 *lp++ = htonl(0x91460154); // stw r10,$0154(r6)
1124 *lp++ = htonl(0x9166015c); // stw r11,$015c(r6)
1125 *lp++ = htonl(0x91860164); // stw r12,$0164(r6)
1126 *lp++ = htonl(0x91a6016c); // stw r13,$016c(r6)
1127 *lp++ = htonl(0x7da00026); // mfcr r13
1128 *lp++ = htonl(0x80e10660); // lwz r7,$0660(r1)
1129 *lp++ = htonl(0x7d8802a6); // mflr r12
1130 *lp++ = htonl(0x50e74001); // rlwimi. r7,r7,8,$80000000
1131 *lp++ = htonl(0x814105f4); // lwz r10,0x05f4(r1)
1132 *lp++ = htonl(0x7d4803a6); // mtlr r10
1133 *lp++ = htonl(0x7d8a6378); // mr r10,r12
1134 *lp++ = htonl(0x3d600002); // lis r11,0x0002
1135 *lp++ = htonl(0x616bf072); // ori r11,r11,0xf072 (MSR)
1136 *lp++ = htonl(0x50e7deb4); // rlwimi r7,r7,27,$00000020
1137 *lp = htonl(0x4e800020); // blr
1138
1139 // Extra routine for Reset/FC1E opcode
1140 lp = (uint32 *)(ROM_BASE + 0x36fb00);
1141 *lp++ = htonl(0x7c2903a6); // mtctr r1
1142 *lp++ = htonl(0x80200000 + XLM_IRQ_NEST); // lwz r1,XLM_IRQ_NEST
1143 *lp++ = htonl(0x38210001); // addi r1,r1,1
1144 *lp++ = htonl(0x90200000 + XLM_IRQ_NEST); // stw r1,XLM_IRQ_NEST
1145 *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz r1,XLM_KERNEL_DATA
1146 *lp++ = htonl(0x90c10018); // stw r6,0x18(r1)
1147 *lp++ = htonl(0x7cc902a6); // mfctr r6
1148 *lp++ = htonl(0x90c10004); // stw r6,$0004(r1)
1149 *lp++ = htonl(0x80c1065c); // lwz r6,$065c(r1)
1150 *lp++ = htonl(0x90e6013c); // stw r7,$013c(r6)
1151 *lp++ = htonl(0x91060144); // stw r8,$0144(r6)
1152 *lp++ = htonl(0x9126014c); // stw r9,$014c(r6)
1153 *lp++ = htonl(0x91460154); // stw r10,$0154(r6)
1154 *lp++ = htonl(0x9166015c); // stw r11,$015c(r6)
1155 *lp++ = htonl(0x91860164); // stw r12,$0164(r6)
1156 *lp++ = htonl(0x91a6016c); // stw r13,$016c(r6)
1157 *lp++ = htonl(0x7da00026); // mfcr r13
1158 *lp++ = htonl(0x80e10660); // lwz r7,$0660(r1)
1159 *lp++ = htonl(0x7d8802a6); // mflr r12
1160 *lp++ = htonl(0x50e74001); // rlwimi. r7,r7,8,$80000000
1161 *lp++ = htonl(0x814105f8); // lwz r10,0x05f8(r1)
1162 *lp++ = htonl(0x7d4803a6); // mtlr r10
1163 *lp++ = htonl(0x7d8a6378); // mr r10,r12
1164 *lp++ = htonl(0x3d600002); // lis r11,0x0002
1165 *lp++ = htonl(0x616bf072); // ori r11,r11,0xf072 (MSR)
1166 *lp++ = htonl(0x50e7deb4); // rlwimi r7,r7,27,$00000020
1167 *lp = htonl(0x4e800020); // blr
1168
1169 // Extra routine for FE0A opcode (QuickDraw 3D needs this)
1170 lp = (uint32 *)(ROM_BASE + 0x36fc00);
1171 *lp++ = htonl(0x7c2903a6); // mtctr r1
1172 *lp++ = htonl(0x80200000 + XLM_IRQ_NEST); // lwz r1,XLM_IRQ_NEST
1173 *lp++ = htonl(0x38210001); // addi r1,r1,1
1174 *lp++ = htonl(0x90200000 + XLM_IRQ_NEST); // stw r1,XLM_IRQ_NEST
1175 *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz r1,XLM_KERNEL_DATA
1176 *lp++ = htonl(0x90c10018); // stw r6,0x18(r1)
1177 *lp++ = htonl(0x7cc902a6); // mfctr r6
1178 *lp++ = htonl(0x90c10004); // stw r6,$0004(r1)
1179 *lp++ = htonl(0x80c1065c); // lwz r6,$065c(r1)
1180 *lp++ = htonl(0x90e6013c); // stw r7,$013c(r6)
1181 *lp++ = htonl(0x91060144); // stw r8,$0144(r6)
1182 *lp++ = htonl(0x9126014c); // stw r9,$014c(r6)
1183 *lp++ = htonl(0x91460154); // stw r10,$0154(r6)
1184 *lp++ = htonl(0x9166015c); // stw r11,$015c(r6)
1185 *lp++ = htonl(0x91860164); // stw r12,$0164(r6)
1186 *lp++ = htonl(0x91a6016c); // stw r13,$016c(r6)
1187 *lp++ = htonl(0x7da00026); // mfcr r13
1188 *lp++ = htonl(0x80e10660); // lwz r7,$0660(r1)
1189 *lp++ = htonl(0x7d8802a6); // mflr r12
1190 *lp++ = htonl(0x50e74001); // rlwimi. r7,r7,8,$80000000
1191 *lp++ = htonl(0x814105fc); // lwz r10,0x05fc(r1)
1192 *lp++ = htonl(0x7d4803a6); // mtlr r10
1193 *lp++ = htonl(0x7d8a6378); // mr r10,r12
1194 *lp++ = htonl(0x3d600002); // lis r11,0x0002
1195 *lp++ = htonl(0x616bf072); // ori r11,r11,0xf072 (MSR)
1196 *lp++ = htonl(0x50e7deb4); // rlwimi r7,r7,27,$00000020
1197 *lp = htonl(0x4e800020); // blr
1198
1199 // Patch DR emulator to jump to right address when an interrupt occurs
1200 lp = (uint32 *)(ROM_BASE + 0x370000);
1201 while (lp < (uint32 *)(ROM_BASE + 0x380000)) {
1202 if (ntohl(*lp) == 0x4ca80020) // bclr 5,8
1203 goto dr_found;
1204 lp++;
1205 }
1206 D(bug("DR emulator patch location not found\n"));
1207 return false;
1208 dr_found:
1209 lp++;
1210 *lp = htonl(0x48000000 + 0xf000 - (((uint32)lp - ROM_BASE) & 0xffff)); // b DR_CACHE_BASE+0x1f000
1211 lp = (uint32 *)(ROM_BASE + 0x37f000);
1212 *lp++ = htonl(0x3c000000 + ((ROM_BASE + 0x46d0a4) >> 16)); // lis r0,xxx
1213 *lp++ = htonl(0x60000000 + ((ROM_BASE + 0x46d0a4) & 0xffff)); // ori r0,r0,xxx
1214 *lp++ = htonl(0x7c0903a6); // mtctr r0
1215 *lp = htonl(POWERPC_BCTR); // bctr
1216 return true;
1217 }
1218
1219
1220 /*
1221 * Nanokernel patches
1222 */
1223
1224 static bool patch_nanokernel(void)
1225 {
1226 uint32 *lp;
1227
1228 // Patch Mixed Mode trap
1229 lp = (uint32 *)(ROM_BASE + 0x313c90); // Don't translate virtual->physical
1230 while (ntohl(*lp) != 0x3ba10320) lp++;
1231 lp++;
1232 *lp++ = htonl(0x7f7fdb78); // mr r31,r27
1233 lp++;
1234 *lp = htonl(POWERPC_NOP);
1235
1236 lp = (uint32 *)(ROM_BASE + 0x313c3c); // Don't activate PPC exception table
1237 while (ntohl(*lp) != 0x39010420) lp++;
1238 *lp++ = htonl(0x39000000 + MODE_NATIVE); // li r8,MODE_NATIVE
1239 *lp = htonl(0x91000000 + XLM_RUN_MODE); // stw r8,XLM_RUN_MODE
1240
1241 lp = (uint32 *)(ROM_BASE + 0x312e88); // Don't modify MSR to turn on FPU
1242 while (ntohl(*lp) != 0x556b04e2) lp++;
1243 lp -= 4;
1244 *lp++ = htonl(POWERPC_NOP);
1245 lp++;
1246 *lp++ = htonl(POWERPC_NOP);
1247 lp++;
1248 *lp = htonl(POWERPC_NOP);
1249
1250 lp = (uint32 *)(ROM_BASE + 0x312b3c); // Always save FPU state
1251 while (ntohl(*lp) != 0x81010668) lp++;
1252 lp--;
1253 *lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff)); // bl 0x00312e88
1254
1255 lp = (uint32 *)(ROM_BASE + 0x312b44); // Don't read DEC
1256 while (ntohl(*lp) != 0x7ff602a6) lp++;
1257 *lp = htonl(0x3be00000); // li r31,0
1258
1259 lp = (uint32 *)(ROM_BASE + 0x312b50); // Don't write DEC
1260 while (ntohl(*lp) != 0x7d1603a6) lp++;
1261 #if 1
1262 *lp++ = htonl(POWERPC_NOP);
1263 *lp = htonl(POWERPC_NOP);
1264 #else
1265 *lp++ = htonl(0x39000040); // li r8,0x40
1266 *lp = htonl(0x990600e4); // stb r8,0xe4(r6)
1267 #endif
1268
1269 lp = (uint32 *)(ROM_BASE + 0x312b9c); // Always restore FPU state
1270 while (ntohl(*lp) != 0x7c00092d) lp++;
1271 lp--;
1272 *lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff)); // bl 0x00312ddc
1273
1274 lp = (uint32 *)(ROM_BASE + 0x312a68); // Don't activate 68k exception table
1275 while (ntohl(*lp) != 0x39010360) lp++;
1276 *lp++ = htonl(0x39000000 + MODE_68K); // li r8,MODE_68K
1277 *lp = htonl(0x91000000 + XLM_RUN_MODE); // stw r8,XLM_RUN_MODE
1278
1279 // Patch 68k emulator trap routine
1280 lp = (uint32 *)(ROM_BASE + 0x312994); // Always restore FPU state
1281 while (ntohl(*lp) != 0x39260040) lp++;
1282 lp--;
1283 *lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff)); // bl 0x00312dd4
1284
1285 lp = (uint32 *)(ROM_BASE + 0x312dd8); // Don't modify MSR to turn on FPU
1286 while (ntohl(*lp) != 0x810600e4) lp++;
1287 lp--;
1288 *lp++ = htonl(POWERPC_NOP);
1289 lp += 2;
1290 *lp++ = htonl(POWERPC_NOP);
1291 lp++;
1292 *lp++ = htonl(POWERPC_NOP);
1293 *lp++ = htonl(POWERPC_NOP);
1294 *lp = htonl(POWERPC_NOP);
1295
1296 // Patch trap return routine
1297 lp = (uint32 *)(ROM_BASE + 0x312c20);
1298 while (ntohl(*lp) != 0x7d5a03a6) lp++;
1299 *lp++ = htonl(0x7d4903a6); // mtctr r10
1300 *lp++ = htonl(0x7daff120); // mtcr r13
1301 *lp = htonl(0x48000000 + 0x8000 - (((uint32)lp - ROM_BASE) & 0xffff)); // b ROM_BASE+0x318000
1302 uint32 xlp = ((uint32)(lp+1) - ROM_BASE) & 0xffff;
1303
1304 lp = (uint32 *)(ROM_BASE + 0x312c50); // Replace rfi
1305 while (ntohl(*lp) != 0x4c000064) lp++;
1306 *lp = htonl(POWERPC_BCTR);
1307
1308 lp = (uint32 *)(ROM_BASE + 0x318000);
1309 *lp++ = htonl(0x81400000 + XLM_IRQ_NEST); // lwz r10,XLM_IRQ_NEST
1310 *lp++ = htonl(0x394affff); // subi r10,r10,1
1311 *lp++ = htonl(0x91400000 + XLM_IRQ_NEST); // stw r10,XLM_IRQ_NEST
1312 *lp = htonl(0x48000000 + ((xlp - 0x800c) & 0x03fffffc)); // b ROM_BASE+0x312c2c
1313 /*
1314 // Disable FE0A/FE06 opcodes
1315 lp = (uint32 *)(ROM_BASE + 0x3144ac);
1316 *lp++ = htonl(POWERPC_NOP);
1317 *lp += 8;
1318 */
1319 return true;
1320 }
1321
1322
1323 /*
1324 * 68k boot routine patches
1325 */
1326
1327 static bool patch_68k(void)
1328 {
1329 uint32 *lp;
1330 uint16 *wp;
1331 uint8 *bp;
1332 uint32 base;
1333
1334 // Remove 68k RESET instruction
1335 static const uint8 reset_dat[] = {0x4e, 0x70};
1336 if ((base = find_rom_data(0xc8, 0x120, reset_dat, sizeof(reset_dat))) == 0) return false;
1337 D(bug("reset %08lx\n", base));
1338 wp = (uint16 *)(ROM_BASE + base);
1339 *wp = htons(M68K_NOP);
1340
1341 // Fake reading PowerMac ID (via Universal)
1342 static const uint8 powermac_id_dat[] = {0x45, 0xf9, 0x5f, 0xff, 0xff, 0xfc, 0x20, 0x12, 0x72, 0x00};
1343 if ((base = find_rom_data(0xe000, 0x15000, powermac_id_dat, sizeof(powermac_id_dat))) == 0) return false;
1344 D(bug("powermac_id %08lx\n", base));
1345 wp = (uint16 *)(ROM_BASE + base);
1346 *wp++ = htons(0x203c); // move.l #id,d0
1347 *wp++ = htons(0);
1348 // if (ROMType == ROMTYPE_NEWWORLD)
1349 // *wp++ = htons(0x3035); // (PowerMac 9500 ID)
1350 // else
1351 *wp++ = htons(0x3020); // (PowerMac 9500 ID)
1352 *wp++ = htons(0xb040); // cmp.w d0,d0
1353 *wp = htons(0x4ed6); // jmp (a6)
1354
1355 // Patch UniversalInfo
1356 if (ROMType == ROMTYPE_NEWWORLD) {
1357 static const uint8 univ_info_dat[] = {0x3f, 0xff, 0x04, 0x00};
1358 if ((base = find_rom_data(0x14000, 0x18000, univ_info_dat, sizeof(univ_info_dat))) == 0) return false;
1359 D(bug("universal_info %08lx\n", base));
1360 lp = (uint32 *)(ROM_BASE + base - 0x14);
1361 lp[0x00 >> 2] = htonl(ADDR_MAP_PATCH_SPACE - (base - 0x14));
1362 lp[0x10 >> 2] = htonl(0xcc003d11); // Make it like the PowerMac 9500 UniversalInfo
1363 lp[0x14 >> 2] = htonl(0x3fff0401);
1364 lp[0x18 >> 2] = htonl(0x0300001c);
1365 lp[0x1c >> 2] = htonl(0x000108c4);
1366 lp[0x24 >> 2] = htonl(0xc301bf26);
1367 lp[0x28 >> 2] = htonl(0x00000861);
1368 lp[0x58 >> 2] = htonl(0x30200000);
1369 lp[0x60 >> 2] = htonl(0x0000003d);
1370 } else if (ROMType == ROMTYPE_ZANZIBAR) {
1371 base = 0x12b70;
1372 lp = (uint32 *)(ROM_BASE + base - 0x14);
1373 lp[0x00 >> 2] = htonl(ADDR_MAP_PATCH_SPACE - (base - 0x14));
1374 lp[0x10 >> 2] = htonl(0xcc003d11); // Make it like the PowerMac 9500 UniversalInfo
1375 lp[0x14 >> 2] = htonl(0x3fff0401);
1376 lp[0x18 >> 2] = htonl(0x0300001c);
1377 lp[0x1c >> 2] = htonl(0x000108c4);
1378 lp[0x24 >> 2] = htonl(0xc301bf26);
1379 lp[0x28 >> 2] = htonl(0x00000861);
1380 lp[0x58 >> 2] = htonl(0x30200000);
1381 lp[0x60 >> 2] = htonl(0x0000003d);
1382 }
1383
1384 // Construct AddrMap for NewWorld ROM
1385 if (ROMType == ROMTYPE_NEWWORLD || ROMType == ROMTYPE_ZANZIBAR) {
1386 lp = (uint32 *)(ROM_BASE + ADDR_MAP_PATCH_SPACE);
1387 memset(lp - 10, 0, 0x128);
1388 lp[-10] = htonl(0x0300001c);
1389 lp[-9] = htonl(0x000108c4);
1390 lp[-4] = htonl(0x00300000);
1391 lp[-2] = htonl(0x11010000);
1392 lp[-1] = htonl(0xf8000000);
1393 lp[0] = htonl(0xffc00000);
1394 lp[2] = htonl(0xf3016000);
1395 lp[3] = htonl(0xf3012000);
1396 lp[4] = htonl(0xf3012000);
1397 lp[24] = htonl(0xf3018000);
1398 lp[25] = htonl(0xf3010000);
1399 lp[34] = htonl(0xf3011000);
1400 lp[38] = htonl(0xf3015000);
1401 lp[39] = htonl(0xf3014000);
1402 lp[43] = htonl(0xf3000000);
1403 lp[48] = htonl(0xf8000000);
1404 }
1405
1406 // Don't initialize VIA (via Universal)
1407 static const uint8 via_init_dat[] = {0x08, 0x00, 0x00, 0x02, 0x67, 0x00, 0x00, 0x2c, 0x24, 0x68, 0x00, 0x08};
1408 if ((base = find_rom_data(0xe000, 0x15000, via_init_dat, sizeof(via_init_dat))) == 0) return false;
1409 D(bug("via_init %08lx\n", base));
1410 wp = (uint16 *)(ROM_BASE + base + 4);
1411 *wp = htons(0x6000); // bra
1412
1413 static const uint8 via_init2_dat[] = {0x24, 0x68, 0x00, 0x08, 0x00, 0x12, 0x00, 0x30, 0x4e, 0x71};
1414 if ((base = find_rom_data(0xa000, 0x10000, via_init2_dat, sizeof(via_init2_dat))) == 0) return false;
1415 D(bug("via_init2 %08lx\n", base));
1416 wp = (uint16 *)(ROM_BASE + base);
1417 *wp = htons(0x4ed6); // jmp (a6)
1418
1419 static const uint8 via_init3_dat[] = {0x22, 0x68, 0x00, 0x08, 0x28, 0x3c, 0x20, 0x00, 0x01, 0x00};
1420 if ((base = find_rom_data(0xa000, 0x10000, via_init3_dat, sizeof(via_init3_dat))) == 0) return false;
1421 D(bug("via_init3 %08lx\n", base));
1422 wp = (uint16 *)(ROM_BASE + base);
1423 *wp = htons(0x4ed6); // jmp (a6)
1424
1425 // Don't RunDiags, get BootGlobs pointer directly
1426 if (ROMType == ROMTYPE_NEWWORLD) {
1427 static const uint8 run_diags_dat[] = {0x60, 0xff, 0x00, 0x0c};
1428 if ((base = find_rom_data(0x110, 0x128, run_diags_dat, sizeof(run_diags_dat))) == 0) return false;
1429 D(bug("run_diags %08lx\n", base));
1430 wp = (uint16 *)(ROM_BASE + base);
1431 *wp++ = htons(0x4df9); // lea xxx,a6
1432 *wp++ = htons((RAMBase + RAMSize - 0x1c) >> 16);
1433 *wp = htons((RAMBase + RAMSize - 0x1c) & 0xffff);
1434 } else {
1435 static const uint8 run_diags_dat[] = {0x74, 0x00, 0x2f, 0x0e};
1436 if ((base = find_rom_data(0xd0, 0xf0, run_diags_dat, sizeof(run_diags_dat))) == 0) return false;
1437 D(bug("run_diags %08lx\n", base));
1438 wp = (uint16 *)(ROM_BASE + base - 6);
1439 *wp++ = htons(0x4df9); // lea xxx,a6
1440 *wp++ = htons((RAMBase + RAMSize - 0x1c) >> 16);
1441 *wp = htons((RAMBase + RAMSize - 0x1c) & 0xffff);
1442 }
1443
1444 // Replace NVRAM routines
1445 static const uint8 nvram1_dat[] = {0x48, 0xe7, 0x01, 0x0e, 0x24, 0x68, 0x00, 0x08, 0x08, 0x83, 0x00, 0x1f};
1446 if ((base = find_rom_data(0x7000, 0xc000, nvram1_dat, sizeof(nvram1_dat))) == 0) return false;
1447 D(bug("nvram1 %08lx\n", base));
1448 wp = (uint16 *)(ROM_BASE + base);
1449 *wp++ = htons(M68K_EMUL_OP_XPRAM1);
1450 *wp = htons(M68K_RTS);
1451
1452 if (ROMType == ROMTYPE_NEWWORLD) {
1453 static const uint8 nvram2_dat[] = {0x48, 0xe7, 0x1c, 0xe0, 0x4f, 0xef, 0xff, 0xb4};
1454 if ((base = find_rom_data(0xa000, 0xd000, nvram2_dat, sizeof(nvram2_dat))) == 0) return false;
1455 D(bug("nvram2 %08lx\n", base));
1456 wp = (uint16 *)(ROM_BASE + base);
1457 *wp++ = htons(M68K_EMUL_OP_XPRAM2);
1458 *wp = htons(0x4ed3); // jmp (a3)
1459
1460 static const uint8 nvram3_dat[] = {0x48, 0xe7, 0xdc, 0xe0, 0x4f, 0xef, 0xff, 0xb4};
1461 if ((base = find_rom_data(0xa000, 0xd000, nvram3_dat, sizeof(nvram3_dat))) == 0) return false;
1462 D(bug("nvram3 %08lx\n", base));
1463 wp = (uint16 *)(ROM_BASE + base);
1464 *wp++ = htons(M68K_EMUL_OP_XPRAM3);
1465 *wp = htons(0x4ed3); // jmp (a3)
1466
1467 static const uint8 nvram4_dat[] = {0x4e, 0x56, 0xff, 0xa8, 0x48, 0xe7, 0x1f, 0x38, 0x16, 0x2e, 0x00, 0x13};
1468 if ((base = find_rom_data(0xa000, 0xd000, nvram4_dat, sizeof(nvram4_dat))) == 0) return false;
1469 D(bug("nvram4 %08lx\n", base));
1470 wp = (uint16 *)(ROM_BASE + base + 16);
1471 *wp++ = htons(0x1a2e); // move.b ($000f,a6),d5
1472 *wp++ = htons(0x000f);
1473 *wp++ = htons(M68K_EMUL_OP_NVRAM3);
1474 *wp++ = htons(0x4cee); // movem.l ($ff88,a6),d3-d7/a2-a4
1475 *wp++ = htons(0x1cf8);
1476 *wp++ = htons(0xff88);
1477 *wp++ = htons(0x4e5e); // unlk a6
1478 *wp = htons(M68K_RTS);
1479
1480 static const uint8 nvram5_dat[] = {0x0c, 0x80, 0x03, 0x00, 0x00, 0x00, 0x66, 0x0a, 0x70, 0x00, 0x21, 0xf8, 0x02, 0x0c, 0x01, 0xe4};
1481 if ((base = find_rom_data(0xa000, 0xd000, nvram5_dat, sizeof(nvram5_dat))) == 0) return false;
1482 D(bug("nvram5 %08lx\n", base));
1483 wp = (uint16 *)(ROM_BASE + base + 6);
1484 *wp = htons(M68K_NOP);
1485
1486 static const uint8 nvram6_dat[] = {0x2f, 0x0a, 0x24, 0x48, 0x4f, 0xef, 0xff, 0xa0, 0x20, 0x0f};
1487 if ((base = find_rom_data(0x9000, 0xb000, nvram6_dat, sizeof(nvram6_dat))) == 0) return false;
1488 D(bug("nvram6 %08lx\n", base));
1489 wp = (uint16 *)(ROM_BASE + base);
1490 *wp++ = htons(0x7000); // moveq #0,d0
1491 *wp++ = htons(0x2080); // move.l d0,(a0)
1492 *wp++ = htons(0x4228); // clr.b 4(a0)
1493 *wp++ = htons(0x0004);
1494 *wp = htons(M68K_RTS);
1495
1496 static const uint8 nvram7_dat[] = {0x42, 0x2a, 0x00, 0x04, 0x4f, 0xef, 0x00, 0x60, 0x24, 0x5f, 0x4e, 0x75, 0x4f, 0xef, 0xff, 0xa0, 0x20, 0x0f};
1497 base = find_rom_data(0x9000, 0xb000, nvram7_dat, sizeof(nvram7_dat));
1498 if (base) {
1499 D(bug("nvram7 %08lx\n", base));
1500 wp = (uint16 *)(ROM_BASE + base + 12);
1501 *wp = htons(M68K_RTS);
1502 }
1503 } else {
1504 static const uint8 nvram2_dat[] = {0x4e, 0xd6, 0x06, 0x41, 0x13, 0x00};
1505 if ((base = find_rom_data(0x7000, 0xb000, nvram2_dat, sizeof(nvram2_dat))) == 0) return false;
1506 D(bug("nvram2 %08lx\n", base));
1507 wp = (uint16 *)(ROM_BASE + base + 2);
1508 *wp++ = htons(M68K_EMUL_OP_XPRAM2);
1509 *wp = htons(0x4ed3); // jmp (a3)
1510
1511 static const uint32 nvram3_loc[] = {0x582f0, 0xa0a0, 0x7e50, 0xa1d0, 0};
1512 wp = (uint16 *)(ROM_BASE + nvram3_loc[ROMType]);
1513 *wp++ = htons(0x202f); // move.l 4(sp),d0
1514 *wp++ = htons(0x0004);
1515 *wp++ = htons(M68K_EMUL_OP_NVRAM1);
1516 if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_GAZELLE)
1517 *wp = htons(M68K_RTS);
1518 else {
1519 *wp++ = htons(0x1f40); // move.b d0,8(sp)
1520 *wp++ = htons(0x0008);
1521 *wp++ = htons(0x4e74); // rtd #4
1522 *wp = htons(0x0004);
1523 }
1524
1525 static const uint32 nvram4_loc[] = {0x58460, 0xa0f0, 0x7f40, 0xa220, 0};
1526 wp = (uint16 *)(ROM_BASE + nvram4_loc[ROMType]);
1527 if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_GAZELLE) {
1528 *wp++ = htons(0x202f); // move.l 4(sp),d0
1529 *wp++ = htons(0x0004);
1530 *wp++ = htons(0x122f); // move.b 11(sp),d1
1531 *wp++ = htons(0x000b);
1532 *wp++ = htons(M68K_EMUL_OP_NVRAM2);
1533 *wp = htons(M68K_RTS);
1534 } else {
1535 *wp++ = htons(0x202f); // move.l 6(sp),d0
1536 *wp++ = htons(0x0006);
1537 *wp++ = htons(0x122f); // move.b 4(sp),d1
1538 *wp++ = htons(0x0004);
1539 *wp++ = htons(M68K_EMUL_OP_NVRAM2);
1540 *wp++ = htons(0x4e74); // rtd #6
1541 *wp = htons(0x0006);
1542 }
1543 }
1544
1545 // Fix MemTop/BootGlobs during system startup
1546 static const uint8 mem_top_dat[] = {0x2c, 0x6c, 0xff, 0xec, 0x2a, 0x4c, 0xdb, 0xec, 0xff, 0xf4};
1547 if ((base = find_rom_data(0x120, 0x180, mem_top_dat, sizeof(mem_top_dat))) == 0) return false;
1548 D(bug("mem_top %08lx\n", base));
1549 wp = (uint16 *)(ROM_BASE + base);
1550 *wp++ = htons(M68K_EMUL_OP_FIX_MEMTOP);
1551 *wp = htons(M68K_NOP);
1552
1553 // Don't initialize SCC (via 0x1ac)
1554 static const uint8 scc_init_dat[] = {0x48, 0xe7, 0x38, 0xfe};
1555 if ((base = find_rom_data(0x190, 0x1f0, scc_init_dat, sizeof(scc_init_dat))) == 0) return false;
1556 D(bug("scc_init %08lx\n", base));
1557 wp = (uint16 *)(ROM_BASE + base - 2);
1558 wp = (uint16 *)(ROM_BASE + ntohs(*wp) + base - 2);
1559 *wp++ = htons(M68K_EMUL_OP_RESET);
1560 *wp = htons(M68K_RTS);
1561
1562 // Don't EnableExtCache (via 0x1f6) and don't DisableIntSources(via 0x1fc)
1563 static const uint8 ext_cache_dat[] = {0x4e, 0x7b, 0x00, 0x02};
1564 if ((base = find_rom_data(0x1d0, 0x230, ext_cache_dat, sizeof(ext_cache_dat))) == 0) return false;
1565 D(bug("ext_cache %08lx\n", base));
1566 lp = (uint32 *)(ROM_BASE + base + 6);
1567 wp = (uint16 *)(ROM_BASE + ntohl(*lp) + base + 6);
1568 *wp = htons(M68K_RTS);
1569 lp = (uint32 *)(ROM_BASE + base + 12);
1570 wp = (uint16 *)(ROM_BASE + ntohl(*lp) + base + 12);
1571 *wp = htons(M68K_RTS);
1572
1573 // Fake CPU speed test (SetupTimeK)
1574 static const uint8 timek_dat[] = {0x0c, 0x38, 0x00, 0x04, 0x01, 0x2f, 0x6d, 0x3c};
1575 if ((base = find_rom_data(0x400, 0x500, timek_dat, sizeof(timek_dat))) == 0) return false;
1576 D(bug("timek %08lx\n", base));
1577 wp = (uint16 *)(ROM_BASE + base);
1578 *wp++ = htons(0x31fc); // move.w #xxx,TimeDBRA
1579 *wp++ = htons(100);
1580 *wp++ = htons(0x0d00);
1581 *wp++ = htons(0x31fc); // move.w #xxx,TimeSCCDBRA
1582 *wp++ = htons(100);
1583 *wp++ = htons(0x0d02);
1584 *wp++ = htons(0x31fc); // move.w #xxx,TimeSCSIDBRA
1585 *wp++ = htons(100);
1586 *wp++ = htons(0x0b24);
1587 *wp++ = htons(0x31fc); // move.w #xxx,TimeRAMDBRA
1588 *wp++ = htons(100);
1589 *wp++ = htons(0x0cea);
1590 *wp = htons(M68K_RTS);
1591
1592 // Relocate jump tables ($2000..)
1593 static const uint8 jump_tab_dat[] = {0x41, 0xfa, 0x00, 0x0e, 0x21, 0xc8, 0x20, 0x10, 0x4e, 0x75};
1594 if ((base = find_rom_data(0x3000, 0x6000, jump_tab_dat, sizeof(jump_tab_dat))) == 0) return false;
1595 D(bug("jump_tab %08lx\n", base));
1596 lp = (uint32 *)(ROM_BASE + base + 16);
1597 for (;;) {
1598 D(bug(" %08lx\n", (uint32)lp - ROM_BASE));
1599 while ((ntohl(*lp) & 0xff000000) == 0xff000000) {
1600 *lp = htonl((ntohl(*lp) & (ROM_SIZE-1)) + ROM_BASE);
1601 lp++;
1602 }
1603 while (!ntohl(*lp)) lp++;
1604 if (ntohl(*lp) != 0x41fa000e)
1605 break;
1606 lp += 4;
1607 }
1608
1609 // Create SysZone at start of Mac RAM (SetSysAppZone, via 0x22a)
1610 static const uint8 sys_zone_dat[] = {0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x40, 0x00};
1611 if ((base = find_rom_data(0x600, 0x900, sys_zone_dat, sizeof(sys_zone_dat))) == 0) return false;
1612 D(bug("sys_zone %08lx\n", base));
1613 lp = (uint32 *)(ROM_BASE + base);
1614 *lp++ = htonl(RAMBase ? RAMBase : 0x3000);
1615 *lp = htonl(RAMBase ? RAMBase + 0x1800 : 0x4800);
1616
1617 // Set boot stack at RAMBase+4MB and fix logical/physical RAM size (CompBootStack)
1618 // The RAM size fix must be done after InitMemMgr!
1619 static const uint8 boot_stack_dat[] = {0x08, 0x38, 0x00, 0x06, 0x24, 0x0b};
1620 if ((base = find_rom_data(0x580, 0x800, boot_stack_dat, sizeof(boot_stack_dat))) == 0) return false;
1621 D(bug("boot_stack %08lx\n", base));
1622 wp = (uint16 *)(ROM_BASE + base);
1623 *wp++ = htons(0x207c); // move.l #RAMBase+0x3ffffe,a0
1624 *wp++ = htons((RAMBase + 0x3ffffe) >> 16);
1625 *wp++ = htons((RAMBase + 0x3ffffe) & 0xffff);
1626 *wp++ = htons(M68K_EMUL_OP_FIX_MEMSIZE);
1627 *wp = htons(M68K_RTS);
1628
1629 // Get PowerPC page size (InitVMemMgr, via 0x240)
1630 static const uint8 page_size_dat[] = {0x20, 0x30, 0x81, 0xf2, 0x5f, 0xff, 0xef, 0xd8, 0x00, 0x10};
1631 if ((base = find_rom_data(0xb000, 0x12000, page_size_dat, sizeof(page_size_dat))) == 0) return false;
1632 D(bug("page_size %08lx\n", base));
1633 wp = (uint16 *)(ROM_BASE + base);
1634 *wp++ = htons(0x203c); // move.l #$1000,d0
1635 *wp++ = htons(0);
1636 *wp++ = htons(0x1000);
1637 *wp++ = htons(M68K_NOP);
1638 *wp = htons(M68K_NOP);
1639
1640 // Gestalt PowerPC page size, RAM size (InitGestalt, via 0x25c)
1641 static const uint8 page_size2_dat[] = {0x26, 0x79, 0x5f, 0xff, 0xef, 0xd8, 0x25, 0x6b, 0x00, 0x10, 0x00, 0x1e};
1642 if ((base = find_rom_data(0x50000, 0x70000, page_size2_dat, sizeof(page_size2_dat))) == 0) return false;
1643 D(bug("page_size2 %08lx\n", base));
1644 wp = (uint16 *)(ROM_BASE + base);
1645 *wp++ = htons(0x257c); // move.l #$1000,$1e(a2)
1646 *wp++ = htons(0);
1647 *wp++ = htons(0x1000);
1648 *wp++ = htons(0x001e);
1649 *wp++ = htons(0x157c); // move.b #PVR,$1d(a2)
1650 *wp++ = htons(PVR >> 16);
1651 *wp++ = htons(0x001d);
1652 *wp++ = htons(0x263c); // move.l #RAMSize,d3
1653 *wp++ = htons(RAMSize >> 16);
1654 *wp++ = htons(RAMSize & 0xffff);
1655 *wp++ = htons(M68K_NOP);
1656 *wp++ = htons(M68K_NOP);
1657 *wp = htons(M68K_NOP);
1658 if (ROMType == ROMTYPE_NEWWORLD)
1659 wp = (uint16 *)(ROM_BASE + base + 0x4a);
1660 else
1661 wp = (uint16 *)(ROM_BASE + base + 0x28);
1662 *wp++ = htons(M68K_NOP);
1663 *wp = htons(M68K_NOP);
1664
1665 // Gestalt CPU/bus clock speed (InitGestalt, via 0x25c)
1666 if (ROMType == ROMTYPE_ZANZIBAR) {
1667 wp = (uint16 *)(ROM_BASE + 0x5d87a);
1668 *wp++ = htons(0x203c); // move.l #Hz,d0
1669 *wp++ = htons(BusClockSpeed >> 16);
1670 *wp++ = htons(BusClockSpeed & 0xffff);
1671 *wp++ = htons(M68K_NOP);
1672 *wp = htons(M68K_NOP);
1673 wp = (uint16 *)(ROM_BASE + 0x5d888);
1674 *wp++ = htons(0x203c); // move.l #Hz,d0
1675 *wp++ = htons(CPUClockSpeed >> 16);
1676 *wp++ = htons(CPUClockSpeed & 0xffff);
1677 *wp++ = htons(M68K_NOP);
1678 *wp = htons(M68K_NOP);
1679 }
1680
1681 // Don't write to GC interrupt mask register (via 0x262)
1682 if (ROMType != ROMTYPE_NEWWORLD) {
1683 static const uint8 gc_mask_dat[] = {0x83, 0xa8, 0x00, 0x24, 0x4e, 0x71};
1684 if ((base = find_rom_data(0x13000, 0x20000, gc_mask_dat, sizeof(gc_mask_dat))) == 0) return false;
1685 D(bug("gc_mask %08lx\n", base));
1686 wp = (uint16 *)(ROM_BASE + base);
1687 *wp++ = htons(M68K_NOP);
1688 *wp = htons(M68K_NOP);
1689 wp = (uint16 *)(ROM_BASE + base + 0x40);
1690 *wp++ = htons(M68K_NOP);
1691 *wp = htons(M68K_NOP);
1692 wp = (uint16 *)(ROM_BASE + base + 0x78);
1693 *wp++ = htons(M68K_NOP);
1694 *wp = htons(M68K_NOP);
1695 wp = (uint16 *)(ROM_BASE + base + 0x96);
1696 *wp++ = htons(M68K_NOP);
1697 *wp = htons(M68K_NOP);
1698
1699 static const uint8 gc_mask2_dat[] = {0x02, 0xa8, 0x00, 0x00, 0x00, 0x80, 0x00, 0x24};
1700 if ((base = find_rom_data(0x13000, 0x20000, gc_mask2_dat, sizeof(gc_mask2_dat))) == 0) return false;
1701 D(bug("gc_mask2 %08lx\n", base));
1702 wp = (uint16 *)(ROM_BASE + base);
1703 for (int i=0; i<5; i++) {
1704 *wp++ = htons(M68K_NOP);
1705 *wp++ = htons(M68K_NOP);
1706 *wp++ = htons(M68K_NOP);
1707 *wp++ = htons(M68K_NOP);
1708 wp += 2;
1709 }
1710 if (ROMType == ROMTYPE_ZANZIBAR) {
1711 for (int i=0; i<6; i++) {
1712 *wp++ = htons(M68K_NOP);
1713 *wp++ = htons(M68K_NOP);
1714 *wp++ = htons(M68K_NOP);
1715 *wp++ = htons(M68K_NOP);
1716 wp += 2;
1717 }
1718 }
1719 }
1720
1721 // Don't initialize Cuda (via 0x274)
1722 static const uint8 cuda_init_dat[] = {0x08, 0xa9, 0x00, 0x04, 0x16, 0x00, 0x4e, 0x71, 0x13, 0x7c, 0x00, 0x84, 0x1c, 0x00, 0x4e, 0x71};
1723 if ((base = find_rom_data(0xa000, 0x12000, cuda_init_dat, sizeof(cuda_init_dat))) == 0) return false;
1724 D(bug("cuda_init %08lx\n", base));
1725 wp = (uint16 *)(ROM_BASE + base);
1726 *wp++ = htons(M68K_NOP);
1727 *wp++ = htons(M68K_NOP);
1728 *wp++ = htons(M68K_NOP);
1729 *wp++ = htons(M68K_NOP);
1730 *wp++ = htons(M68K_NOP);
1731 *wp++ = htons(M68K_NOP);
1732 *wp = htons(M68K_NOP);
1733
1734 // Patch GetCPUSpeed (via 0x27a) (some ROMs have two of them)
1735 static const uint8 cpu_speed_dat[] = {0x20, 0x30, 0x81, 0xf2, 0x5f, 0xff, 0xef, 0xd8, 0x00, 0x04, 0x4c, 0x7c};
1736 if ((base = find_rom_data(0x6000, 0xa000, cpu_speed_dat, sizeof(cpu_speed_dat))) == 0) return false;
1737 D(bug("cpu_speed %08lx\n", base));
1738 wp = (uint16 *)(ROM_BASE + base);
1739 *wp++ = htons(0x203c); // move.l #(MHz<<16)|MHz,d0
1740 *wp++ = htons(CPUClockSpeed / 1000000);
1741 *wp++ = htons(CPUClockSpeed / 1000000);
1742 *wp = htons(M68K_RTS);
1743 if ((base = find_rom_data(base, 0xa000, cpu_speed_dat, sizeof(cpu_speed_dat))) != 0) {
1744 D(bug("cpu_speed2 %08lx\n", base));
1745 wp = (uint16 *)(ROM_BASE + base);
1746 *wp++ = htons(0x203c); // move.l #(MHz<<16)|MHz,d0
1747 *wp++ = htons(CPUClockSpeed / 1000000);
1748 *wp++ = htons(CPUClockSpeed / 1000000);
1749 *wp = htons(M68K_RTS);
1750 }
1751
1752 // Don't poke VIA in InitTimeMgr (via 0x298)
1753 static const uint8 time_via_dat[] = {0x40, 0xe7, 0x00, 0x7c, 0x07, 0x00, 0x28, 0x78, 0x01, 0xd4, 0x43, 0xec, 0x10, 0x00};
1754 if ((base = find_rom_data(0x30000, 0x40000, time_via_dat, sizeof(time_via_dat))) == 0) return false;
1755 D(bug("time_via %08lx\n", base));
1756 wp = (uint16 *)(ROM_BASE + base);
1757 *wp++ = htons(0x4cdf); // movem.l (sp)+,d0-d5/a0-a4
1758 *wp++ = htons(0x1f3f);
1759 *wp = htons(M68K_RTS);
1760
1761 // Don't read from 0xff800000 (Name Registry, Open Firmware?) (via 0x2a2)
1762 // Remove this if FE03 works!!
1763 static const uint8 open_firmware_dat[] = {0x2f, 0x79, 0xff, 0x80, 0x00, 0x00, 0x00, 0xfc};
1764 if ((base = find_rom_data(0x48000, 0x58000, open_firmware_dat, sizeof(open_firmware_dat))) == 0) return false;
1765 D(bug("open_firmware %08lx\n", base));
1766 wp = (uint16 *)(ROM_BASE + base);
1767 *wp++ = htons(0x2f7c); // move.l #deadbeef,0xfc(a7)
1768 *wp++ = htons(0xdead);
1769 *wp++ = htons(0xbeef);
1770 *wp = htons(0x00fc);
1771 wp = (uint16 *)(ROM_BASE + base + 0x1a);
1772 *wp++ = htons(M68K_NOP); // (FE03 opcode, tries to jump to 0xdeadbeef)
1773 *wp = htons(M68K_NOP);
1774
1775 // Don't EnableExtCache (via 0x2b2)
1776 static const uint8 ext_cache2_dat[] = {0x4f, 0xef, 0xff, 0xec, 0x20, 0x4f, 0x10, 0xbc, 0x00, 0x01, 0x11, 0x7c, 0x00, 0x1b};
1777 if ((base = find_rom_data(0x13000, 0x20000, ext_cache2_dat, sizeof(ext_cache2_dat))) == 0) return false;
1778 D(bug("ext_cache2 %08lx\n", base));
1779 wp = (uint16 *)(ROM_BASE + base);
1780 *wp = htons(M68K_RTS);
1781
1782 // Don't install Time Manager task for 60Hz interrupt (Enable60HzInts, via 0x2b8)
1783 if (ROMType == ROMTYPE_NEWWORLD) {
1784 static const uint8 tm_task_dat[] = {0x30, 0x3c, 0x4e, 0x2b, 0xa9, 0xc9};
1785 if ((base = find_rom_data(0x2e0, 0x320, tm_task_dat, sizeof(tm_task_dat))) == 0) return false;
1786 D(bug("tm_task %08lx\n", base));
1787 wp = (uint16 *)(ROM_BASE + base + 28);
1788 *wp++ = htons(M68K_NOP);
1789 *wp++ = htons(M68K_NOP);
1790 *wp++ = htons(M68K_NOP);
1791 *wp++ = htons(M68K_NOP);
1792 *wp++ = htons(M68K_NOP);
1793 *wp = htons(M68K_NOP);
1794 } else {
1795 static const uint8 tm_task_dat[] = {0x20, 0x3c, 0x73, 0x79, 0x73, 0x61};
1796 if ((base = find_rom_data(0x280, 0x300, tm_task_dat, sizeof(tm_task_dat))) == 0) return false;
1797 D(bug("tm_task %08lx\n", base));
1798 wp = (uint16 *)(ROM_BASE + base - 6);
1799 *wp++ = htons(M68K_NOP);
1800 *wp++ = htons(M68K_NOP);
1801 *wp = htons(M68K_NOP);
1802 }
1803
1804 // Don't read PVR from 0x5fffef80 in DriverServicesLib (via 0x316)
1805 if (ROMType != ROMTYPE_NEWWORLD) {
1806 uint32 dsl_offset = find_rom_resource(FOURCC('n','l','i','b'), -16401);
1807 if (ROMType == ROMTYPE_ZANZIBAR) {
1808 static const uint8 dsl_pvr_dat[] = {0x40, 0x82, 0x00, 0x40, 0x38, 0x60, 0xef, 0x80, 0x3c, 0x63, 0x60, 0x00, 0x80, 0x83, 0x00, 0x00, 0x54, 0x84, 0x84, 0x3e};
1809 if ((base = find_rom_data(dsl_offset, dsl_offset + 0x6000, dsl_pvr_dat, sizeof(dsl_pvr_dat))) == 0) return false;
1810 } else {
1811 static const uint8 dsl_pvr_dat[] = {0x3b, 0xc3, 0x00, 0x00, 0x30, 0x84, 0xff, 0xa0, 0x40, 0x82, 0x00, 0x44, 0x80, 0x84, 0xef, 0xe0, 0x54, 0x84, 0x84, 0x3e};
1812 if ((base = find_rom_data(dsl_offset, dsl_offset + 0x6000, dsl_pvr_dat, sizeof(dsl_pvr_dat))) == 0) return false;
1813 }
1814 D(bug("dsl_pvr %08lx\n", base));
1815 lp = (uint32 *)(ROM_BASE + base + 12);
1816 *lp = htonl(0x3c800000 | (PVR >> 16)); // lis r4,PVR
1817
1818 // Don't read bus clock from 0x5fffef88 in DriverServicesLib (via 0x316)
1819 if (ROMType == ROMTYPE_ZANZIBAR) {
1820 static const uint8 dsl_bus_dat[] = {0x81, 0x07, 0x00, 0x00, 0x39, 0x20, 0x42, 0x40, 0x81, 0x62, 0xff, 0x20};
1821 if ((base = find_rom_data(dsl_offset, dsl_offset + 0x6000, dsl_bus_dat, sizeof(dsl_bus_dat))) == 0) return false;
1822 D(bug("dsl_bus %08lx\n", base));
1823 lp = (uint32 *)(ROM_BASE + base);
1824 *lp = htonl(0x81000000 + XLM_BUS_CLOCK); // lwz r8,(bus clock speed)
1825 } else {
1826 static const uint8 dsl_bus_dat[] = {0x80, 0x83, 0xef, 0xe8, 0x80, 0x62, 0x00, 0x10, 0x7c, 0x04, 0x03, 0x96};
1827 if ((base = find_rom_data(dsl_offset, dsl_offset + 0x6000, dsl_bus_dat, sizeof(dsl_bus_dat))) == 0) return false;
1828 D(bug("dsl_bus %08lx\n", base));
1829 lp = (uint32 *)(ROM_BASE + base);
1830 *lp = htonl(0x80800000 + XLM_BUS_CLOCK); // lwz r4,(bus clock speed)
1831 }
1832 }
1833
1834 // Don't open InterruptTreeTNT in MotherBoardHAL init in DriverServicesLib init
1835 if (ROMType == ROMTYPE_ZANZIBAR) {
1836 lp = (uint32 *)(ROM_BASE + find_rom_resource(FOURCC('n','l','i','b'), -16408) + 0x16c);
1837 *lp = htonl(0x38600000); // li r3,0
1838 }
1839
1840 // Patch Name Registry
1841 static const uint8 name_reg_dat[] = {0x70, 0xff, 0xab, 0xeb};
1842 if ((base = find_rom_data(0x300, 0x380, name_reg_dat, sizeof(name_reg_dat))) == 0) return false;
1843 D(bug("name_reg %08lx\n", base));
1844 wp = (uint16 *)(ROM_BASE + base);
1845 *wp = htons(M68K_EMUL_OP_NAME_REGISTRY);
1846
1847 #if DISABLE_SCSI
1848 // Fake SCSI Manager
1849 // Remove this if SCSI Manager works!!
1850 static const uint8 scsi_mgr_a_dat[] = {0x4e, 0x56, 0x00, 0x00, 0x20, 0x3c, 0x00, 0x00, 0x04, 0x0c, 0xa7, 0x1e};
1851 static const uint8 scsi_mgr_b_dat[] = {0x4e, 0x56, 0x00, 0x00, 0x2f, 0x0c, 0x20, 0x3c, 0x00, 0x00, 0x04, 0x0c, 0xa7, 0x1e};
1852 if ((base = find_rom_data(0x1c000, 0x28000, scsi_mgr_a_dat, sizeof(scsi_mgr_a_dat))) == 0) {
1853 if ((base = find_rom_data(0x1c000, 0x28000, scsi_mgr_b_dat, sizeof(scsi_mgr_b_dat))) == 0) return false;
1854 }
1855 D(bug("scsi_mgr %08lx\n", base));
1856 wp = (uint16 *)(ROM_BASE + base);
1857 *wp++ = htons(0x21fc); // move.l #xxx,0x624 (SCSIAtomic)
1858 *wp++ = htons((ROM_BASE + base + 18) >> 16);
1859 *wp++ = htons((ROM_BASE + base + 18) & 0xffff);
1860 *wp++ = htons(0x0624);
1861 *wp++ = htons(0x21fc); // move.l #xxx,0xe54 (SCSIDispatch)
1862 *wp++ = htons((ROM_BASE + base + 22) >> 16);
1863 *wp++ = htons((ROM_BASE + base + 22) & 0xffff);
1864 *wp++ = htons(0x0e54);
1865 *wp++ = htons(M68K_RTS);
1866 *wp++ = htons(M68K_EMUL_OP_SCSI_ATOMIC);
1867 *wp++ = htons(M68K_RTS);
1868 *wp++ = htons(M68K_EMUL_OP_SCSI_DISPATCH);
1869 *wp = htons(0x4ed0); // jmp (a0)
1870 wp = (uint16 *)(ROM_BASE + base + 0x20);
1871 *wp++ = htons(0x7000); // moveq #0,d0
1872 *wp = htons(M68K_RTS);
1873 #endif
1874
1875 #if DISABLE_SCSI
1876 // Don't access SCSI variables
1877 // Remove this if SCSI Manager works!!
1878 if (ROMType == ROMTYPE_NEWWORLD) {
1879 static const uint8 scsi_var_dat[] = {0x70, 0x01, 0xa0, 0x89, 0x4a, 0x6e, 0xfe, 0xac, 0x4f, 0xef, 0x00, 0x10, 0x66, 0x00};
1880 if ((base = find_rom_data(0x1f500, 0x1f600, scsi_var_dat, sizeof(scsi_var_dat))) != 0) {
1881 D(bug("scsi_var %08lx\n", base));
1882 wp = (uint16 *)(ROM_BASE + base + 12);
1883 *wp = htons(0x6000); // bra
1884 }
1885
1886 static const uint8 scsi_var2_dat[] = {0x4e, 0x56, 0xfc, 0x58, 0x48, 0xe7, 0x1f, 0x38};
1887 if ((base = find_rom_data(0x1f700, 0x1f800, scsi_var2_dat, sizeof(scsi_var2_dat))) != 0) {
1888 D(bug("scsi_var2 %08lx\n", base));
1889 wp = (uint16 *)(ROM_BASE + base);
1890 *wp++ = htons(0x7000); // moveq #0,d0
1891 *wp = htons(M68K_RTS); // bra
1892 }
1893 }
1894 #endif
1895
1896 // Don't wait in ADBInit (via 0x36c)
1897 static const uint8 adb_init_dat[] = {0x08, 0x2b, 0x00, 0x05, 0x01, 0x5d, 0x66, 0xf8};
1898 if ((base = find_rom_data(0x31000, 0x3d000, adb_init_dat, sizeof(adb_init_dat))) == 0) return false;
1899 D(bug("adb_init %08lx\n", base));
1900 wp = (uint16 *)(ROM_BASE + base + 6);
1901 *wp = htons(M68K_NOP);
1902
1903 // Modify check in InitResources() so that addresses >0x80000000 work
1904 static const uint8 init_res_dat[] = {0x4a, 0xb8, 0x0a, 0x50, 0x6e, 0x20};
1905 if ((base = find_rom_data(0x78000, 0x8c000, init_res_dat, sizeof(init_res_dat))) == 0) return false;
1906 D(bug("init_res %08lx\n", base));
1907 bp = (uint8 *)(ROM_BASE + base + 4);
1908 *bp = 0x66;
1909
1910 // Modify vCheckLoad() so that we can patch resources (68k Resource Manager)
1911 static const uint8 check_load_dat[] = {0x20, 0x78, 0x07, 0xf0, 0x4e, 0xd0};
1912 if ((base = find_rom_data(0x78000, 0x8c000, check_load_dat, sizeof(check_load_dat))) == 0) return false;
1913 D(bug("check_load %08lx\n", base));
1914 wp = (uint16 *)(ROM_BASE + base);
1915 *wp++ = htons(M68K_JMP);
1916 *wp++ = htons((ROM_BASE + CHECK_LOAD_PATCH_SPACE) >> 16);
1917 *wp = htons((ROM_BASE + CHECK_LOAD_PATCH_SPACE) & 0xffff);
1918 wp = (uint16 *)(ROM_BASE + CHECK_LOAD_PATCH_SPACE);
1919 *wp++ = htons(0x2f03); // move.l d3,-(a7)
1920 *wp++ = htons(0x2078); // move.l $07f0,a0
1921 *wp++ = htons(0x07f0);
1922 *wp++ = htons(M68K_JSR_A0);
1923 *wp++ = htons(M68K_EMUL_OP_CHECKLOAD);
1924 *wp = htons(M68K_RTS);
1925
1926 // Replace .Sony driver
1927 sony_offset = find_rom_resource(FOURCC('D','R','V','R'), 4);
1928 if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_NEWWORLD)
1929 sony_offset = find_rom_resource(FOURCC('D','R','V','R'), 4, true); // First DRVR 4 is .MFMFloppy
1930 if (sony_offset == 0) {
1931 sony_offset = find_rom_resource(FOURCC('n','d','r','v'), -20196); // NewWorld 1.6 has "PCFloppy" ndrv
1932 if (sony_offset == 0)
1933 return false;
1934 lp = (uint32 *)(ROM_BASE + rsrc_ptr + 8);
1935 *lp = htonl(FOURCC('D','R','V','R'));
1936 wp = (uint16 *)(ROM_BASE + rsrc_ptr + 12);
1937 *wp = htons(4);
1938 }
1939 D(bug("sony_offset %08lx\n", sony_offset));
1940 memcpy((void *)(ROM_BASE + sony_offset), sony_driver, sizeof(sony_driver));
1941
1942 // Install .Disk and .AppleCD drivers
1943 memcpy((void *)(ROM_BASE + sony_offset + 0x100), disk_driver, sizeof(disk_driver));
1944 memcpy((void *)(ROM_BASE + sony_offset + 0x200), cdrom_driver, sizeof(cdrom_driver));
1945
1946 // Install serial drivers
1947 memcpy((void *)(ROM_BASE + sony_offset + 0x300), ain_driver, sizeof(ain_driver));
1948 memcpy((void *)(ROM_BASE + sony_offset + 0x400), aout_driver, sizeof(aout_driver));
1949 memcpy((void *)(ROM_BASE + sony_offset + 0x500), bin_driver, sizeof(bin_driver));
1950 memcpy((void *)(ROM_BASE + sony_offset + 0x600), bout_driver, sizeof(bout_driver));
1951
1952 // Copy icons to ROM
1953 SonyDiskIconAddr = ROM_BASE + sony_offset + 0x800;
1954 memcpy((void *)(ROM_BASE + sony_offset + 0x800), SonyDiskIcon, sizeof(SonyDiskIcon));
1955 SonyDriveIconAddr = ROM_BASE + sony_offset + 0xa00;
1956 memcpy((void *)(ROM_BASE + sony_offset + 0xa00), SonyDriveIcon, sizeof(SonyDriveIcon));
1957 DiskIconAddr = ROM_BASE + sony_offset + 0xc00;
1958 memcpy((void *)(ROM_BASE + sony_offset + 0xc00), DiskIcon, sizeof(DiskIcon));
1959 CDROMIconAddr = ROM_BASE + sony_offset + 0xe00;
1960 memcpy((void *)(ROM_BASE + sony_offset + 0xe00), CDROMIcon, sizeof(CDROMIcon));
1961
1962 // Patch driver install routine
1963 static const uint8 drvr_install_dat[] = {0xa7, 0x1e, 0x21, 0xc8, 0x01, 0x1c, 0x4e, 0x75};
1964 if ((base = find_rom_data(0xb00, 0xd00, drvr_install_dat, sizeof(drvr_install_dat))) == 0) return false;
1965 D(bug("drvr_install %08lx\n", base));
1966 wp = (uint16 *)(ROM_BASE + base + 8);
1967 *wp++ = htons(M68K_EMUL_OP_INSTALL_DRIVERS);
1968 *wp = htons(M68K_RTS);
1969
1970 // Don't install serial drivers from ROM
1971 if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_NEWWORLD) {
1972 wp = (uint16 *)(ROM_BASE + find_rom_resource(FOURCC('S','E','R','D'), 0));
1973 *wp = htons(M68K_RTS);
1974 } else {
1975 wp = (uint16 *)(ROM_BASE + find_rom_resource(FOURCC('s','l','0','5'), 2) + 0xc4);
1976 *wp++ = htons(M68K_NOP);
1977 *wp++ = htons(M68K_NOP);
1978 *wp++ = htons(M68K_NOP);
1979 *wp++ = htons(M68K_NOP);
1980 *wp = htons(0x7000); // moveq #0,d0
1981 wp = (uint16 *)(ROM_BASE + find_rom_resource(FOURCC('s','l','0','5'), 2) + 0x8ee);
1982 *wp = htons(M68K_NOP);
1983 }
1984 uint32 nsrd_offset = find_rom_resource(FOURCC('n','s','r','d'), 1);
1985 if (nsrd_offset) {
1986 lp = (uint32 *)(ROM_BASE + rsrc_ptr + 8);
1987 *lp = htonl(FOURCC('x','s','r','d'));
1988 }
1989
1990 // Replace ADBOp()
1991 memcpy((void *)(ROM_BASE + find_rom_trap(0xa07c)), adbop_patch, sizeof(adbop_patch));
1992
1993 // Replace Time Manager
1994 wp = (uint16 *)(ROM_BASE + find_rom_trap(0xa058));
1995 *wp++ = htons(M68K_EMUL_OP_INSTIME);
1996 *wp = htons(M68K_RTS);
1997 wp = (uint16 *)(ROM_BASE + find_rom_trap(0xa059));
1998 *wp++ = htons(0x40e7); // move sr,-(sp)
1999 *wp++ = htons(0x007c); // ori #$0700,sr
2000 *wp++ = htons(0x0700);
2001 *wp++ = htons(M68K_EMUL_OP_RMVTIME);
2002 *wp++ = htons(0x46df); // move (sp)+,sr
2003 *wp = htons(M68K_RTS);
2004 wp = (uint16 *)(ROM_BASE + find_rom_trap(0xa05a));
2005 *wp++ = htons(0x40e7); // move sr,-(sp)
2006 *wp++ = htons(0x007c); // ori #$0700,sr
2007 *wp++ = htons(0x0700);
2008 *wp++ = htons(M68K_EMUL_OP_PRIMETIME);
2009 *wp++ = htons(0x46df); // move (sp)+,sr
2010 *wp = htons(M68K_RTS);
2011 wp = (uint16 *)(ROM_BASE + find_rom_trap(0xa093));
2012 *wp++ = htons(M68K_EMUL_OP_MICROSECONDS);
2013 *wp = htons(M68K_RTS);
2014
2015 // Disable Egret Manager
2016 static const uint8 egret_dat[] = {0x2f, 0x30, 0x81, 0xe2, 0x20, 0x10, 0x00, 0x18};
2017 if ((base = find_rom_data(0xa000, 0x10000, egret_dat, sizeof(egret_dat))) == 0) return false;
2018 D(bug("egret %08lx\n", base));
2019 wp = (uint16 *)(ROM_BASE + base);
2020 *wp++ = htons(0x7000);
2021 *wp = htons(M68K_RTS);
2022
2023 // Don't call FE0A opcode in Shutdown Manager
2024 static const uint8 shutdown_dat[] = {0x40, 0xe7, 0x00, 0x7c, 0x07, 0x00, 0x48, 0xe7, 0x3f, 0x00, 0x2c, 0x00, 0x2e, 0x01};
2025 if ((base = find_rom_data(0x30000, 0x40000, shutdown_dat, sizeof(shutdown_dat))) == 0) return false;
2026 D(bug("shutdown %08lx\n", base));
2027 wp = (uint16 *)(ROM_BASE + base);
2028 if (ROMType == ROMTYPE_ZANZIBAR)
2029 *wp = htons(M68K_RTS);
2030 else if (ntohs(wp[-4]) == 0x61ff)
2031 *wp = htons(M68K_RTS);
2032 else if (ntohs(wp[-2]) == 0x6700)
2033 wp[-2] = htons(0x6000); // bra
2034
2035 // Patch PowerOff()
2036 wp = (uint16 *)(ROM_BASE + find_rom_trap(0xa05b)); // PowerOff()
2037 *wp = htons(M68K_EMUL_RETURN);
2038
2039 // Patch VIA interrupt handler
2040 static const uint8 via_int_dat[] = {0x70, 0x7f, 0xc0, 0x29, 0x1a, 0x00, 0xc0, 0x29, 0x1c, 0x00};
2041 if ((base = find_rom_data(0x13000, 0x1c000, via_int_dat, sizeof(via_int_dat))) == 0) return false;
2042 D(bug("via_int %08lx\n", base));
2043 uint32 level1_int = ROM_BASE + base;
2044 wp = (uint16 *)level1_int; // Level 1 handler
2045 *wp++ = htons(0x7002); // moveq #2,d0 (60Hz interrupt)
2046 *wp++ = htons(M68K_NOP);
2047 *wp++ = htons(M68K_NOP);
2048 *wp++ = htons(M68K_NOP);
2049 *wp = htons(M68K_NOP);
2050
2051 static const uint8 via_int2_dat[] = {0x13, 0x7c, 0x00, 0x02, 0x1a, 0x00, 0x4e, 0x71, 0x52, 0xb8, 0x01, 0x6a};
2052 if ((base = find_rom_data(0x10000, 0x18000, via_int2_dat, sizeof(via_int2_dat))) == 0) return false;
2053 D(bug("via_int2 %08lx\n", base));
2054 wp = (uint16 *)(ROM_BASE + base); // 60Hz handler
2055 *wp++ = htons(M68K_EMUL_OP_IRQ);
2056 *wp++ = htons(0x4a80); // tst.l d0
2057 *wp++ = htons(0x6700); // beq xxx
2058 *wp = htons(0xffe8);
2059
2060 if (ROMType == ROMTYPE_NEWWORLD) {
2061 static const uint8 via_int3_dat[] = {0x48, 0xe7, 0xf0, 0xf0, 0x76, 0x01, 0x60, 0x26};
2062 if ((base = find_rom_data(0x15000, 0x19000, via_int3_dat, sizeof(via_int3_dat))) == 0) return false;
2063 D(bug("via_int3 %08lx\n", base));
2064 wp = (uint16 *)(ROM_BASE + base); // CHRP level 1 handler
2065 *wp++ = htons(M68K_JMP);
2066 *wp++ = htons((level1_int - 12) >> 16);
2067 *wp = htons((level1_int - 12) & 0xffff);
2068 }
2069
2070 // Patch PutScrap() for clipboard exchange with host OS
2071 uint32 put_scrap = find_rom_trap(0xa9fe); // PutScrap()
2072 wp = (uint16 *)(ROM_BASE + PUT_SCRAP_PATCH_SPACE);
2073 *wp++ = htons(M68K_EMUL_OP_PUT_SCRAP);
2074 *wp++ = htons(M68K_JMP);
2075 *wp++ = htons((ROM_BASE + put_scrap) >> 16);
2076 *wp++ = htons((ROM_BASE + put_scrap) & 0xffff);
2077 lp = (uint32 *)(ROM_BASE + 0x22);
2078 lp = (uint32 *)(ROM_BASE + ntohl(*lp));
2079 lp[0xa9fe & 0x3ff] = htonl(PUT_SCRAP_PATCH_SPACE);
2080
2081 // Patch GetScrap() for clipboard exchange with host OS
2082 uint32 get_scrap = find_rom_trap(0xa9fd); // GetScrap()
2083 wp = (uint16 *)(ROM_BASE + GET_SCRAP_PATCH_SPACE);
2084 *wp++ = htons(M68K_EMUL_OP_GET_SCRAP);
2085 *wp++ = htons(M68K_JMP);
2086 *wp++ = htons((ROM_BASE + get_scrap) >> 16);
2087 *wp++ = htons((ROM_BASE + get_scrap) & 0xffff);
2088 lp = (uint32 *)(ROM_BASE + 0x22);
2089 lp = (uint32 *)(ROM_BASE + ntohl(*lp));
2090 lp[0xa9fd & 0x3ff] = htonl(GET_SCRAP_PATCH_SPACE);
2091
2092 #if __BEOS__
2093 // Patch SynchIdleTime()
2094 if (PrefsFindBool("idlewait")) {
2095 wp = (uint16 *)(ROM_BASE + find_rom_trap(0xabf7) + 4); // SynchIdleTime()
2096 D(bug("SynchIdleTime at %08lx\n", wp));
2097 if (ntohs(*wp) == 0x2078) {
2098 *wp++ = htons(M68K_EMUL_OP_IDLE_TIME);
2099 *wp = htons(M68K_NOP);
2100 } else {
2101 D(bug("SynchIdleTime patch not installed\n"));
2102 }
2103 }
2104 #endif
2105
2106 // Construct list of all sifters used by sound components in ROM
2107 D(bug("Searching for sound components with type sdev in ROM\n"));
2108 uint32 thing = find_rom_resource(FOURCC('t','h','n','g'));
2109 while (thing) {
2110 thing += ROM_BASE;
2111 D(bug(" found %c%c%c%c %c%c%c%c\n", ReadMacInt8(thing), ReadMacInt8(thing + 1), ReadMacInt8(thing + 2), ReadMacInt8(thing + 3), ReadMacInt8(thing + 4), ReadMacInt8(thing + 5), ReadMacInt8(thing + 6), ReadMacInt8(thing + 7)));
2112 if (ReadMacInt32(thing) == FOURCC('s','d','e','v') && ReadMacInt32(thing + 4) == FOURCC('s','i','n','g')) {
2113 WriteMacInt32(thing + 4, FOURCC('a','w','g','c'));
2114 D(bug(" found sdev component at offset %08x in ROM\n", thing));
2115 AddSifter(ReadMacInt32(thing + componentResType), ReadMacInt16(thing + componentResID));
2116 if (ReadMacInt32(thing + componentPFCount))
2117 AddSifter(ReadMacInt32(thing + componentPFResType), ReadMacInt16(thing + componentPFResID));
2118 }
2119 thing = find_rom_resource(FOURCC('t','h','n','g'), 4711, true);
2120 }
2121
2122 // Patch component code
2123 D(bug("Patching sifters in ROM\n"));
2124 for (int i=0; i<num_sifters; i++) {
2125 if ((thing = find_rom_resource(sifter_list[i].type, sifter_list[i].id)) != 0) {
2126 D(bug(" patching type %08x, id %d\n", sifter_list[i].type, sifter_list[i].id));
2127 // Install 68k glue code
2128 uint16 *wp = (uint16 *)(ROM_BASE + thing);
2129 *wp++ = htons(0x4e56); *wp++ = htons(0x0000); // link a6,#0
2130 *wp++ = htons(0x48e7); *wp++ = htons(0x8018); // movem.l d0/a3-a4,-(a7)
2131 *wp++ = htons(0x266e); *wp++ = htons(0x000c); // movea.l $c(a6),a3
2132 *wp++ = htons(0x286e); *wp++ = htons(0x0008); // movea.l $8(a6),a4
2133 *wp++ = htons(M68K_EMUL_OP_AUDIO_DISPATCH);
2134 *wp++ = htons(0x2d40); *wp++ = htons(0x0010); // move.l d0,$10(a6)
2135 *wp++ = htons(0x4cdf); *wp++ = htons(0x1801); // movem.l (a7)+,d0/a3-a4
2136 *wp++ = htons(0x4e5e); // unlk a6
2137 *wp++ = htons(0x4e74); *wp++ = htons(0x0008); // rtd #8
2138 }
2139 }
2140 return true;
2141 }
2142
2143
2144 /*
2145 * Install .Sony, disk and CD-ROM drivers
2146 */
2147
2148 void InstallDrivers(void)
2149 {
2150 D(bug("Installing drivers...\n"));
2151 M68kRegisters r;
2152 uint8 pb[SIZEOF_IOParam];
2153
2154 #if DISABLE_SCSI && 0
2155 // Fake SCSIGlobals
2156 static const uint8 fake_scsi_globals[32] = {0,};
2157 WriteMacInt32(0xc0c, (uint32)fake_scsi_globals);
2158 #endif
2159
2160 // Install floppy driver
2161 if (ROMType == ROMTYPE_NEWWORLD) {
2162
2163 // Force installation of floppy driver with NewWorld ROMs
2164 r.a[0] = ROM_BASE + sony_offset;
2165 r.d[0] = (uint32)SonyRefNum;
2166 Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem()
2167 r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~SonyRefNum * 4); // Get driver handle from Unit Table
2168 Execute68kTrap(0xa029, &r); // HLock()
2169 uint32 dce = ReadMacInt32(r.a[0]);
2170 WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset);
2171 WriteMacInt16(dce + dCtlFlags, SonyDriverFlags);
2172 }
2173
2174 // Open .Sony driver
2175 WriteMacInt8((uint32)pb + ioPermssn, 0);
2176 WriteMacInt32((uint32)pb + ioNamePtr, (uint32)"\005.Sony");
2177 r.a[0] = (uint32)pb;
2178 Execute68kTrap(0xa000, &r); // Open()
2179
2180 // Install disk driver
2181 r.a[0] = ROM_BASE + sony_offset + 0x100;
2182 r.d[0] = (uint32)DiskRefNum;
2183 Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem()
2184 r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~DiskRefNum * 4); // Get driver handle from Unit Table
2185 Execute68kTrap(0xa029, &r); // HLock()
2186 uint32 dce = ReadMacInt32(r.a[0]);
2187 WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x100);
2188 WriteMacInt16(dce + dCtlFlags, DiskDriverFlags);
2189
2190 // Open disk driver
2191 WriteMacInt32((uint32)pb + ioNamePtr, (uint32)"\005.Disk");
2192 r.a[0] = (uint32)pb;
2193 Execute68kTrap(0xa000, &r); // Open()
2194
2195 // Install CD-ROM driver unless nocdrom option given
2196 if (!PrefsFindBool("nocdrom")) {
2197
2198 // Install CD-ROM driver
2199 r.a[0] = ROM_BASE + sony_offset + 0x200;
2200 r.d[0] = (uint32)CDROMRefNum;
2201 Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem()
2202 r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~CDROMRefNum * 4); // Get driver handle from Unit Table
2203 Execute68kTrap(0xa029, &r); // HLock()
2204 dce = ReadMacInt32(r.a[0]);
2205 WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x200);
2206 WriteMacInt16(dce + dCtlFlags, CDROMDriverFlags);
2207
2208 // Open CD-ROM driver
2209 WriteMacInt32((uint32)pb + ioNamePtr, (uint32)"\010.AppleCD");
2210 r.a[0] = (uint32)pb;
2211 Execute68kTrap(0xa000, &r); // Open()
2212 }
2213
2214 // Install serial drivers
2215 r.a[0] = ROM_BASE + sony_offset + 0x300;
2216 r.d[0] = (uint32)-6;
2217 Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem()
2218 r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~(-6) * 4); // Get driver handle from Unit Table
2219 Execute68kTrap(0xa029, &r); // HLock()
2220 dce = ReadMacInt32(r.a[0]);
2221 WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x300);
2222 WriteMacInt16(dce + dCtlFlags, 0x4d00);
2223
2224 r.a[0] = ROM_BASE + sony_offset + 0x400;
2225 r.d[0] = (uint32)-7;
2226 Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem()
2227 r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~(-7) * 4); // Get driver handle from Unit Table
2228 Execute68kTrap(0xa029, &r); // HLock()
2229 dce = ReadMacInt32(r.a[0]);
2230 WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x400);
2231 WriteMacInt16(dce + dCtlFlags, 0x4e00);
2232
2233 r.a[0] = ROM_BASE + sony_offset + 0x500;
2234 r.d[0] = (uint32)-8;
2235 Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem()
2236 r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~(-8) * 4); // Get driver handle from Unit Table
2237 Execute68kTrap(0xa029, &r); // HLock()
2238 dce = ReadMacInt32(r.a[0]);
2239 WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x500);
2240 WriteMacInt16(dce + dCtlFlags, 0x4d00);
2241
2242 r.a[0] = ROM_BASE + sony_offset + 0x600;
2243 r.d[0] = (uint32)-9;
2244 Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem()
2245 r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~(-9) * 4); // Get driver handle from Unit Table
2246 Execute68kTrap(0xa029, &r); // HLock()
2247 dce = ReadMacInt32(r.a[0]);
2248 WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x600);
2249 WriteMacInt16(dce + dCtlFlags, 0x4e00);
2250 }