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root/cebix/BasiliskII/src/uae_cpu/gencpu.c

Comparing BasiliskII/src/uae_cpu/gencpu.c (file contents):
Revision 1.12 by gbeauche, 2001-03-19T13:11:40Z vs.
Revision 1.25 by gbeauche, 2007-06-30T08:00:31Z

#	Line 30 | Line 30
30
31		#define BOOL_TYPE "int"
32
33	+	/* Define the minimal 680x0 where NV flags are not affected by xBCD instructions.  */
34	+	#define xBCD_KEEPS_NV_FLAGS 4
35	+
36		static FILE *headerfile;
37		static FILE *stblfile;
38
#	Line 568 | Line 571 | static void duplicate_carry (void)
571		}
572
573		typedef enum {
574	<	flag_logical_noclobber, flag_logical, flag_add, flag_sub, flag_cmp, flag_addx, flag_subx, flag_zn,
574	>	flag_logical_noclobber, flag_logical, flag_add, flag_sub, flag_cmp, flag_addx, flag_subx, flag_z, flag_zn,
575		flag_av, flag_sv
576		} flagtypes;
577
#	Line 622 | Line 625 | static void genflags_normal (flagtypes t
625		switch (type) {
626		case flag_logical_noclobber:
627		case flag_logical:
628	+	case flag_z:
629		case flag_zn:
630		case flag_av:
631		case flag_sv:
#	Line 643 | Line 647 | static void genflags_normal (flagtypes t
647		switch (type) {
648		case flag_logical_noclobber:
649		case flag_logical:
650	+	case flag_z:
651		case flag_zn:
652		break;
653
#	Line 676 | Line 681 | static void genflags_normal (flagtypes t
681		case flag_sv:
682		printf ("\tSET_VFLG ((flgs ^ flgo) & (flgn ^ flgo));\n");
683		break;
684	+	case flag_z:
685	+	printf ("\tSET_ZFLG (GET_ZFLG & (%s == 0));\n", vstr);
686	+	break;
687		case flag_zn:
688		printf ("\tSET_ZFLG (GET_ZFLG & (%s == 0));\n", vstr);
689		printf ("\tSET_NFLG (%s < 0);\n", vstr);
#	Line 715 | Line 723 | static void genflags_normal (flagtypes t
723
724		static void genflags (flagtypes type, wordsizes size, char *value, char *src, char *dst)
725		{
726	<	#ifdef SPARC_V8_ASSEMBLY
727	<	switch(type)
728	<	{
729	<	case flag_add:
722	<	start_brace();
723	<	printf("\tuae_u32 %s;\n", value);
724	<	switch(size)
725	<	{
726	<	case sz_byte:
727	<	printf("\t%s = sparc_v8_flag_add_8(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
728	<	break;
729	<	case sz_word:
730	<	printf("\t%s = sparc_v8_flag_add_16(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
731	<	break;
732	<	case sz_long:
733	<	printf("\t%s = sparc_v8_flag_add_32(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
734	<	break;
735	<	}
736	<	return;
737	<
738	<	case flag_sub:
739	<	start_brace();
740	<	printf("\tuae_u32 %s;\n", value);
741	<	switch(size)
742	<	{
743	<	case sz_byte:
744	<	printf("\t%s = sparc_v8_flag_sub_8(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
745	<	break;
746	<	case sz_word:
747	<	printf("\t%s = sparc_v8_flag_sub_16(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
748	<	break;
749	<	case sz_long:
750	<	printf("\t%s = sparc_v8_flag_sub_32(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
751	<	break;
752	<	}
753	<	return;
754	<
755	<	case flag_cmp:
756	<	switch(size)
757	<	{
758	<	case sz_byte:
759	<	//                                      printf("\tsparc_v8_flag_cmp_8(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", src, dst);
760	<	break;
761	<	case sz_word:
762	<	//                                      printf("\tsparc_v8_flag_cmp_16(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", src, dst);
763	<	break;
764	<	case sz_long:
765	<	#if 1
766	<	printf("\tsparc_v8_flag_cmp_32(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", src, dst);
767	<	return;
768	<	#endif
769	<	break;
770	<	}
771	<	//                      return;
772	<	break;
773	<	}
774	<	#elif defined(SPARC_V9_ASSEMBLY)
775	<	switch(type)
776	<	{
777	<	case flag_add:
778	<	start_brace();
779	<	printf("\tuae_u32 %s;\n", value);
780	<	switch(size)
781	<	{
782	<	case sz_byte:
783	<	printf("\t%s = sparc_v9_flag_add_8(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
784	<	break;
785	<	case sz_word:
786	<	printf("\t%s = sparc_v9_flag_add_16(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
787	<	break;
788	<	case sz_long:
789	<	printf("\t%s = sparc_v9_flag_add_32(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
790	<	break;
791	<	}
792	<	return;
793	<
794	<	case flag_sub:
795	<	start_brace();
796	<	printf("\tuae_u32 %s;\n", value);
797	<	switch(size)
798	<	{
799	<	case sz_byte:
800	<	printf("\t%s = sparc_v9_flag_sub_8(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
801	<	break;
802	<	case sz_word:
803	<	printf("\t%s = sparc_v9_flag_sub_16(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
804	<	break;
805	<	case sz_long:
806	<	printf("\t%s = sparc_v9_flag_sub_32(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", value, src, dst);
807	<	break;
808	<	}
809	<	return;
810	<
811	<	case flag_cmp:
812	<	switch(size)
813	<	{
814	<	case sz_byte:
815	<	printf("\tsparc_v9_flag_cmp_8(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", src, dst);
816	<	break;
817	<	case sz_word:
818	<	printf("\tsparc_v9_flag_cmp_16(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", src, dst);
819	<	break;
820	<	case sz_long:
821	<	printf("\tsparc_v9_flag_cmp_32(&regflags, (uae_u32)(%s), (uae_u32)(%s));\n", src, dst);
822	<	break;
823	<	}
824	<	return;
825	<
826	<	case flag_logical:
827	<	if (strcmp(value, "0") == 0) {
828	<	printf("\tregflags.nzvc = 0x04;\n");
829	<	} else {
830	<	switch(size) {
831	<	case sz_byte:
832	<	printf("\tsparc_v9_flag_test_8(&regflags, (uae_u32)(%s));\n", value);
833	<	break;
834	<	case sz_word:
835	<	printf("\tsparc_v9_flag_test_16(&regflags, (uae_u32)(%s));\n", value);
836	<	break;
837	<	case sz_long:
838	<	printf("\tsparc_v9_flag_test_32(&regflags, (uae_u32)(%s));\n", value);
839	<	break;
840	<	}
841	<	}
842	<	return;
843	<
844	<	#if 0
845	<	case flag_logical_noclobber:
846	<	printf("\t{uae_u32 old_flags = regflags.nzvc & ~0x0C;\n");
847	<	if (strcmp(value, "0") == 0) {
848	<	printf("\tregflags.nzvc = old_flags | 0x04;\n");
849	<	} else {
850	<	switch(size) {
851	<	case sz_byte:
852	<	printf("\tsparc_v9_flag_test_8(&regflags, (uae_u32)(%s));\n", value);
853	<	break;
854	<	case sz_word:
855	<	printf("\tsparc_v9_flag_test_16(&regflags, (uae_u32)(%s));\n", value);
856	<	break;
857	<	case sz_long:
858	<	printf("\tsparc_v9_flag_test_32(&regflags, (uae_u32)(%s));\n", value);
859	<	break;
860	<	}
861	<	printf("\tregflags.nzvc |= old_flags;\n");
862	<	}
863	<	printf("\t}\n");
864	<	return;
865	<	#endif
866	<	}
867	<	#elif defined(X86_ASSEMBLY)
726	>	/* Temporarily deleted 68k/ARM flag optimizations.  I'd prefer to have
727	>	them in the appropriate m68k.h files and use just one copy of this
728	>	code here.  The API can be changed if necessary.  */
729	>	#ifdef OPTIMIZED_FLAGS
730		switch (type) {
731		case flag_add:
732		case flag_sub:
733		start_brace ();
734		printf ("\tuae_u32 %s;\n", value);
735		break;
874	–
736		default:
737		break;
738		}
#	Line 879 | Line 740 | static void genflags (flagtypes type, wo
740		/* At least some of those casts are fairly important! */
741		switch (type) {
742		case flag_logical_noclobber:
743	<	printf ("\t{uae_u32 oldcznv = regflags.cznv & ~0xC0;\n");
743	>	printf ("\t{uae_u32 oldcznv = GET_CZNV & ~(FLAGVAL_Z | FLAGVAL_N);\n");
744		if (strcmp (value, "0") == 0) {
745	<	printf ("\tregflags.cznv = olcznv | 64;\n");
745	>	printf ("\tSET_CZNV (olcznv | FLAGVAL_Z);\n");
746		} else {
747		switch (size) {
748	<	case sz_byte: printf ("\tx86_flag_testb ((uae_s8)(%s));\n", value); break;
749	<	case sz_word: printf ("\tx86_flag_testw ((uae_s16)(%s));\n", value); break;
750	<	case sz_long: printf ("\tx86_flag_testl ((uae_s32)(%s));\n", value); break;
748	>	case sz_byte: printf ("\toptflag_testb ((uae_s8)(%s));\n", value); break;
749	>	case sz_word: printf ("\toptflag_testw ((uae_s16)(%s));\n", value); break;
750	>	case sz_long: printf ("\toptflag_testl ((uae_s32)(%s));\n", value); break;
751		}
752	<	printf ("\tregflags.cznv |= oldcznv;\n");
752	>	printf ("\tIOR_CZNV (oldcznv);\n");
753		}
754		printf ("\t}\n");
755		return;
756	+
757		case flag_logical:
758		if (strcmp (value, "0") == 0) {
759	<	printf ("\tregflags.cznv = 64;\n");
759	>	printf ("\tSET_CZNV (FLAGVAL_Z);\n");
760		} else {
761		switch (size) {
762	<	case sz_byte: printf ("\tx86_flag_testb ((uae_s8)(%s));\n", value); break;
763	<	case sz_word: printf ("\tx86_flag_testw ((uae_s16)(%s));\n", value); break;
764	<	case sz_long: printf ("\tx86_flag_testl ((uae_s32)(%s));\n", value); break;
762	>	case sz_byte: printf ("\toptflag_testb ((uae_s8)(%s));\n", value); break;
763	>	case sz_word: printf ("\toptflag_testw ((uae_s16)(%s));\n", value); break;
764	>	case sz_long: printf ("\toptflag_testl ((uae_s32)(%s));\n", value); break;
765		}
766		}
767		return;
768
769		case flag_add:
770		switch (size) {
771	<	case sz_byte: printf ("\tx86_flag_addb (%s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
772	<	case sz_word: printf ("\tx86_flag_addw (%s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
773	<	case sz_long: printf ("\tx86_flag_addl (%s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
771	>	case sz_byte: printf ("\toptflag_addb (%s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
772	>	case sz_word: printf ("\toptflag_addw (%s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
773	>	case sz_long: printf ("\toptflag_addl (%s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
774		}
775		return;
776
777		case flag_sub:
778		switch (size) {
779	<	case sz_byte: printf ("\tx86_flag_subb (%s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
780	<	case sz_word: printf ("\tx86_flag_subw (%s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
781	<	case sz_long: printf ("\tx86_flag_subl (%s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
779	>	case sz_byte: printf ("\toptflag_subb (%s, (uae_s8)(%s), (uae_s8)(%s));\n", value, src, dst); break;
780	>	case sz_word: printf ("\toptflag_subw (%s, (uae_s16)(%s), (uae_s16)(%s));\n", value, src, dst); break;
781	>	case sz_long: printf ("\toptflag_subl (%s, (uae_s32)(%s), (uae_s32)(%s));\n", value, src, dst); break;
782		}
783		return;
784
785		case flag_cmp:
786		switch (size) {
787	<	case sz_byte: printf ("\tx86_flag_cmpb ((uae_s8)(%s), (uae_s8)(%s));\n", src, dst); break;
788	<	case sz_word: printf ("\tx86_flag_cmpw ((uae_s16)(%s), (uae_s16)(%s));\n", src, dst); break;
789	<	case sz_long: printf ("\tx86_flag_cmpl ((uae_s32)(%s), (uae_s32)(%s));\n", src, dst); break;
787	>	case sz_byte: printf ("\toptflag_cmpb ((uae_s8)(%s), (uae_s8)(%s));\n", src, dst); break;
788	>	case sz_word: printf ("\toptflag_cmpw ((uae_s16)(%s), (uae_s16)(%s));\n", src, dst); break;
789	>	case sz_long: printf ("\toptflag_cmpl ((uae_s32)(%s), (uae_s32)(%s));\n", src, dst); break;
790		}
791		return;
792
793		default:
794		break;
795		}
934	–	#elif defined(M68K_FLAG_OPT)
935	–	/* sam: here I'm cloning what X86_ASSEMBLY does */
936	–	#define EXT(size)  (size==sz_byte?"b":(size==sz_word?"w":"l"))
937	–	#define CAST(size) (size==sz_byte?"uae_s8":(size==sz_word?"uae_s16":"uae_s32"))
938	–	switch (type) {
939	–	case flag_add:
940	–	case flag_sub:
941	–	start_brace ();
942	–	printf ("\tuae_u32 %s;\n", value);
943	–	break;
944	–
945	–	default:
946	–	break;
947	–	}
948	–
949	–	switch (type) {
950	–	case flag_logical:
951	–	if (strcmp (value, "0") == 0) {
952	–	printf ("\t*(uae_u16 *)&regflags = 4;\n");  /* Z = 1 */
953	–	} else {
954	–	printf ("\tm68k_flag_tst (%s, (%s)(%s));\n",
955	–	EXT (size), CAST (size), value);
956	–	}
957	–	return;
958	–
959	–	case flag_add:
960	–	printf ("\t{uae_u16 ccr;\n");
961	–	printf ("\tm68k_flag_add (%s, (%s)%s, (%s)(%s), (%s)(%s));\n",
962	–	EXT (size), CAST (size), value, CAST (size), src, CAST (size), dst);
963	–	printf ("\t((uae_u16*)&regflags)[1]=((uae_u16*)&regflags)[0]=ccr;}\n");
964	–	return;
965	–
966	–	case flag_sub:
967	–	printf ("\t{uae_u16 ccr;\n");
968	–	printf ("\tm68k_flag_sub (%s, (%s)%s, (%s)(%s), (%s)(%s));\n",
969	–	EXT (size), CAST (size), value, CAST (size), src, CAST (size), dst);
970	–	printf ("\t((uae_u16*)&regflags)[1]=((uae_u16*)&regflags)[0]=ccr;}\n");
971	–	return;
972	–
973	–	case flag_cmp:
974	–	printf ("\tm68k_flag_cmp (%s, (%s)(%s), (%s)(%s));\n",
975	–	EXT (size), CAST (size), src, CAST (size), dst);
976	–	return;
977	–
978	–	default:
979	–	break;
980	–	}
981	–	#elif defined(ACORN_FLAG_OPT) && defined(__GNUC_MINOR__)
982	–	/*
983	–	* This is new. Might be quite buggy.
984	–	*/
985	–	switch (type) {
986	–	case flag_av:
987	–	case flag_sv:
988	–	case flag_zn:
989	–	case flag_addx:
990	–	case flag_subx:
991	–	break;
992	–
993	–	case flag_logical:
994	–	if (strcmp (value, "0") == 0) {
995	–	/* v=c=n=0 z=1 */
996	–	printf ("\t*(ULONG*)&regflags = 0x40000000;\n");
997	–	return;
998	–	} else {
999	–	start_brace ();
1000	–	switch (size) {
1001	–	case sz_byte:
1002	–	printf ("\tUBYTE ccr;\n");
1003	–	printf ("\tULONG shift;\n");
1004	–	printf ("\t__asm__(\"mov %%2,%%1,lsl#24\n\ttst %%2,%%2\n\tmov %%0,r15,lsr#24\n\tbic %%0,%%0,#0x30\"\n"
1005	–	"\t: \"=r\" (ccr) : \"r\" (%s), \"r\" (shift) : \"cc\" );\n", value);
1006	–	printf ("\t*((UBYTE*)&regflags+3) = ccr;\n");
1007	–	return;
1008	–	case sz_word:
1009	–	printf ("\tUBYTE ccr;\n");
1010	–	printf ("\tULONG shift;\n");
1011	–	printf ("\t__asm__(\"mov %%2,%%1,lsl#16\n\ttst %%2,%%2\n\tmov %%0,r15,lsr#24\n\tbic %%0,%%0,#0x30\"\n"
1012	–	"\t: \"=r\" (ccr) : \"r\" ((WORD)%s), \"r\" (shift) : \"cc\" );\n", value);
1013	–	printf ("\t*((UBYTE*)&regflags+3) = ccr;\n");
1014	–	return;
1015	–	case sz_long:
1016	–	printf ("\tUBYTE ccr;\n");
1017	–	printf ("\t__asm__(\"tst %%1,%%1\n\tmov %%0,r15,lsr#24\n\tbic %%0,%%0,#0x30\"\n"
1018	–	"\t: \"=r\" (ccr) : \"r\" ((LONG)%s) : \"cc\" );\n", value);
1019	–	printf ("\t*((UBYTE*)&regflags+3) = ccr;\n");
1020	–	return;
1021	–	}
1022	–	}
1023	–	break;
1024	–	case flag_add:
1025	–	if (strcmp (dst, "0") == 0) {
1026	–	printf ("/* Error! Hier muss Peter noch was machen !!! (ADD-Flags) */");
1027	–	} else {
1028	–	start_brace ();
1029	–	switch (size) {
1030	–	case sz_byte:
1031	–	printf ("\tULONG ccr, shift, %s;\n", value);
1032	–	printf ("\t__asm__(\"mov %%4,%%3,lsl#24\n\tadds %%0,%%4,%%2,lsl#24\n\tmov %%0,%%0,asr#24\n\tmov %%1,r15\n\torr %%1,%%1,%%1,lsr#29\"\n"
1033	–	"\t: \"=r\" (%s), \"=r\" (ccr) : \"r\" (%s), \"r\" (%s), \"r\" (shift) : \"cc\" );\n", value, src, dst);
1034	–	printf ("\t*(ULONG*)&regflags = ccr;\n");
1035	–	return;
1036	–	case sz_word:
1037	–	printf ("\tULONG ccr, shift, %s;\n", value);
1038	–	printf ("\t__asm__(\"mov %%4,%%3,lsl#16\n\tadds %%0,%%4,%%2,lsl#16\n\tmov %%0,%%0,asr#16\n\tmov %%1,r15\n\torr %%1,%%1,%%1,lsr#29\"\n"
1039	–	"\t: \"=r\" (%s), \"=r\" (ccr) : \"r\" ((WORD)%s), \"r\" ((WORD)%s), \"r\" (shift) : \"cc\" );\n", value, src, dst);
1040	–	printf ("\t*(ULONG*)&regflags = ccr;\n");
1041	–	return;
1042	–	case sz_long:
1043	–	printf ("\tULONG ccr, %s;\n", value);
1044	–	printf ("\t__asm__(\"adds %%0,%%3,%%2\n\tmov %%1,r15\n\torr %%1,%%1,%%1,lsr#29\"\n"
1045	–	"\t: \"=r\" (%s), \"=r\" (ccr) : \"r\" ((LONG)%s), \"r\" ((LONG)%s) : \"cc\" );\n", value, src, dst);
1046	–	printf ("\t*(ULONG*)&regflags = ccr;\n");
1047	–	return;
1048	–	}
1049	–	}
1050	–	break;
1051	–	case flag_sub:
1052	–	if (strcmp (dst, "0") == 0) {
1053	–	printf ("/* Error! Hier muss Peter noch was machen !!! (SUB-Flags) */");
1054	–	} else {
1055	–	start_brace ();
1056	–	switch (size) {
1057	–	case sz_byte:
1058	–	printf ("\tULONG ccr, shift, %s;\n", value);
1059	–	printf ("\t__asm__(\"mov %%4,%%3,lsl#24\n\tsubs %%0,%%4,%%2,lsl#24\n\tmov %%0,%%0,asr#24\n\tmov %%1,r15\n\teor %%1,%%1,#0x20000000\n\torr %%1,%%1,%%1,lsr#29\"\n"
1060	–	"\t: \"=r\" (%s), \"=r\" (ccr) : \"r\" (%s), \"r\" (%s), \"r\" (shift) : \"cc\" );\n", value, src, dst);
1061	–	printf ("\t*(ULONG*)&regflags = ccr;\n");
1062	–	return;
1063	–	case sz_word:
1064	–	printf ("\tULONG ccr, shift, %s;\n", value);
1065	–	printf ("\t__asm__(\"mov %%4,%%3,lsl#16\n\tsubs %%0,%%4,%%2,lsl#16\n\tmov %%0,%%0,asr#16\n\tmov %%1,r15\n\teor %%1,%%1,#0x20000000\n\torr %%1,%%1,%%1,lsr#29\"\n"
1066	–	"\t: \"=r\" (%s), \"=r\" (ccr) : \"r\" ((WORD)%s), \"r\" ((WORD)%s), \"r\" (shift) : \"cc\" );\n", value, src, dst);
1067	–	printf ("\t*(ULONG*)&regflags = ccr;\n");
1068	–	return;
1069	–	case sz_long:
1070	–	printf ("\tULONG ccr, %s;\n", value);
1071	–	printf ("\t__asm__(\"subs %%0,%%3,%%2\n\tmov %%1,r15\n\teor %%1,%%1,#0x20000000\n\torr %%1,%%1,%%1,lsr#29\"\n"
1072	–	"\t: \"=r\" (%s), \"=r\" (ccr) : \"r\" ((LONG)%s), \"r\" ((LONG)%s) : \"cc\" );\n", value, src, dst);
1073	–	printf ("\t*(ULONG*)&regflags = ccr;\n");
1074	–	return;
1075	–	}
1076	–	}
1077	–	break;
1078	–	case flag_cmp:
1079	–	if (strcmp (dst, "0") == 0) {
1080	–	printf ("/*Error! Hier muss Peter noch was machen !!! (CMP-Flags)*/");
1081	–	} else {
1082	–	start_brace ();
1083	–	switch (size) {
1084	–	case sz_byte:
1085	–	printf ("\tULONG shift, ccr;\n");
1086	–	printf ("\t__asm__(\"mov %%3,%%2,lsl#24\n\tcmp %%3,%%1,lsl#24\n\tmov %%0,r15,lsr#24\n\teor %%0,%%0,#0x20\"\n"
1087	–	"\t: \"=r\" (ccr) : \"r\" (%s), \"r\" (%s), \"r\" (shift) : \"cc\" );\n", src, dst);
1088	–	printf ("\t*((UBYTE*)&regflags+3) = ccr;\n");
1089	–	return;
1090	–	case sz_word:
1091	–	printf ("\tULONG shift, ccr;\n");
1092	–	printf ("\t__asm__(\"mov %%3,%%2,lsl#16\n\tcmp %%3,%%1,lsl#16\n\tmov %%0,r15,lsr#24\n\teor %%0,%%0,#0x20\"\n"
1093	–	"\t: \"=r\" (ccr) : \"r\" ((WORD)%s), \"r\" ((WORD)%s), \"r\" (shift) : \"cc\" );\n", src, dst);
1094	–	printf ("\t*((UBYTE*)&regflags+3) = ccr;\n");
1095	–	return;
1096	–	case sz_long:
1097	–	printf ("\tULONG ccr;\n");
1098	–	printf ("\t__asm__(\"cmp %%2,%%1\n\tmov %%0,r15,lsr#24\n\teor %%0,%%0,#0x20\"\n"
1099	–	"\t: \"=r\" (ccr) : \"r\" ((LONG)%s), \"r\" ((LONG)%s) : \"cc\" );\n", src, dst);
1100	–	printf ("\t*((UBYTE*)&regflags+3) = ccr;\n");
1101	–	/*printf ("\tprintf (\"%%08x %%08x %%08x\\n\", %s, %s, *((ULONG*)&regflags));\n", src, dst); */
1102	–	return;
1103	–	}
1104	–	}
1105	–	break;
1106	–	}
796		#endif
797		genflags_normal (type, size, value, src, dst);
798		}
#	Line 1228 | Line 917 | static void gen_opcode (unsigned long in
917		genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
918		break;
919		case i_SBCD:
1231	–	/* Let's hope this works... */
920		genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
921		genamode (curi->dmode, "dstreg", curi->size, "dst", 1, 0);
922		start_brace ();
923		printf ("\tuae_u16 newv_lo = (dst & 0xF) - (src & 0xF) - (GET_XFLG ? 1 : 0);\n");
924		printf ("\tuae_u16 newv_hi = (dst & 0xF0) - (src & 0xF0);\n");
925	<	printf ("\tuae_u16 newv;\n");
926	<	printf ("\tint cflg;\n");
927	<	printf ("\tif (newv_lo > 9) { newv_lo-=6; newv_hi-=0x10; }\n");
928	<	printf ("\tnewv = newv_hi + (newv_lo & 0xF);");
929	<	printf ("\tSET_CFLG (cflg = (newv_hi & 0x1F0) > 0x90);\n");
925	>	printf ("\tuae_u16 newv, tmp_newv;\n");
926	>	printf ("\tint bcd = 0;\n");
927	>	printf ("\tnewv = tmp_newv = newv_hi + newv_lo;\n");
928	>	printf ("\tif (newv_lo & 0xF0) { newv -= 6; bcd = 6; };\n");
929	>	printf ("\tif ((((dst & 0xFF) - (src & 0xFF) - (GET_XFLG ? 1 : 0)) & 0x100) > 0xFF) { newv -= 0x60; }\n");
930	>	printf ("\tSET_CFLG ((((dst & 0xFF) - (src & 0xFF) - bcd - (GET_XFLG ? 1 : 0)) & 0x300) > 0xFF);\n");
931		duplicate_carry ();
932	<	printf ("\tif (cflg) newv -= 0x60;\n");
933	<	genflags (flag_zn, curi->size, "newv", "", "");
934	<	genflags (flag_sv, curi->size, "newv", "src", "dst");
932	>	/* Manual says bits NV are undefined though a real 68040 don't change them */
933	>	if (cpu_level >= xBCD_KEEPS_NV_FLAGS) {
934	>	if (next_cpu_level < xBCD_KEEPS_NV_FLAGS)
935	>	next_cpu_level = xBCD_KEEPS_NV_FLAGS - 1;
936	>	genflags (flag_z, curi->size, "newv", "", "");
937	>	}
938	>	else {
939	>	genflags (flag_zn, curi->size, "newv", "", "");
940	>	printf ("\tSET_VFLG ((tmp_newv & 0x80) != 0 && (newv & 0x80) == 0);\n");
941	>	}
942		genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
943		break;
944		case i_ADD:
#	Line 1274 | Line 970 | static void gen_opcode (unsigned long in
970		start_brace ();
971		printf ("\tuae_u16 newv_lo = (src & 0xF) + (dst & 0xF) + (GET_XFLG ? 1 : 0);\n");
972		printf ("\tuae_u16 newv_hi = (src & 0xF0) + (dst & 0xF0);\n");
973	<	printf ("\tuae_u16 newv;\n");
973	>	printf ("\tuae_u16 newv, tmp_newv;\n");
974		printf ("\tint cflg;\n");
975	<	printf ("\tif (newv_lo > 9) { newv_lo +=6; }\n");
976	<	printf ("\tnewv = newv_hi + newv_lo;");
977	<	printf ("\tSET_CFLG (cflg = (newv & 0x1F0) > 0x90);\n");
1282	<	duplicate_carry ();
975	>	printf ("\tnewv = tmp_newv = newv_hi + newv_lo;\n");
976	>	printf ("\tif (newv_lo > 9) { newv += 6; }\n");
977	>	printf ("\tcflg = (newv & 0x3F0) > 0x90;\n");
978		printf ("\tif (cflg) newv += 0x60;\n");
979	<	genflags (flag_zn, curi->size, "newv", "", "");
980	<	genflags (flag_sv, curi->size, "newv", "src", "dst");
979	>	printf ("\tSET_CFLG (cflg);\n");
980	>	duplicate_carry ();
981	>	/* Manual says bits NV are undefined though a real 68040 don't change them */
982	>	if (cpu_level >= xBCD_KEEPS_NV_FLAGS) {
983	>	if (next_cpu_level < xBCD_KEEPS_NV_FLAGS)
984	>	next_cpu_level = xBCD_KEEPS_NV_FLAGS - 1;
985	>	genflags (flag_z, curi->size, "newv", "", "");
986	>	}
987	>	else {
988	>	genflags (flag_zn, curi->size, "newv", "", "");
989	>	printf ("\tSET_VFLG ((tmp_newv & 0x80) == 0 && (newv & 0x80) != 0);\n");
990	>	}
991		genastore ("newv", curi->dmode, "dstreg", curi->size, "dst");
992		break;
993		case i_NEG:
#	Line 1306 | Line 1011 | static void gen_opcode (unsigned long in
1011		printf ("\tuae_u16 newv_hi = - (src & 0xF0);\n");
1012		printf ("\tuae_u16 newv;\n");
1013		printf ("\tint cflg;\n");
1014	<	printf ("\tif (newv_lo > 9) { newv_lo-=6; newv_hi-=0x10; }\n");
1015	<	printf ("\tnewv = newv_hi + (newv_lo & 0xF);");
1016	<	printf ("\tSET_CFLG (cflg = (newv_hi & 0x1F0) > 0x90);\n");
1312	<	duplicate_carry();
1014	>	printf ("\tif (newv_lo > 9) { newv_lo -= 6; }\n");
1015	>	printf ("\tnewv = newv_hi + newv_lo;\n");
1016	>	printf ("\tcflg = (newv & 0x1F0) > 0x90;\n");
1017		printf ("\tif (cflg) newv -= 0x60;\n");
1018	<	genflags (flag_zn, curi->size, "newv", "", "");
1018	>	printf ("\tSET_CFLG (cflg);\n");
1019	>	duplicate_carry();
1020	>	/* Manual says bits NV are undefined though a real 68040 don't change them */
1021	>	if (cpu_level >= xBCD_KEEPS_NV_FLAGS) {
1022	>	if (next_cpu_level < xBCD_KEEPS_NV_FLAGS)
1023	>	next_cpu_level = xBCD_KEEPS_NV_FLAGS - 1;
1024	>	genflags (flag_z, curi->size, "newv", "", "");
1025	>	}
1026	>	else {
1027	>	genflags (flag_zn, curi->size, "newv", "", "");
1028	>	}
1029		genastore ("newv", curi->smode, "srcreg", curi->size, "src");
1030		break;
1031		case i_CLR:
#	Line 1347 | Line 1061 | static void gen_opcode (unsigned long in
1061		else
1062		printf ("\tsrc &= 31;\n");
1063		printf ("\tdst ^= (1 << src);\n");
1064	<	printf ("\tSET_ZFLG ((dst & (1 << src)) >> src);\n");
1064	>	printf ("\tSET_ZFLG (((uae_u32)dst & (1 << src)) >> src);\n");
1065		genastore ("dst", curi->dmode, "dstreg", curi->size, "dst");
1066		break;
1067		case i_BCLR:
#	Line 1518 | Line 1232 | static void gen_opcode (unsigned long in
1232		printf ("\tif ((format & 0xF000) == 0x0000) { break; }\n");
1233		printf ("\telse if ((format & 0xF000) == 0x1000) { ; }\n");
1234		printf ("\telse if ((format & 0xF000) == 0x2000) { m68k_areg(regs, 7) += 4; break; }\n");
1235	+	/* gb-- the next two lines are deleted in Bernie's gencpu.c */
1236		printf ("\telse if ((format & 0xF000) == 0x3000) { m68k_areg(regs, 7) += 4; break; }\n");
1237		printf ("\telse if ((format & 0xF000) == 0x7000) { m68k_areg(regs, 7) += 52; break; }\n");
1238		printf ("\telse if ((format & 0xF000) == 0x8000) { m68k_areg(regs, 7) += 50; break; }\n");
#	Line 1536 | Line 1251 | static void gen_opcode (unsigned long in
1251		m68k_pc_offset = 0;
1252		break;
1253		case i_RTD:
1539	–	printf ("\tcompiler_flush_jsr_stack();\n");
1254		genamode (Aipi, "7", sz_long, "pc", 1, 0);
1255		genamode (curi->smode, "srcreg", curi->size, "offs", 1, 0);
1256		printf ("\tm68k_areg(regs, 7) += offs;\n");
#	Line 1570 | Line 1284 | static void gen_opcode (unsigned long in
1284		need_endlabel = 1;
1285		break;
1286		case i_RTR:
1573	–	printf ("\tcompiler_flush_jsr_stack();\n");
1287		printf ("\tMakeSR();\n");
1288		genamode (Aipi, "7", sz_word, "sr", 1, 0);
1289		genamode (Aipi, "7", sz_long, "pc", 1, 0);
#	Line 1608 | Line 1321 | static void gen_opcode (unsigned long in
1321		m68k_pc_offset = 0;
1322		break;
1323		case i_Bcc:
1324	+	if (0 && !using_prefetch && !using_exception_3 && (cpu_level >= 2)) {
1325	+	/* gb-- variant probably more favorable to compiler optimizations
1326	+	also assumes no prefetch buffer is used
1327	+	Hmm, that would make sense with processors capable of conditional moves */
1328	+	if (curi->size == sz_long && next_cpu_level < 1)
1329	+	next_cpu_level = 1;
1330	+	genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1331	+	printf ("\tm68k_incpc (cctrue(%d) ? ((uae_s32)src + 2) : %d);\n", curi->cc, m68k_pc_offset);
1332	+	m68k_pc_offset = 0;
1333	+	}
1334	+	else {
1335	+	/* original code for branch instructions */
1336		if (curi->size == sz_long) {
1337		if (cpu_level < 2) {
1338		printf ("\tm68k_incpc(2);\n");
#	Line 1631 | Line 1356 | static void gen_opcode (unsigned long in
1356		printf ("\t}\n");
1357		need_endlabel = 1;
1358		}
1634	–	#ifdef USE_COMPILER
1635	–	printf ("\tm68k_setpc_bcc(m68k_getpc() + 2 + (uae_s32)src);\n");
1636	–	#else
1359		printf ("\tm68k_incpc ((uae_s32)src + 2);\n");
1638	–	#endif
1360		fill_prefetch_0 ();
1361	<	printf ("\tgoto %s;\n", endlabelstr);
1361	>	printf ("return;\n");
1362		printf ("didnt_jump:;\n");
1363		need_endlabel = 1;
1364	+	}
1365		break;
1366		case i_LEA:
1367		genamode (curi->smode, "srcreg", curi->size, "src", 0, 0);
#	Line 1667 | Line 1389 | static void gen_opcode (unsigned long in
1389		printf ("\t\t}\n");
1390		need_endlabel = 1;
1391		}
1670	–	#ifdef USE_COMPILER
1671	–	printf ("\t\t\tm68k_setpc_bcc(m68k_getpc() + (uae_s32)offs + 2);\n");
1672	–	#else
1392		printf ("\t\t\tm68k_incpc((uae_s32)offs + 2);\n");
1674	–	#endif
1393		fill_prefetch_0 ();
1394	<	printf ("\t\tgoto %s;\n", endlabelstr);
1394	>	printf ("return;\n");
1395		printf ("\t\t}\n");
1396		printf ("\t}\n");
1397		need_endlabel = 1;
#	Line 1688 | Line 1406 | static void gen_opcode (unsigned long in
1406		printf ("\tuaecptr oldpc = m68k_getpc();\n");
1407		genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1408		genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1409	<	printf ("\tif(src == 0) { Exception(5,oldpc); goto %s; } else {\n", endlabelstr);
1409	>	sync_m68k_pc ();
1410	>	/* Clear V flag when dividing by zero - Alcatraz Odyssey demo depends
1411	>	* on this (actually, it's doing a DIVS).  */
1412	>	printf ("\tif (src == 0) { SET_VFLG (0); Exception (5, oldpc); goto %s; } else {\n", endlabelstr);
1413		printf ("\tuae_u32 newv = (uae_u32)dst / (uae_u32)(uae_u16)src;\n");
1414		printf ("\tuae_u32 rem = (uae_u32)dst %% (uae_u32)(uae_u16)src;\n");
1415		/* The N flag appears to be set each time there is an overflow.
#	Line 1706 | Line 1427 | static void gen_opcode (unsigned long in
1427		printf ("\tuaecptr oldpc = m68k_getpc();\n");
1428		genamode (curi->smode, "srcreg", sz_word, "src", 1, 0);
1429		genamode (curi->dmode, "dstreg", sz_long, "dst", 1, 0);
1430	<	printf ("\tif(src == 0) { Exception(5,oldpc); goto %s; } else {\n", endlabelstr);
1430	>	sync_m68k_pc ();
1431	>	printf ("\tif (src == 0) { SET_VFLG (0); Exception(5,oldpc); goto %s; } else {\n", endlabelstr);
1432		printf ("\tuae_s32 newv = (uae_s32)dst / (uae_s32)(uae_s16)src;\n");
1433		printf ("\tuae_u16 rem = (uae_s32)dst %% (uae_s32)(uae_s16)src;\n");
1434		printf ("\tif ((newv & 0xffff8000) != 0 && (newv & 0xffff8000) != 0xffff8000) { SET_VFLG (1); SET_NFLG (1); SET_CFLG (0); } else\n\t{\n");
#	Line 1767 | Line 1489 | static void gen_opcode (unsigned long in
1489		abort ();
1490		}
1491		printf ("\tSET_ZFLG (upper == reg || lower == reg);\n");
1492	<	printf ("\tSET_CFLG (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);\n");
1492	>	printf ("\tSET_CFLG_ALWAYS (lower <= upper ? reg < lower || reg > upper : reg > upper || reg < lower);\n");
1493		printf ("\tif ((extra & 0x800) && GET_CFLG) { Exception(6,oldpc); goto %s; }\n}\n", endlabelstr);
1494		need_endlabel = 1;
1495		break;
#	Line 1966 | Line 1688 | static void gen_opcode (unsigned long in
1688		}
1689		printf ("\tcnt &= 63;\n");
1690		printf ("\tCLEAR_CZNV;\n");
1969	–	if (! source_is_imm1_8 (curi))
1970	–	force_range_for_rox ("cnt", curi->size);
1691		if (source_is_imm1_8 (curi))
1692		printf ("{");
1693	<	else
1693	>	else {
1694	>	force_range_for_rox ("cnt", curi->size);
1695		printf ("\tif (cnt > 0) {\n");
1696	+	}
1697		printf ("\tcnt--;\n");
1698		printf ("\t{\n\tuae_u32 carry;\n");
1699		printf ("\tuae_u32 loval = val >> (%d - cnt);\n", bit_size (curi->size) - 1);
#	Line 1996 | Line 1718 | static void gen_opcode (unsigned long in
1718		}
1719		printf ("\tcnt &= 63;\n");
1720		printf ("\tCLEAR_CZNV;\n");
1999	–	if (! source_is_imm1_8 (curi))
2000	–	force_range_for_rox ("cnt", curi->size);
1721		if (source_is_imm1_8 (curi))
1722		printf ("{");
1723	<	else
1723	>	else {
1724	>	force_range_for_rox ("cnt", curi->size);
1725		printf ("\tif (cnt > 0) {\n");
1726	+	}
1727		printf ("\tcnt--;\n");
1728		printf ("\t{\n\tuae_u32 carry;\n");
1729		printf ("\tuae_u32 hival = (val << 1) | GET_XFLG;\n");
#	Line 2157 | Line 1879 | static void gen_opcode (unsigned long in
1879		start_brace ();
1880		printf ("\tint regno = (src >> 12) & 15;\n");
1881		printf ("\tuae_u32 *regp = regs.regs + regno;\n");
1882	<	printf ("\tm68k_movec2(src & 0xFFF, regp);\n");
1882	>	printf ("\tif (! m68k_movec2(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
1883		break;
1884		case i_MOVE2C:
1885		genamode (curi->smode, "srcreg", curi->size, "src", 1, 0);
1886		start_brace ();
1887		printf ("\tint regno = (src >> 12) & 15;\n");
1888		printf ("\tuae_u32 *regp = regs.regs + regno;\n");
1889	<	printf ("\tm68k_move2c(src & 0xFFF, regp);\n");
1889	>	printf ("\tif (! m68k_move2c(src & 0xFFF, regp)) goto %s;\n", endlabelstr);
1890		break;
1891		case i_CAS:
1892		{
#	Line 2304 | Line 2026 | static void gen_opcode (unsigned long in
2026		printf ("\ttmp = (bf0 << (offset & 7)) | (bf1 >> (8 - (offset & 7)));\n");
2027		}
2028		printf ("\ttmp >>= (32 - width);\n");
2029	<	printf ("\tSET_NFLG (tmp & (1 << (width-1)) ? 1 : 0);\n");
2029	>	printf ("\tSET_NFLG_ALWAYS (tmp & (1 << (width-1)) ? 1 : 0);\n");
2030		printf ("\tSET_ZFLG (tmp == 0); SET_VFLG (0); SET_CFLG (0);\n");
2031		switch (curi->mnemo) {
2032		case i_BFTST:
#	Line 2332 | Line 2054 | static void gen_opcode (unsigned long in
2054		break;
2055		case i_BFINS:
2056		printf ("\ttmp = m68k_dreg(regs, (extra >> 12) & 7);\n");
2057	+	printf ("\tSET_NFLG_ALWAYS (tmp & (1 << (width - 1)) ? 1 : 0);\n");
2058	+	printf ("\tSET_ZFLG (tmp == 0);\n");
2059		break;
2060		default:
2061		break;
#	Line 2402 | Line 2126 | static void gen_opcode (unsigned long in
2126		genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2127		sync_m68k_pc ();
2128		swap_opcode ();
2129	<	printf ("\tfpp_opp(opcode,extra);\n");
2129	>	printf ("\tfpuop_arithmetic(opcode, extra);\n");
2130		break;
2131		case i_FDBcc:
2132		genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2133		sync_m68k_pc ();
2134		swap_opcode ();
2135	<	printf ("\tfdbcc_opp(opcode,extra);\n");
2135	>	printf ("\tfpuop_dbcc(opcode, extra);\n");
2136		break;
2137		case i_FScc:
2138		genamode (curi->smode, "srcreg", curi->size, "extra", 1, 0);
2139		sync_m68k_pc ();
2140		swap_opcode ();
2141	<	printf ("\tfscc_opp(opcode,extra);\n");
2141	>	printf ("\tfpuop_scc(opcode,extra);\n");
2142		break;
2143		case i_FTRAPcc:
2144		sync_m68k_pc ();
#	Line 2424 | Line 2148 | static void gen_opcode (unsigned long in
2148		genamode (curi->smode, "srcreg", curi->size, "dummy", 1, 0);
2149		sync_m68k_pc ();
2150		swap_opcode ();
2151	<	printf ("\tftrapcc_opp(opcode,oldpc);\n");
2151	>	printf ("\tfpuop_trapcc(opcode,oldpc);\n");
2152		break;
2153		case i_FBcc:
2154		sync_m68k_pc ();
#	Line 2433 | Line 2157 | static void gen_opcode (unsigned long in
2157		genamode (curi->dmode, "srcreg", curi->size, "extra", 1, 0);
2158		sync_m68k_pc ();
2159		swap_opcode ();
2160	<	printf ("\tfbcc_opp(opcode,pc,extra);\n");
2160	>	printf ("\tfpuop_bcc(opcode,pc,extra);\n");
2161		break;
2162		case i_FSAVE:
2163		sync_m68k_pc ();
2164		swap_opcode ();
2165	<	printf ("\tfsave_opp(opcode);\n");
2165	>	printf ("\tfpuop_save(opcode);\n");
2166		break;
2167		case i_FRESTORE:
2168		sync_m68k_pc ();
2169		swap_opcode ();
2170	<	printf ("\tfrestore_opp(opcode);\n");
2170	>	printf ("\tfpuop_restore(opcode);\n");
2171		break;
2172		case i_CINVL:
2173		case i_CINVP:
2174		case i_CINVA:
2175	+	/* gb-- srcreg now contains the cache field */
2176	+	printf ("\tif (srcreg&0x2)\n");
2177	+	printf ("\t\tflush_icache(%d);\n", 30 + ((opcode >> 3) & 3));
2178	+	break;
2179		case i_CPUSHL:
2180		case i_CPUSHP:
2181		case i_CPUSHA:
2182	+	/* gb-- srcreg now contains the cache field */
2183	+	printf ("\tif (srcreg&0x2)\n");
2184	+	printf ("\t\tflush_icache(%d);\n", 40 + ((opcode >> 3) & 3));
2185		break;
2186		case i_MOVE16:
2187		if ((opcode & 0xfff8) == 0xf620) {
#	Line 2488 | Line 2219 | static void gen_opcode (unsigned long in
2219		swap_opcode ();
2220		printf ("\tmmu_op(opcode,extra);\n");
2221		break;
2222	+
2223	+	case i_EMULOP_RETURN:
2224	+	printf ("\tm68k_emulop_return();\n");
2225	+	m68k_pc_offset = 0;
2226	+	break;
2227	+
2228	+	case i_EMULOP:
2229	+	printf ("\n");
2230	+	swap_opcode ();
2231	+	printf ("\tm68k_emulop(opcode);\n");
2232	+	break;
2233	+
2234		default:
2235		abort ();
2236		break;
#	Line 2499 | Line 2242 | static void gen_opcode (unsigned long in
2242		static void generate_includes (FILE * f)
2243		{
2244		fprintf (f, "#include \"sysdeps.h\"\n");
2245	+
2246		fprintf (f, "#include \"m68k.h\"\n");
2247		fprintf (f, "#include \"memory.h\"\n");
2248		fprintf (f, "#include \"readcpu.h\"\n");
2249		fprintf (f, "#include \"newcpu.h\"\n");
2250	<	fprintf (f, "#include \"compiler.h\"\n");
2250	>	fprintf (f, "#include \"compiler/compemu.h\"\n");
2251	>	fprintf (f, "#include \"fpu/fpu.h\"\n");
2252		fprintf (f, "#include \"cputbl.h\"\n");
2253	+
2254	+	fprintf (f, "#define SET_CFLG_ALWAYS(x) SET_CFLG(x)\n");
2255	+	fprintf (f, "#define SET_NFLG_ALWAYS(x) SET_NFLG(x)\n");
2256	+	fprintf (f, "#define CPUFUNC_FF(x) x##_ff\n");
2257	+	fprintf (f, "#define CPUFUNC_NF(x) x##_nf\n");
2258	+	fprintf (f, "#define CPUFUNC(x) CPUFUNC_FF(x)\n");
2259	+
2260	+	fprintf (f, "#ifdef NOFLAGS\n");
2261	+	fprintf (f, "# include \"noflags.h\"\n");
2262	+	fprintf (f, "#endif\n");
2263		}
2264
2265		static int postfix;
2266
2267		static void generate_one_opcode (int rp)
2268		{
2514	–	int i;
2269		uae_u16 smsk, dmsk;
2270		long int opcode = opcode_map[rp];
2271	+	const char *opcode_str;
2272
2273		if (table68k[opcode].mnemo == i_ILLG
2274		|| table68k[opcode].clev > cpu_level)
2275		return;
2276
2522	–	for (i = 0; lookuptab[i].name[0]; i++) {
2523	–	if (table68k[opcode].mnemo == lookuptab[i].mnemo)
2524	–	break;
2525	–	}
2526	–
2277		if (table68k[opcode].handler != -1)
2278		return;
2279
2280	+	opcode_str = get_instruction_string (opcode);
2281	+
2282		if (opcode_next_clev[rp] != cpu_level) {
2283	<	fprintf (stblfile, "{ op_%lx_%d, 0, %ld }, /* %s */\n", opcode, opcode_last_postfix[rp],
2284	<	opcode, lookuptab[i].name);
2283	>	if (table68k[opcode].flagdead == 0)
2284	>	/* force to the "ff" variant since the instruction doesn't set at all the condition codes */
2285	>	fprintf (stblfile, "{ CPUFUNC_FF(op_%lx_%d), 0, %ld }, /* %s */\n", opcode, opcode_last_postfix[rp],
2286	>	opcode, opcode_str);
2287	>	else
2288	>	fprintf (stblfile, "{ CPUFUNC(op_%lx_%d), 0, %ld }, /* %s */\n", opcode, opcode_last_postfix[rp],
2289	>	opcode, opcode_str);
2290		return;
2291		}
2292	<	fprintf (stblfile, "{ op_%lx_%d, 0, %ld }, /* %s */\n", opcode, postfix, opcode, lookuptab[i].name);
2293	<	fprintf (headerfile, "extern cpuop_func op_%lx_%d;\n", opcode, postfix);
2294	<	printf ("void REGPARAM2 op_%lx_%d(uae_u32 opcode) /* %s */\n{\n", opcode, postfix, lookuptab[i].name);
2292	>
2293	>	if (table68k[opcode].flagdead == 0)
2294	>	/* force to the "ff" variant since the instruction doesn't set at all the condition codes */
2295	>	fprintf (stblfile, "{ CPUFUNC_FF(op_%lx_%d), 0, %ld }, /* %s */\n", opcode, postfix, opcode, opcode_str);
2296	>	else
2297	>	fprintf (stblfile, "{ CPUFUNC(op_%lx_%d), 0, %ld }, /* %s */\n", opcode, postfix, opcode, opcode_str);
2298	>
2299	>	fprintf (headerfile, "extern cpuop_func op_%lx_%d_nf;\n", opcode, postfix);
2300	>	fprintf (headerfile, "extern cpuop_func op_%lx_%d_ff;\n", opcode, postfix);
2301	>
2302	>	/* gb-- The "nf" variant for an instruction that doesn't set the condition
2303	>	codes at all is the same as the "ff" variant, so we don't need the "nf"
2304	>	variant to be compiled since it is mapped to the "ff" variant in the
2305	>	smalltbl. */
2306	>	if (table68k[opcode].flagdead == 0)
2307	>	printf ("#ifndef NOFLAGS\n");
2308	>
2309	>	printf ("void REGPARAM2 CPUFUNC(op_%lx_%d)(uae_u32 opcode) /* %s */\n{\n", opcode, postfix, opcode_str);
2310	>	printf ("\tcpuop_begin();\n");
2311
2312		switch (table68k[opcode].stype) {
2313		case 0: smsk = 7; break;
#	Line 2543 | Line 2316 | static void generate_one_opcode (int rp)
2316		case 3: smsk = 7; break;
2317		case 4: smsk = 7; break;
2318		case 5: smsk = 63; break;
2319	+	case 6: smsk = 255; break;
2320		case 7: smsk = 3; break;
2321		default: abort ();
2322		}
#	Line 2553 | Line 2327 | static void generate_one_opcode (int rp)
2327		&& table68k[opcode].smode != imm && table68k[opcode].smode != imm0
2328		&& table68k[opcode].smode != imm1 && table68k[opcode].smode != imm2
2329		&& table68k[opcode].smode != absw && table68k[opcode].smode != absl
2330	<	&& table68k[opcode].smode != PC8r && table68k[opcode].smode != PC16)
2330	>	&& table68k[opcode].smode != PC8r && table68k[opcode].smode != PC16
2331	>	/* gb-- We don't want to fetch the EmulOp code since the EmulOp()
2332	>	routine uses the whole opcode value. Maybe all the EmulOps
2333	>	could be expanded out but I don't think it is an improvement */
2334	>	&& table68k[opcode].stype != 6
2335	>	)
2336		{
2337		if (table68k[opcode].spos == -1) {
2338		if (((int) table68k[opcode].sreg) >= 128)
#	Line 2649 | Line 2428 | static void generate_one_opcode (int rp)
2428		gen_opcode (opcode);
2429		if (need_endlabel)
2430		printf ("%s: ;\n", endlabelstr);
2431	+	printf ("\tcpuop_end();\n");
2432		printf ("}\n");
2433	+	if (table68k[opcode].flagdead == 0)
2434	+	printf ("\n#endif\n");
2435		opcode_next_clev[rp] = next_cpu_level;
2436		opcode_last_postfix[rp] = postfix;
2437		}
#	Line 2676 | Line 2458 | static void generate_func (void)
2458		opcode_next_clev[rp] = 0;
2459		}
2460		postfix = i;
2461	<	fprintf (stblfile, "struct cputbl op_smalltbl_%d[] = {\n", postfix);
2461	>	fprintf (stblfile, "struct cputbl CPUFUNC(op_smalltbl_%d)[] = {\n", postfix);
2462
2463		/* sam: this is for people with low memory (eg. me :)) */
2464		printf ("\n"
#	Line 2710 | Line 2492 | static void generate_func (void)
2492
2493		int main (int argc, char **argv)
2494		{
2495	+	FILE *out;
2496		read_table68k ();
2497		do_merges ();
2498
#	Line 2723 | Line 2506 | int main (int argc, char **argv)
2506		* cputbl.h that way), but cpuopti can't cope.  That could be fixed, but
2507		* I don't dare to touch the 68k version.  */
2508
2509	<	headerfile = fopen ("cputbl.h", "wb");
2510	<	stblfile = fopen ("cpustbl.cpp", "wb");
2511	<	freopen ("cpuemu.cpp", "wb", stdout);
2509	>	headerfile = fopen ("cputbl.h", "w");
2510	>	stblfile = fopen ("cpustbl.cpp", "w");
2511	>	out = freopen ("cpuemu.cpp", "w", stdout);
2512
2513		generate_includes (stdout);
2514		generate_includes (stblfile);
#	Line 2733 | Line 2516 | int main (int argc, char **argv)
2516		generate_func ();
2517
2518		free (table68k);
2519	+	fclose (headerfile);
2520	+	fclose (stblfile);
2521	+	fflush (out);
2522		return 0;
2523		}

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