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/* |
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* CIA_SC.cpp - Single-cycle 6526 emulation |
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* |
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* Frodo Copyright (C) Christian Bauer |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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*/ |
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|
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/* |
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* Notes: |
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* ------ |
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* |
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* - The Emulate() function is called for every emulated Phi2 |
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* clock cycle. It counts down the timers and triggers |
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* interrupts if necessary. |
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* - The TOD clocks are counted by CountTOD() during the VBlank, so |
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* the input frequency is 50Hz |
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* - The fields KeyMatrix and RevMatrix contain one bit for each |
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* key on the C64 keyboard (0: key pressed, 1: key released). |
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* KeyMatrix is used for normal keyboard polling (PRA->PRB), |
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* RevMatrix for reversed polling (PRB->PRA). |
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* |
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* Incompatibilities: |
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* ------------------ |
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* |
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* - The TOD clock should not be stopped on a read access, but be |
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* latched |
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* - The SDR interrupt is faked |
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* - Some small incompatibilities with the timers |
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*/ |
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|
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#include "sysdeps.h" |
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|
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#include "CIA.h" |
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#include "CPUC64.h" |
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#include "CPU1541.h" |
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#include "VIC.h" |
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#include "Prefs.h" |
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|
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|
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// Timer states |
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enum { |
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T_STOP, |
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T_WAIT_THEN_COUNT, |
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T_LOAD_THEN_STOP, |
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T_LOAD_THEN_COUNT, |
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T_LOAD_THEN_WAIT_THEN_COUNT, |
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T_COUNT, |
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T_COUNT_THEN_STOP |
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}; |
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|
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|
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/* |
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* Constructors |
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*/ |
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|
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MOS6526::MOS6526(MOS6510 *CPU) : the_cpu(CPU) {} |
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MOS6526_1::MOS6526_1(MOS6510 *CPU, MOS6569 *VIC) : MOS6526(CPU), the_vic(VIC) {} |
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MOS6526_2::MOS6526_2(MOS6510 *CPU, MOS6569 *VIC, MOS6502_1541 *CPU1541) : MOS6526(CPU), the_vic(VIC), the_cpu_1541(CPU1541) {} |
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|
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|
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/* |
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* Reset the CIA |
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*/ |
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|
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void MOS6526::Reset(void) |
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{ |
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pra = prb = ddra = ddrb = 0; |
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|
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ta = tb = 0xffff; |
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latcha = latchb = 1; |
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|
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tod_10ths = tod_sec = tod_min = tod_hr = 0; |
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alm_10ths = alm_sec = alm_min = alm_hr = 0; |
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|
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sdr = icr = cra = crb = int_mask = 0; |
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|
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tod_halt = false; |
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tod_divider = 0; |
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|
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ta_cnt_phi2 = tb_cnt_phi2 = tb_cnt_ta = false; |
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|
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ta_irq_next_cycle = tb_irq_next_cycle = false; |
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has_new_cra = has_new_crb = false; |
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ta_state = tb_state = T_STOP; |
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} |
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|
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void MOS6526_1::Reset(void) |
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{ |
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MOS6526::Reset(); |
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|
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// Clear keyboard matrix and joystick states |
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for (int i=0; i<8; i++) |
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KeyMatrix[i] = RevMatrix[i] = 0xff; |
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|
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Joystick1 = Joystick2 = 0xff; |
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prev_lp = 0x10; |
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} |
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|
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void MOS6526_2::Reset(void) |
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{ |
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MOS6526::Reset(); |
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|
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// VA14/15 = 0 |
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the_vic->ChangedVA(0); |
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|
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// IEC |
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IECLines = 0xd0; |
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} |
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|
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|
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/* |
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* Get CIA state |
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*/ |
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|
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void MOS6526::GetState(MOS6526State *cs) |
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{ |
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cs->pra = pra; |
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cs->prb = prb; |
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cs->ddra = ddra; |
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cs->ddrb = ddrb; |
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|
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cs->ta_lo = ta & 0xff; |
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cs->ta_hi = ta >> 8; |
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cs->tb_lo = tb & 0xff; |
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cs->tb_hi = tb >> 8; |
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cs->latcha = latcha; |
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cs->latchb = latchb; |
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cs->cra = cra; |
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cs->crb = crb; |
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|
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cs->tod_10ths = tod_10ths; |
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cs->tod_sec = tod_sec; |
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cs->tod_min = tod_min; |
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cs->tod_hr = tod_hr; |
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cs->alm_10ths = alm_10ths; |
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cs->alm_sec = alm_sec; |
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cs->alm_min = alm_min; |
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cs->alm_hr = alm_hr; |
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|
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cs->sdr = sdr; |
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|
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cs->int_data = icr; |
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cs->int_mask = int_mask; |
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} |
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|
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|
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/* |
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* Restore CIA state |
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*/ |
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|
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void MOS6526::SetState(MOS6526State *cs) |
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{ |
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pra = cs->pra; |
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prb = cs->prb; |
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ddra = cs->ddra; |
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ddrb = cs->ddrb; |
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|
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ta = (cs->ta_hi << 8) | cs->ta_lo; |
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tb = (cs->tb_hi << 8) | cs->tb_lo; |
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latcha = cs->latcha; |
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latchb = cs->latchb; |
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cra = cs->cra; |
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crb = cs->crb; |
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|
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tod_10ths = cs->tod_10ths; |
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tod_sec = cs->tod_sec; |
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tod_min = cs->tod_min; |
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tod_hr = cs->tod_hr; |
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alm_10ths = cs->alm_10ths; |
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alm_sec = cs->alm_sec; |
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alm_min = cs->alm_min; |
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alm_hr = cs->alm_hr; |
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|
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sdr = cs->sdr; |
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|
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icr = cs->int_data; |
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int_mask = cs->int_mask; |
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|
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tod_halt = false; |
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ta_cnt_phi2 = ((cra & 0x20) == 0x00); |
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tb_cnt_phi2 = ((crb & 0x60) == 0x00); |
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tb_cnt_ta = ((crb & 0x60) == 0x40); |
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|
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ta_state = (cra & 1) ? T_COUNT : T_STOP; |
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tb_state = (crb & 1) ? T_COUNT : T_STOP; |
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} |
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|
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|
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/* |
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* Read from register (CIA 1) |
204 |
*/ |
205 |
|
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uint8 MOS6526_1::ReadRegister(uint16 adr) |
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{ |
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switch (adr) { |
209 |
case 0x00: { |
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uint8 ret = pra | ~ddra, tst = (prb | ~ddrb) & Joystick1; |
211 |
if (!(tst & 0x01)) ret &= RevMatrix[0]; // AND all active columns |
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if (!(tst & 0x02)) ret &= RevMatrix[1]; |
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if (!(tst & 0x04)) ret &= RevMatrix[2]; |
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if (!(tst & 0x08)) ret &= RevMatrix[3]; |
215 |
if (!(tst & 0x10)) ret &= RevMatrix[4]; |
216 |
if (!(tst & 0x20)) ret &= RevMatrix[5]; |
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if (!(tst & 0x40)) ret &= RevMatrix[6]; |
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if (!(tst & 0x80)) ret &= RevMatrix[7]; |
219 |
return ret & Joystick2; |
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} |
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case 0x01: { |
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uint8 ret = ~ddrb, tst = (pra | ~ddra) & Joystick2; |
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if (!(tst & 0x01)) ret &= KeyMatrix[0]; // AND all active rows |
224 |
if (!(tst & 0x02)) ret &= KeyMatrix[1]; |
225 |
if (!(tst & 0x04)) ret &= KeyMatrix[2]; |
226 |
if (!(tst & 0x08)) ret &= KeyMatrix[3]; |
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if (!(tst & 0x10)) ret &= KeyMatrix[4]; |
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if (!(tst & 0x20)) ret &= KeyMatrix[5]; |
229 |
if (!(tst & 0x40)) ret &= KeyMatrix[6]; |
230 |
if (!(tst & 0x80)) ret &= KeyMatrix[7]; |
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return (ret | (prb & ddrb)) & Joystick1; |
232 |
} |
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case 0x02: return ddra; |
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case 0x03: return ddrb; |
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case 0x04: return ta; |
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case 0x05: return ta >> 8; |
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case 0x06: return tb; |
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case 0x07: return tb >> 8; |
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case 0x08: tod_halt = false; return tod_10ths; |
240 |
case 0x09: return tod_sec; |
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case 0x0a: return tod_min; |
242 |
case 0x0b: tod_halt = true; return tod_hr; |
243 |
case 0x0c: return sdr; |
244 |
case 0x0d: { |
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uint8 ret = icr; // Read and clear ICR |
246 |
icr = 0; |
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the_cpu->ClearCIAIRQ(); // Clear IRQ |
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return ret; |
249 |
} |
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case 0x0e: return cra; |
251 |
case 0x0f: return crb; |
252 |
} |
253 |
return 0; // Can't happen |
254 |
} |
255 |
|
256 |
|
257 |
/* |
258 |
* Read from register (CIA 2) |
259 |
*/ |
260 |
|
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uint8 MOS6526_2::ReadRegister(uint16 adr) |
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{ |
263 |
switch (adr) { |
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case 0x00: |
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return (pra | ~ddra) & 0x3f |
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| IECLines & the_cpu_1541->IECLines; |
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case 0x01: return prb | ~ddrb; |
268 |
case 0x02: return ddra; |
269 |
case 0x03: return ddrb; |
270 |
case 0x04: return ta; |
271 |
case 0x05: return ta >> 8; |
272 |
case 0x06: return tb; |
273 |
case 0x07: return tb >> 8; |
274 |
case 0x08: tod_halt = false; return tod_10ths; |
275 |
case 0x09: return tod_sec; |
276 |
case 0x0a: return tod_min; |
277 |
case 0x0b: tod_halt = true; return tod_hr; |
278 |
case 0x0c: return sdr; |
279 |
case 0x0d: { |
280 |
uint8 ret = icr; // Read and clear ICR |
281 |
icr = 0; |
282 |
the_cpu->ClearNMI(); |
283 |
return ret; |
284 |
} |
285 |
case 0x0e: return cra; |
286 |
case 0x0f: return crb; |
287 |
} |
288 |
return 0; // Can't happen |
289 |
} |
290 |
|
291 |
|
292 |
/* |
293 |
* Write to register (CIA 1) |
294 |
*/ |
295 |
|
296 |
// Write to port B, check for lightpen interrupt |
297 |
inline void MOS6526_1::check_lp(void) |
298 |
{ |
299 |
if ((prb | ~ddrb) & 0x10 != prev_lp) |
300 |
the_vic->TriggerLightpen(); |
301 |
prev_lp = (prb | ~ddrb) & 0x10; |
302 |
} |
303 |
|
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void MOS6526_1::WriteRegister(uint16 adr, uint8 byte) |
305 |
{ |
306 |
switch (adr) { |
307 |
case 0x0: pra = byte; break; |
308 |
case 0x1: |
309 |
prb = byte; |
310 |
check_lp(); |
311 |
break; |
312 |
case 0x2: ddra = byte; break; |
313 |
case 0x3: |
314 |
ddrb = byte; |
315 |
check_lp(); |
316 |
break; |
317 |
|
318 |
case 0x4: latcha = (latcha & 0xff00) | byte; break; |
319 |
case 0x5: |
320 |
latcha = (latcha & 0xff) | (byte << 8); |
321 |
if (!(cra & 1)) // Reload timer if stopped |
322 |
ta = latcha; |
323 |
break; |
324 |
|
325 |
case 0x6: latchb = (latchb & 0xff00) | byte; break; |
326 |
case 0x7: |
327 |
latchb = (latchb & 0xff) | (byte << 8); |
328 |
if (!(crb & 1)) // Reload timer if stopped |
329 |
tb = latchb; |
330 |
break; |
331 |
|
332 |
case 0x8: |
333 |
if (crb & 0x80) |
334 |
alm_10ths = byte & 0x0f; |
335 |
else |
336 |
tod_10ths = byte & 0x0f; |
337 |
break; |
338 |
case 0x9: |
339 |
if (crb & 0x80) |
340 |
alm_sec = byte & 0x7f; |
341 |
else |
342 |
tod_sec = byte & 0x7f; |
343 |
break; |
344 |
case 0xa: |
345 |
if (crb & 0x80) |
346 |
alm_min = byte & 0x7f; |
347 |
else |
348 |
tod_min = byte & 0x7f; |
349 |
break; |
350 |
case 0xb: |
351 |
if (crb & 0x80) |
352 |
alm_hr = byte & 0x9f; |
353 |
else |
354 |
tod_hr = byte & 0x9f; |
355 |
break; |
356 |
|
357 |
case 0xc: |
358 |
sdr = byte; |
359 |
TriggerInterrupt(8); // Fake SDR interrupt for programs that need it |
360 |
break; |
361 |
|
362 |
case 0xd: |
363 |
if (byte & 0x80) |
364 |
int_mask |= byte & 0x7f; |
365 |
else |
366 |
int_mask &= ~byte; |
367 |
if (icr & int_mask & 0x1f) { // Trigger IRQ if pending |
368 |
icr |= 0x80; |
369 |
the_cpu->TriggerCIAIRQ(); |
370 |
} |
371 |
break; |
372 |
|
373 |
case 0xe: |
374 |
has_new_cra = true; // Delay write by 1 cycle |
375 |
new_cra = byte; |
376 |
ta_cnt_phi2 = ((byte & 0x20) == 0x00); |
377 |
break; |
378 |
|
379 |
case 0xf: |
380 |
has_new_crb = true; // Delay write by 1 cycle |
381 |
new_crb = byte; |
382 |
tb_cnt_phi2 = ((byte & 0x60) == 0x00); |
383 |
tb_cnt_ta = ((byte & 0x60) == 0x40); |
384 |
break; |
385 |
} |
386 |
} |
387 |
|
388 |
|
389 |
/* |
390 |
* Write to register (CIA 2) |
391 |
*/ |
392 |
|
393 |
void MOS6526_2::WriteRegister(uint16 adr, uint8 byte) |
394 |
{ |
395 |
switch (adr) { |
396 |
case 0x0:{ |
397 |
pra = byte; |
398 |
the_vic->ChangedVA(~(pra | ~ddra) & 3); |
399 |
uint8 old_lines = IECLines; |
400 |
IECLines = (~byte << 2) & 0x80 // DATA |
401 |
| (~byte << 2) & 0x40 // CLK |
402 |
| (~byte << 1) & 0x10; // ATN |
403 |
if ((IECLines ^ old_lines) & 0x10) { // ATN changed |
404 |
the_cpu_1541->NewATNState(); |
405 |
if (old_lines & 0x10) // ATN 1->0 |
406 |
the_cpu_1541->IECInterrupt(); |
407 |
} |
408 |
break; |
409 |
} |
410 |
case 0x1: prb = byte; break; |
411 |
|
412 |
case 0x2: |
413 |
ddra = byte; |
414 |
the_vic->ChangedVA(~(pra | ~ddra) & 3); |
415 |
break; |
416 |
case 0x3: ddrb = byte; break; |
417 |
|
418 |
case 0x4: latcha = (latcha & 0xff00) | byte; break; |
419 |
case 0x5: |
420 |
latcha = (latcha & 0xff) | (byte << 8); |
421 |
if (!(cra & 1)) // Reload timer if stopped |
422 |
ta = latcha; |
423 |
break; |
424 |
|
425 |
case 0x6: latchb = (latchb & 0xff00) | byte; break; |
426 |
case 0x7: |
427 |
latchb = (latchb & 0xff) | (byte << 8); |
428 |
if (!(crb & 1)) // Reload timer if stopped |
429 |
tb = latchb; |
430 |
break; |
431 |
|
432 |
case 0x8: |
433 |
if (crb & 0x80) |
434 |
alm_10ths = byte & 0x0f; |
435 |
else |
436 |
tod_10ths = byte & 0x0f; |
437 |
break; |
438 |
case 0x9: |
439 |
if (crb & 0x80) |
440 |
alm_sec = byte & 0x7f; |
441 |
else |
442 |
tod_sec = byte & 0x7f; |
443 |
break; |
444 |
case 0xa: |
445 |
if (crb & 0x80) |
446 |
alm_min = byte & 0x7f; |
447 |
else |
448 |
tod_min = byte & 0x7f; |
449 |
break; |
450 |
case 0xb: |
451 |
if (crb & 0x80) |
452 |
alm_hr = byte & 0x9f; |
453 |
else |
454 |
tod_hr = byte & 0x9f; |
455 |
break; |
456 |
|
457 |
case 0xc: |
458 |
sdr = byte; |
459 |
TriggerInterrupt(8); // Fake SDR interrupt for programs that need it |
460 |
break; |
461 |
|
462 |
case 0xd: |
463 |
if (byte & 0x80) |
464 |
int_mask |= byte & 0x7f; |
465 |
else |
466 |
int_mask &= ~byte; |
467 |
if (icr & int_mask & 0x1f) { // Trigger NMI if pending |
468 |
icr |= 0x80; |
469 |
the_cpu->TriggerNMI(); |
470 |
} |
471 |
break; |
472 |
|
473 |
case 0xe: |
474 |
has_new_cra = true; // Delay write by 1 cycle |
475 |
new_cra = byte; |
476 |
ta_cnt_phi2 = ((byte & 0x20) == 0x00); |
477 |
break; |
478 |
|
479 |
case 0xf: |
480 |
has_new_crb = true; // Delay write by 1 cycle |
481 |
new_crb = byte; |
482 |
tb_cnt_phi2 = ((byte & 0x60) == 0x00); |
483 |
tb_cnt_ta = ((byte & 0x60) == 0x40); |
484 |
break; |
485 |
} |
486 |
} |
487 |
|
488 |
|
489 |
/* |
490 |
* Emulate CIA for one cycle/raster line |
491 |
*/ |
492 |
|
493 |
void MOS6526::EmulateCycle(void) |
494 |
{ |
495 |
bool ta_underflow = false; |
496 |
|
497 |
// Timer A state machine |
498 |
switch (ta_state) { |
499 |
case T_WAIT_THEN_COUNT: |
500 |
ta_state = T_COUNT; // fall through |
501 |
case T_STOP: |
502 |
goto ta_idle; |
503 |
case T_LOAD_THEN_STOP: |
504 |
ta_state = T_STOP; |
505 |
ta = latcha; // Reload timer |
506 |
goto ta_idle; |
507 |
case T_LOAD_THEN_COUNT: |
508 |
ta_state = T_COUNT; |
509 |
ta = latcha; // Reload timer |
510 |
goto ta_idle; |
511 |
case T_LOAD_THEN_WAIT_THEN_COUNT: |
512 |
ta_state = T_WAIT_THEN_COUNT; |
513 |
if (ta == 1) |
514 |
goto ta_interrupt; // Interrupt if timer == 1 |
515 |
else { |
516 |
ta = latcha; // Reload timer |
517 |
goto ta_idle; |
518 |
} |
519 |
case T_COUNT: |
520 |
goto ta_count; |
521 |
case T_COUNT_THEN_STOP: |
522 |
ta_state = T_STOP; |
523 |
goto ta_count; |
524 |
} |
525 |
|
526 |
// Count timer A |
527 |
ta_count: |
528 |
if (ta_cnt_phi2) |
529 |
if (!ta || !--ta) { // Decrement timer, underflow? |
530 |
if (ta_state != T_STOP) { |
531 |
ta_interrupt: |
532 |
ta = latcha; // Reload timer |
533 |
ta_irq_next_cycle = true; // Trigger interrupt in next cycle |
534 |
icr |= 1; // But set ICR bit now |
535 |
|
536 |
if (cra & 8) { // One-shot? |
537 |
cra &= 0xfe; // Yes, stop timer |
538 |
new_cra &= 0xfe; |
539 |
ta_state = T_LOAD_THEN_STOP; // Reload in next cycle |
540 |
} else |
541 |
ta_state = T_LOAD_THEN_COUNT; // No, delay one cycle (and reload) |
542 |
} |
543 |
ta_underflow = true; |
544 |
} |
545 |
|
546 |
// Delayed write to CRA? |
547 |
ta_idle: |
548 |
if (has_new_cra) { |
549 |
switch (ta_state) { |
550 |
case T_STOP: |
551 |
case T_LOAD_THEN_STOP: |
552 |
if (new_cra & 1) { // Timer started, wasn't running |
553 |
if (new_cra & 0x10) // Force load |
554 |
ta_state = T_LOAD_THEN_WAIT_THEN_COUNT; |
555 |
else // No force load |
556 |
ta_state = T_WAIT_THEN_COUNT; |
557 |
} else { // Timer stopped, was already stopped |
558 |
if (new_cra & 0x10) // Force load |
559 |
ta_state = T_LOAD_THEN_STOP; |
560 |
} |
561 |
break; |
562 |
case T_COUNT: |
563 |
if (new_cra & 1) { // Timer started, was already running |
564 |
if (new_cra & 0x10) // Force load |
565 |
ta_state = T_LOAD_THEN_WAIT_THEN_COUNT; |
566 |
} else { // Timer stopped, was running |
567 |
if (new_cra & 0x10) // Force load |
568 |
ta_state = T_LOAD_THEN_STOP; |
569 |
else // No force load |
570 |
ta_state = T_COUNT_THEN_STOP; |
571 |
} |
572 |
break; |
573 |
case T_LOAD_THEN_COUNT: |
574 |
case T_WAIT_THEN_COUNT: |
575 |
if (new_cra & 1) { |
576 |
if (new_cra & 8) { // One-shot? |
577 |
new_cra &= 0xfe; // Yes, stop timer |
578 |
ta_state = T_STOP; |
579 |
} else if (new_cra & 0x10) // Force load |
580 |
ta_state = T_LOAD_THEN_WAIT_THEN_COUNT; |
581 |
} else { |
582 |
ta_state = T_STOP; |
583 |
} |
584 |
break; |
585 |
} |
586 |
cra = new_cra & 0xef; |
587 |
has_new_cra = false; |
588 |
} |
589 |
|
590 |
// Timer B state machine |
591 |
switch (tb_state) { |
592 |
case T_WAIT_THEN_COUNT: |
593 |
tb_state = T_COUNT; // fall through |
594 |
case T_STOP: |
595 |
goto tb_idle; |
596 |
case T_LOAD_THEN_STOP: |
597 |
tb_state = T_STOP; |
598 |
tb = latchb; // Reload timer |
599 |
goto tb_idle; |
600 |
case T_LOAD_THEN_COUNT: |
601 |
tb_state = T_COUNT; |
602 |
tb = latchb; // Reload timer |
603 |
goto tb_idle; |
604 |
case T_LOAD_THEN_WAIT_THEN_COUNT: |
605 |
tb_state = T_WAIT_THEN_COUNT; |
606 |
if (tb == 1) |
607 |
goto tb_interrupt; // Interrupt if timer == 1 |
608 |
else { |
609 |
tb = latchb; // Reload timer |
610 |
goto tb_idle; |
611 |
} |
612 |
case T_COUNT: |
613 |
goto tb_count; |
614 |
case T_COUNT_THEN_STOP: |
615 |
tb_state = T_STOP; |
616 |
goto tb_count; |
617 |
} |
618 |
|
619 |
// Count timer B |
620 |
tb_count: |
621 |
if (tb_cnt_phi2 || (tb_cnt_ta && ta_underflow)) |
622 |
if (!tb || !--tb) { // Decrement timer, underflow? |
623 |
if (tb_state != T_STOP) { |
624 |
tb_interrupt: |
625 |
tb = latchb; // Reload timer |
626 |
tb_irq_next_cycle = true; // Trigger interrupt in next cycle |
627 |
icr |= 2; // But set ICR bit now |
628 |
|
629 |
if (crb & 8) { // One-shot? |
630 |
crb &= 0xfe; // Yes, stop timer |
631 |
new_crb &= 0xfe; |
632 |
tb_state = T_LOAD_THEN_STOP; // Reload in next cycle |
633 |
} else |
634 |
tb_state = T_LOAD_THEN_COUNT; // No, delay one cycle (and reload) |
635 |
} |
636 |
} |
637 |
|
638 |
// Delayed write to CRB? |
639 |
tb_idle: |
640 |
if (has_new_crb) { |
641 |
switch (tb_state) { |
642 |
case T_STOP: |
643 |
case T_LOAD_THEN_STOP: |
644 |
if (new_crb & 1) { // Timer started, wasn't running |
645 |
if (new_crb & 0x10) // Force load |
646 |
tb_state = T_LOAD_THEN_WAIT_THEN_COUNT; |
647 |
else // No force load |
648 |
tb_state = T_WAIT_THEN_COUNT; |
649 |
} else { // Timer stopped, was already stopped |
650 |
if (new_crb & 0x10) // Force load |
651 |
tb_state = T_LOAD_THEN_STOP; |
652 |
} |
653 |
break; |
654 |
case T_COUNT: |
655 |
if (new_crb & 1) { // Timer started, was already running |
656 |
if (new_crb & 0x10) // Force load |
657 |
tb_state = T_LOAD_THEN_WAIT_THEN_COUNT; |
658 |
} else { // Timer stopped, was running |
659 |
if (new_crb & 0x10) // Force load |
660 |
tb_state = T_LOAD_THEN_STOP; |
661 |
else // No force load |
662 |
tb_state = T_COUNT_THEN_STOP; |
663 |
} |
664 |
break; |
665 |
case T_LOAD_THEN_COUNT: |
666 |
case T_WAIT_THEN_COUNT: |
667 |
if (new_crb & 1) { |
668 |
if (new_crb & 8) { // One-shot? |
669 |
new_crb &= 0xfe; // Yes, stop timer |
670 |
tb_state = T_STOP; |
671 |
} else if (new_crb & 0x10) // Force load |
672 |
tb_state = T_LOAD_THEN_WAIT_THEN_COUNT; |
673 |
} else { |
674 |
tb_state = T_STOP; |
675 |
} |
676 |
break; |
677 |
} |
678 |
crb = new_crb & 0xef; |
679 |
has_new_crb = false; |
680 |
} |
681 |
} |
682 |
|
683 |
|
684 |
/* |
685 |
* Count CIA TOD clock (called during VBlank) |
686 |
*/ |
687 |
|
688 |
void MOS6526::CountTOD(void) |
689 |
{ |
690 |
uint8 lo, hi; |
691 |
|
692 |
// Decrement frequency divider |
693 |
if (tod_divider) |
694 |
tod_divider--; |
695 |
else { |
696 |
|
697 |
// Reload divider according to 50/60 Hz flag |
698 |
if (cra & 0x80) |
699 |
tod_divider = 4; |
700 |
else |
701 |
tod_divider = 5; |
702 |
|
703 |
// 1/10 seconds |
704 |
tod_10ths++; |
705 |
if (tod_10ths > 9) { |
706 |
tod_10ths = 0; |
707 |
|
708 |
// Seconds |
709 |
lo = (tod_sec & 0x0f) + 1; |
710 |
hi = tod_sec >> 4; |
711 |
if (lo > 9) { |
712 |
lo = 0; |
713 |
hi++; |
714 |
} |
715 |
if (hi > 5) { |
716 |
tod_sec = 0; |
717 |
|
718 |
// Minutes |
719 |
lo = (tod_min & 0x0f) + 1; |
720 |
hi = tod_min >> 4; |
721 |
if (lo > 9) { |
722 |
lo = 0; |
723 |
hi++; |
724 |
} |
725 |
if (hi > 5) { |
726 |
tod_min = 0; |
727 |
|
728 |
// Hours |
729 |
lo = (tod_hr & 0x0f) + 1; |
730 |
hi = (tod_hr >> 4) & 1; |
731 |
tod_hr &= 0x80; // Keep AM/PM flag |
732 |
if (lo > 9) { |
733 |
lo = 0; |
734 |
hi++; |
735 |
} |
736 |
tod_hr |= (hi << 4) | lo; |
737 |
if ((tod_hr & 0x1f) > 0x11) |
738 |
tod_hr = tod_hr & 0x80 ^ 0x80; |
739 |
} else |
740 |
tod_min = (hi << 4) | lo; |
741 |
} else |
742 |
tod_sec = (hi << 4) | lo; |
743 |
} |
744 |
|
745 |
// Alarm time reached? Trigger interrupt if enabled |
746 |
if (tod_10ths == alm_10ths && tod_sec == alm_sec && |
747 |
tod_min == alm_min && tod_hr == alm_hr) |
748 |
TriggerInterrupt(4); |
749 |
} |
750 |
} |
751 |
|
752 |
|
753 |
/* |
754 |
* Trigger IRQ (CIA 1) |
755 |
*/ |
756 |
|
757 |
void MOS6526_1::TriggerInterrupt(int bit) |
758 |
{ |
759 |
icr |= bit; |
760 |
if (int_mask & bit) { |
761 |
icr |= 0x80; |
762 |
the_cpu->TriggerCIAIRQ(); |
763 |
} |
764 |
} |
765 |
|
766 |
|
767 |
/* |
768 |
* Trigger NMI (CIA 2) |
769 |
*/ |
770 |
|
771 |
void MOS6526_2::TriggerInterrupt(int bit) |
772 |
{ |
773 |
icr |= bit; |
774 |
if (int_mask & bit) { |
775 |
icr |= 0x80; |
776 |
the_cpu->TriggerNMI(); |
777 |
} |
778 |
} |