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root/cebix/Frodo4/Src/CPU_common.cpp
Revision: 1.4
Committed: 2005-06-27T19:55:48Z (17 years, 5 months ago) by cebix
Branch: MAIN
CVS Tags: VERSION_4_2, HEAD
Changes since 1.3: +1 -1 lines
Log Message:
updated copyright dates

File Contents

# Content
1 /*
2 * CPU_common.cpp - Definitions common to 6502/6510 SC emulation
3 *
4 * Frodo (C) 1994-1997,2002-2005 Christian Bauer
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21 #include "sysdeps.h"
22
23 #include "CPU_common.h"
24
25
26 // Addressing mode for each opcode (first part of execution) (Frodo SC)
27 const uint8 ModeTab[256] = {
28 O_BRK, A_INDX, 1, M_INDX, A_ZERO, A_ZERO, M_ZERO, M_ZERO, // 00
29 O_PHP, O_ORA_I,O_ASL_A,O_ANC_I,A_ABS, A_ABS, M_ABS, M_ABS,
30 O_BPL, AE_INDY,1, M_INDY, A_ZEROX,A_ZEROX,M_ZEROX,M_ZEROX,// 10
31 O_CLC, AE_ABSY,O_NOP, M_ABSY, AE_ABSX,AE_ABSX,M_ABSX, M_ABSX,
32 O_JSR, A_INDX, 1, M_INDX, A_ZERO, A_ZERO, M_ZERO, M_ZERO, // 20
33 O_PLP, O_AND_I,O_ROL_A,O_ANC_I,A_ABS, A_ABS, M_ABS, M_ABS,
34 O_BMI, AE_INDY,1, M_INDY, A_ZEROX,A_ZEROX,M_ZEROX,M_ZEROX,// 30
35 O_SEC, AE_ABSY,O_NOP, M_ABSY, AE_ABSX,AE_ABSX,M_ABSX, M_ABSX,
36 O_RTI, A_INDX, 1, M_INDX, A_ZERO, A_ZERO, M_ZERO, M_ZERO, // 40
37 O_PHA, O_EOR_I,O_LSR_A,O_ASR_I,O_JMP, A_ABS, M_ABS, M_ABS,
38 O_BVC, AE_INDY,1, M_INDY, A_ZEROX,A_ZEROX,M_ZEROX,M_ZEROX,// 50
39 O_CLI, AE_ABSY,O_NOP, M_ABSY, AE_ABSX,AE_ABSX,M_ABSX, M_ABSX,
40 O_RTS, A_INDX, 1, M_INDX, A_ZERO, A_ZERO, M_ZERO, M_ZERO, // 60
41 O_PLA, O_ADC_I,O_ROR_A,O_ARR_I,A_ABS, A_ABS, M_ABS, M_ABS,
42 O_BVS, AE_INDY,1, M_INDY, A_ZEROX,A_ZEROX,M_ZEROX,M_ZEROX,// 70
43 O_SEI, AE_ABSY,O_NOP, M_ABSY, AE_ABSX,AE_ABSX,M_ABSX, M_ABSX,
44 O_NOP_I,A_INDX, O_NOP_I,A_INDX, A_ZERO, A_ZERO, A_ZERO, A_ZERO, // 80
45 O_DEY, O_NOP_I,O_TXA, O_ANE_I,A_ABS, A_ABS, A_ABS, A_ABS,
46 O_BCC, A_INDY, 1, A_INDY, A_ZEROX,A_ZEROX,A_ZEROY,A_ZEROY,// 90
47 O_TYA, A_ABSY, O_TXS, A_ABSY, A_ABSX, A_ABSX, A_ABSY, A_ABSY,
48 O_LDY_I,A_INDX, O_LDX_I,A_INDX, A_ZERO, A_ZERO, A_ZERO, A_ZERO, // a0
49 O_TAY, O_LDA_I,O_TAX, O_LXA_I,A_ABS, A_ABS, A_ABS, A_ABS,
50 O_BCS, AE_INDY,1, AE_INDY,A_ZEROX,A_ZEROX,A_ZEROY,A_ZEROY,// b0
51 O_CLV, AE_ABSY,O_TSX, AE_ABSY,AE_ABSX,AE_ABSX,AE_ABSY,AE_ABSY,
52 O_CPY_I,A_INDX, O_NOP_I,M_INDX, A_ZERO, A_ZERO, M_ZERO, M_ZERO, // c0
53 O_INY, O_CMP_I,O_DEX, O_SBX_I,A_ABS, A_ABS, M_ABS, M_ABS,
54 O_BNE, AE_INDY,1, M_INDY, A_ZEROX,A_ZEROX,M_ZEROX,M_ZEROX,// d0
55 O_CLD, AE_ABSY,O_NOP, M_ABSY, AE_ABSX,AE_ABSX,M_ABSX, M_ABSX,
56 O_CPX_I,A_INDX, O_NOP_I,M_INDX, A_ZERO, A_ZERO, M_ZERO, M_ZERO, // e0
57 O_INX, O_SBC_I,O_NOP, O_SBC_I,A_ABS, A_ABS, M_ABS, M_ABS,
58 O_BEQ, AE_INDY,O_EXT, M_INDY, A_ZEROX,A_ZEROX,M_ZEROX,M_ZEROX,// f0
59 O_SED, AE_ABSY,O_NOP, M_ABSY, AE_ABSX,AE_ABSX,M_ABSX, M_ABSX
60 };
61
62
63 // Operation for each opcode (second part of execution) (Frodo SC)
64 const uint8 OpTab[256] = {
65 1, O_ORA, 1, O_SLO, O_NOP_A,O_ORA, O_ASL, O_SLO, // 00
66 1, 1, 1, 1, O_NOP_A,O_ORA, O_ASL, O_SLO,
67 1, O_ORA, 1, O_SLO, O_NOP_A,O_ORA, O_ASL, O_SLO, // 10
68 1, O_ORA, 1, O_SLO, O_NOP_A,O_ORA, O_ASL, O_SLO,
69 1, O_AND, 1, O_RLA, O_BIT, O_AND, O_ROL, O_RLA, // 20
70 1, 1, 1, 1, O_BIT, O_AND, O_ROL, O_RLA,
71 1, O_AND, 1, O_RLA, O_NOP_A,O_AND, O_ROL, O_RLA, // 30
72 1, O_AND, 1, O_RLA, O_NOP_A,O_AND, O_ROL, O_RLA,
73 1, O_EOR, 1, O_SRE, O_NOP_A,O_EOR, O_LSR, O_SRE, // 40
74 1, 1, 1, 1, 1, O_EOR, O_LSR, O_SRE,
75 1, O_EOR, 1, O_SRE, O_NOP_A,O_EOR, O_LSR, O_SRE, // 50
76 1, O_EOR, 1, O_SRE, O_NOP_A,O_EOR, O_LSR, O_SRE,
77 1, O_ADC, 1, O_RRA, O_NOP_A,O_ADC, O_ROR, O_RRA, // 60
78 1, 1, 1, 1, O_JMP_I,O_ADC, O_ROR, O_RRA,
79 1, O_ADC, 1, O_RRA, O_NOP_A,O_ADC, O_ROR, O_RRA, // 70
80 1, O_ADC, 1, O_RRA, O_NOP_A,O_ADC, O_ROR, O_RRA,
81 1, O_STA, 1, O_SAX, O_STY, O_STA, O_STX, O_SAX, // 80
82 1, 1, 1, 1, O_STY, O_STA, O_STX, O_SAX,
83 1, O_STA, 1, O_SHA, O_STY, O_STA, O_STX, O_SAX, // 90
84 1, O_STA, 1, O_SHS, O_SHY, O_STA, O_SHX, O_SHA,
85 1, O_LDA, 1, O_LAX, O_LDY, O_LDA, O_LDX, O_LAX, // a0
86 1, 1, 1, 1, O_LDY, O_LDA, O_LDX, O_LAX,
87 1, O_LDA, 1, O_LAX, O_LDY, O_LDA, O_LDX, O_LAX, // b0
88 1, O_LDA, 1, O_LAS, O_LDY, O_LDA, O_LDX, O_LAX,
89 1, O_CMP, 1, O_DCP, O_CPY, O_CMP, O_DEC, O_DCP, // c0
90 1, 1, 1, 1, O_CPY, O_CMP, O_DEC, O_DCP,
91 1, O_CMP, 1, O_DCP, O_NOP_A,O_CMP, O_DEC, O_DCP, // d0
92 1, O_CMP, 1, O_DCP, O_NOP_A,O_CMP, O_DEC, O_DCP,
93 1, O_SBC, 1, O_ISB, O_CPX, O_SBC, O_INC, O_ISB, // e0
94 1, 1, 1, 1, O_CPX, O_SBC, O_INC, O_ISB,
95 1, O_SBC, 1, O_ISB, O_NOP_A,O_SBC, O_INC, O_ISB, // f0
96 1, O_SBC, 1, O_ISB, O_NOP_A,O_SBC, O_INC, O_ISB
97 };