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/* |
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* CPU_common.h - Definitions common to 6502/6510 SC emulation |
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* |
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* Frodo (C) 1994-1997,2002 Christian Bauer |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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*/ |
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|
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#ifndef _CPU_COMMON_H_ |
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#define _CPU_COMMON_H_ |
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|
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|
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// States for addressing modes/operations (Frodo SC) |
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enum { |
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// Read effective address, no extra cycles |
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A_ZERO=0x18, |
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A_ZEROX, A_ZEROX1, |
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A_ZEROY, A_ZEROY1, |
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A_ABS, A_ABS1, |
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A_ABSX, A_ABSX1, A_ABSX2, A_ABSX3, |
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A_ABSY, A_ABSY1, A_ABSY2, A_ABSY3, |
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A_INDX, A_INDX1, A_INDX2, A_INDX3, |
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A_INDY, A_INDY1, A_INDY2, A_INDY3, A_INDY4, |
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|
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// Read effective address, extra cycle on page crossing |
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AE_ABSX, AE_ABSX1, AE_ABSX2, |
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AE_ABSY, AE_ABSY1, AE_ABSY2, |
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AE_INDY, AE_INDY1, AE_INDY2, AE_INDY3, |
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|
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// Read operand and write it back (for RMW instructions), no extra cycles |
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M_ZERO, |
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M_ZEROX, M_ZEROX1, |
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M_ZEROY, M_ZEROY1, |
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M_ABS, M_ABS1, |
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M_ABSX, M_ABSX1, M_ABSX2, M_ABSX3, |
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M_ABSY, M_ABSY1, M_ABSY2, M_ABSY3, |
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M_INDX, M_INDX1, M_INDX2, M_INDX3, |
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M_INDY, M_INDY1, M_INDY2, M_INDY3, M_INDY4, |
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RMW_DO_IT, RMW_DO_IT1, |
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|
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// Operations (_I = Immediate/Indirect, _A = Accumulator) |
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O_LDA, O_LDA_I, O_LDX, O_LDX_I, O_LDY, O_LDY_I, |
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O_STA, O_STX, O_STY, |
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O_TAX, O_TXA, O_TAY, O_TYA, O_TSX, O_TXS, |
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O_ADC, O_ADC_I, O_SBC, O_SBC_I, |
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O_INX, O_DEX, O_INY, O_DEY, O_INC, O_DEC, |
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O_AND, O_AND_I, O_ORA, O_ORA_I, O_EOR, O_EOR_I, |
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O_CMP, O_CMP_I, O_CPX, O_CPX_I, O_CPY, O_CPY_I, |
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O_BIT, |
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O_ASL, O_ASL_A, O_LSR, O_LSR_A, O_ROL, O_ROL_A, O_ROR, O_ROR_A, |
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O_PHA, O_PHA1, O_PLA, O_PLA1, O_PLA2, |
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O_PHP, O_PHP1, O_PLP, O_PLP1, O_PLP2, |
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O_JMP, O_JMP1, O_JMP_I, O_JMP_I1, |
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O_JSR, O_JSR1, O_JSR2, O_JSR3, O_JSR4, |
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O_RTS, O_RTS1, O_RTS2, O_RTS3, O_RTS4, |
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O_RTI, O_RTI1, O_RTI2, O_RTI3, O_RTI4, |
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O_BRK, O_BRK1, O_BRK2, O_BRK3, O_BRK4, O_BRK5, O_BRK5NMI, |
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O_BCS, O_BCC, O_BEQ, O_BNE, O_BVS, O_BVC, O_BMI, O_BPL, |
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O_BRANCH_NP, O_BRANCH_BP, O_BRANCH_BP1, O_BRANCH_FP, O_BRANCH_FP1, |
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O_SEC, O_CLC, O_SED, O_CLD, O_SEI, O_CLI, O_CLV, |
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O_NOP, |
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|
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O_NOP_I, O_NOP_A, |
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O_LAX, O_SAX, |
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O_SLO, O_RLA, O_SRE, O_RRA, O_DCP, O_ISB, |
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O_ANC_I, O_ASR_I, O_ARR_I, O_ANE_I, O_LXA_I, O_SBX_I, |
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O_LAS, O_SHS, O_SHY, O_SHX, O_SHA, |
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O_EXT |
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}; |
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|
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|
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// Addressing mode for each opcode (first part of execution) (Frodo SC) |
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extern const uint8 ModeTab[256]; |
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|
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// Operation for each opcode (second part of execution) (Frodo SC) |
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extern const uint8 OpTab[256]; |
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|
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#endif |
