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root/cebix/Frodo4/Src/CPU_common.h
Revision: 1.4
Committed: 2005-06-27T19:55:48Z (17 years, 5 months ago) by cebix
Content type: text/plain
Branch: MAIN
CVS Tags: VERSION_4_2, HEAD
Changes since 1.3: +1 -1 lines
Log Message:
updated copyright dates

File Contents

# Content
1 /*
2 * CPU_common.h - Definitions common to 6502/6510 SC emulation
3 *
4 * Frodo (C) 1994-1997,2002-2005 Christian Bauer
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21 #ifndef _CPU_COMMON_H_
22 #define _CPU_COMMON_H_
23
24
25 // States for addressing modes/operations (Frodo SC)
26 enum {
27 // Read effective address, no extra cycles
28 A_ZERO=0x18,
29 A_ZEROX, A_ZEROX1,
30 A_ZEROY, A_ZEROY1,
31 A_ABS, A_ABS1,
32 A_ABSX, A_ABSX1, A_ABSX2, A_ABSX3,
33 A_ABSY, A_ABSY1, A_ABSY2, A_ABSY3,
34 A_INDX, A_INDX1, A_INDX2, A_INDX3,
35 A_INDY, A_INDY1, A_INDY2, A_INDY3, A_INDY4,
36
37 // Read effective address, extra cycle on page crossing
38 AE_ABSX, AE_ABSX1, AE_ABSX2,
39 AE_ABSY, AE_ABSY1, AE_ABSY2,
40 AE_INDY, AE_INDY1, AE_INDY2, AE_INDY3,
41
42 // Read operand and write it back (for RMW instructions), no extra cycles
43 M_ZERO,
44 M_ZEROX, M_ZEROX1,
45 M_ZEROY, M_ZEROY1,
46 M_ABS, M_ABS1,
47 M_ABSX, M_ABSX1, M_ABSX2, M_ABSX3,
48 M_ABSY, M_ABSY1, M_ABSY2, M_ABSY3,
49 M_INDX, M_INDX1, M_INDX2, M_INDX3,
50 M_INDY, M_INDY1, M_INDY2, M_INDY3, M_INDY4,
51 RMW_DO_IT, RMW_DO_IT1,
52
53 // Operations (_I = Immediate/Indirect, _A = Accumulator)
54 O_LDA, O_LDA_I, O_LDX, O_LDX_I, O_LDY, O_LDY_I,
55 O_STA, O_STX, O_STY,
56 O_TAX, O_TXA, O_TAY, O_TYA, O_TSX, O_TXS,
57 O_ADC, O_ADC_I, O_SBC, O_SBC_I,
58 O_INX, O_DEX, O_INY, O_DEY, O_INC, O_DEC,
59 O_AND, O_AND_I, O_ORA, O_ORA_I, O_EOR, O_EOR_I,
60 O_CMP, O_CMP_I, O_CPX, O_CPX_I, O_CPY, O_CPY_I,
61 O_BIT,
62 O_ASL, O_ASL_A, O_LSR, O_LSR_A, O_ROL, O_ROL_A, O_ROR, O_ROR_A,
63 O_PHA, O_PHA1, O_PLA, O_PLA1, O_PLA2,
64 O_PHP, O_PHP1, O_PLP, O_PLP1, O_PLP2,
65 O_JMP, O_JMP1, O_JMP_I, O_JMP_I1,
66 O_JSR, O_JSR1, O_JSR2, O_JSR3, O_JSR4,
67 O_RTS, O_RTS1, O_RTS2, O_RTS3, O_RTS4,
68 O_RTI, O_RTI1, O_RTI2, O_RTI3, O_RTI4,
69 O_BRK, O_BRK1, O_BRK2, O_BRK3, O_BRK4, O_BRK5, O_BRK5NMI,
70 O_BCS, O_BCC, O_BEQ, O_BNE, O_BVS, O_BVC, O_BMI, O_BPL,
71 O_BRANCH_NP, O_BRANCH_BP, O_BRANCH_BP1, O_BRANCH_FP, O_BRANCH_FP1,
72 O_SEC, O_CLC, O_SED, O_CLD, O_SEI, O_CLI, O_CLV,
73 O_NOP,
74
75 O_NOP_I, O_NOP_A,
76 O_LAX, O_SAX,
77 O_SLO, O_RLA, O_SRE, O_RRA, O_DCP, O_ISB,
78 O_ANC_I, O_ASR_I, O_ARR_I, O_ANE_I, O_LXA_I, O_SBX_I,
79 O_LAS, O_SHS, O_SHY, O_SHX, O_SHA,
80 O_EXT
81 };
82
83
84 // Addressing mode for each opcode (first part of execution) (Frodo SC)
85 extern const uint8 ModeTab[256];
86
87 // Operation for each opcode (second part of execution) (Frodo SC)
88 extern const uint8 OpTab[256];
89
90 #endif