| 91 |
|
case 0: |
| 92 |
|
read_to(pc++, op); |
| 93 |
|
state = ModeTab[op]; |
| 94 |
+ |
opflags = 0; |
| 95 |
|
break; |
| 96 |
|
|
| 97 |
|
|
| 739 |
|
read_idle(sp++ | 0x100); |
| 740 |
|
state = O_PLP2; |
| 741 |
|
break; |
| 742 |
< |
case O_PLP2: |
| 742 |
> |
case O_PLP2: { |
| 743 |
> |
bool old_i_flag = i_flag; |
| 744 |
|
pop_flags(); |
| 745 |
+ |
if (!old_i_flag && i_flag) { |
| 746 |
+ |
opflags |= OPFLAG_IRQ_DISABLED; |
| 747 |
+ |
} else if (old_i_flag && !i_flag) { |
| 748 |
+ |
opflags |= OPFLAG_IRQ_ENABLED; |
| 749 |
+ |
} |
| 750 |
|
Last; |
| 751 |
+ |
} |
| 752 |
|
|
| 753 |
|
|
| 754 |
|
// Jump/branch group |
| 850 |
|
push_flags(true); |
| 851 |
|
i_flag = true; |
| 852 |
|
#ifndef IS_CPU_1541 |
| 853 |
< |
if (interrupt.intr[INT_NMI]) { // BRK interrupted by NMI? |
| 853 |
> |
if (interrupt.intr[INT_NMI]) { // BRK interrupted by NMI? |
| 854 |
|
interrupt.intr[INT_NMI] = false; // Simulate an edge-triggered input |
| 855 |
|
state = 0x0015; // Jump to NMI sequence |
| 856 |
|
break; |
| 859 |
|
state = O_BRK4; |
| 860 |
|
break; |
| 861 |
|
case O_BRK4: |
| 854 |
– |
#ifndef IS_CPU_1541 |
| 855 |
– |
first_nmi_cycle++; // Delay NMI |
| 856 |
– |
#endif |
| 862 |
|
read_to(0xfffe, pc); |
| 863 |
|
state = O_BRK5; |
| 864 |
|
break; |
| 900 |
|
Branch(!(n_flag & 0x80)); |
| 901 |
|
|
| 902 |
|
case O_BRANCH_NP: // No page crossed |
| 903 |
< |
first_irq_cycle++; // Delay IRQ |
| 899 |
< |
#ifndef IS_CPU_1541 |
| 900 |
< |
first_nmi_cycle++; // Delay NMI |
| 901 |
< |
#endif |
| 903 |
> |
opflags |= OPFLAG_INT_DELAYED; |
| 904 |
|
read_idle(pc); |
| 905 |
|
pc = ar; |
| 906 |
|
Last; |
| 945 |
|
|
| 946 |
|
case O_SEI: |
| 947 |
|
read_idle(pc); |
| 948 |
+ |
if (!i_flag) |
| 949 |
+ |
opflags |= OPFLAG_IRQ_DISABLED; |
| 950 |
|
i_flag = true; |
| 951 |
|
Last; |
| 952 |
|
|
| 953 |
|
case O_CLI: |
| 954 |
|
read_idle(pc); |
| 955 |
+ |
if (i_flag) |
| 956 |
+ |
opflags |= OPFLAG_IRQ_ENABLED; |
| 957 |
|
i_flag = false; |
| 958 |
|
Last; |
| 959 |
|
|
