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cebix |
1.1 |
/* |
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* rom_patches.cpp - ROM patches |
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* |
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* SheepShaver (C) 1997-2002 Christian Bauer and Marc Hellwig |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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*/ |
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/* |
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* TODO: |
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* IRQ_NEST must be handled atomically |
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* Don't use r1 in extra routines |
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*/ |
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#include <string.h> |
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#include "sysdeps.h" |
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#include "rom_patches.h" |
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#include "main.h" |
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#include "prefs.h" |
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#include "cpu_emulation.h" |
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#include "emul_op.h" |
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#include "xlowmem.h" |
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#include "sony.h" |
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#include "disk.h" |
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#include "cdrom.h" |
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#include "audio.h" |
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#include "audio_defs.h" |
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#include "serial.h" |
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#include "macos_util.h" |
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#define DEBUG 0 |
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#include "debug.h" |
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47 |
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// 68k breakpoint address |
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//#define M68K_BREAK_POINT 0x29e0 // BootMe |
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//#define M68K_BREAK_POINT 0x2a1e // Boot block code returned |
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//#define M68K_BREAK_POINT 0x3150 // CritError |
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//#define M68K_BREAK_POINT 0x187ce // Unimplemented trap |
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// PowerPC breakpoint address |
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//#define POWERPC_BREAK_POINT 0x36e6c0 // 68k emulator start |
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#define DISABLE_SCSI 1 |
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// Other ROM addresses |
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const uint32 CHECK_LOAD_PATCH_SPACE = 0x2f7f00; |
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const uint32 PUT_SCRAP_PATCH_SPACE = 0x2f7f80; |
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const uint32 GET_SCRAP_PATCH_SPACE = 0x2f7fc0; |
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const uint32 ADDR_MAP_PATCH_SPACE = 0x2f8000; |
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// Global variables |
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int ROMType; // ROM type |
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static uint32 sony_offset; // Offset of .Sony driver resource |
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// Prototypes |
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static bool patch_nanokernel_boot(void); |
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static bool patch_68k_emul(void); |
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static bool patch_nanokernel(void); |
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static bool patch_68k(void); |
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gbeauche |
1.2 |
// Decode LZSS data |
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static void decode_lzss(const uint8 *src, uint8 *dest, int size) |
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{ |
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char dict[0x1000]; |
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int run_mask = 0, dict_idx = 0xfee; |
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for (;;) { |
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if (run_mask < 0x100) { |
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// Start new run |
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if (--size < 0) |
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break; |
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run_mask = *src++ | 0xff00; |
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} |
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bool bit = run_mask & 1; |
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run_mask >>= 1; |
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if (bit) { |
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// Verbatim copy |
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if (--size < 0) |
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break; |
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int c = *src++; |
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dict[dict_idx++] = c; |
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*dest++ = c; |
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dict_idx &= 0xfff; |
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} else { |
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// Copy from dictionary |
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if (--size < 0) |
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break; |
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int idx = *src++; |
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if (--size < 0) |
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break; |
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int cnt = *src++; |
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idx |= (cnt << 4) & 0xf00; |
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cnt = (cnt & 0x0f) + 3; |
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while (cnt--) { |
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char c = dict[idx++]; |
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dict[dict_idx++] = c; |
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*dest++ = c; |
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idx &= 0xfff; |
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dict_idx &= 0xfff; |
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} |
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} |
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} |
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} |
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// Decode parcels of ROM image (MacOS 9.X and even earlier) |
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void decode_parcels(const uint8 *src, uint8 *dest, int size) |
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{ |
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uint32 parcel_offset = 0x14; |
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D(bug("Offset Type Name\n")); |
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while (parcel_offset != 0) { |
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const uint32 *parcel_data = (uint32 *)(src + parcel_offset); |
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gbeauche |
1.3 |
uint32 next_offset = ntohl(parcel_data[0]); |
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gbeauche |
1.2 |
uint32 parcel_type = ntohl(parcel_data[1]); |
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D(bug("%08x %c%c%c%c %s\n", parcel_offset, |
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(parcel_type >> 24) & 0xff, (parcel_type >> 16) & 0xff, |
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(parcel_type >> 8) & 0xff, parcel_type & 0xff, &parcel_data[6])); |
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if (parcel_type == FOURCC('r','o','m',' ')) { |
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uint32 lzss_offset = ntohl(parcel_data[2]); |
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uint32 lzss_size = ((uint32)src + parcel_offset) - ((uint32)parcel_data + lzss_offset); |
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decode_lzss((uint8 *)parcel_data + lzss_offset, dest, lzss_size); |
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} |
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gbeauche |
1.3 |
parcel_offset = next_offset; |
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gbeauche |
1.2 |
} |
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} |
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/* |
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* Decode ROM image, 4 MB plain images or NewWorld images |
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*/ |
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bool DecodeROM(uint8 *data, uint32 size) |
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{ |
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if (size == ROM_SIZE) { |
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// Plain ROM image |
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memcpy((void *)ROM_BASE, data, ROM_SIZE); |
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return true; |
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} |
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else if (strncmp((char *)data, "<CHRP-BOOT>", 11) == 0) { |
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// CHRP compressed ROM image |
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uint32 image_offset, image_size; |
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bool decode_info_ok = false; |
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char *s = strstr((char *)data, "constant lzss-offset"); |
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if (s != NULL) { |
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// Probably a plain LZSS compressed ROM image |
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if (sscanf(s - 7, "%06x", &image_offset) == 1) { |
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s = strstr((char *)data, "constant lzss-size"); |
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if (s != NULL && (sscanf(s - 7, "%06x", &image_size) == 1)) |
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decode_info_ok = true; |
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} |
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} |
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else { |
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// Probably a MacOS 9.2.x ROM image |
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s = strstr((char *)data, "constant parcels-offset"); |
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if (s != NULL) { |
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if (sscanf(s - 7, "%06x", &image_offset) == 1) { |
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s = strstr((char *)data, "constant parcels-size"); |
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if (s != NULL && (sscanf(s - 7, "%06x", &image_size) == 1)) |
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decode_info_ok = true; |
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} |
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} |
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} |
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// No valid information to decode the ROM found? |
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if (!decode_info_ok) |
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return false; |
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// Check signature, this could be a parcels-based ROM image |
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uint32 rom_signature = ntohl(*(uint32 *)(data + image_offset)); |
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if (rom_signature == FOURCC('p','r','c','l')) { |
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D(bug("Offset of parcels data: %08x\n", image_offset)); |
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D(bug("Size of parcels data: %08x\n", image_size)); |
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decode_parcels(data + image_offset, (uint8 *)ROM_BASE, image_size); |
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} |
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else { |
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D(bug("Offset of compressed data: %08x\n", image_offset)); |
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D(bug("Size of compressed data: %08x\n", image_size)); |
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decode_lzss(data + image_offset, (uint8 *)ROM_BASE, image_size); |
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} |
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return true; |
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} |
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return false; |
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} |
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cebix |
1.1 |
/* |
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* Search ROM for byte string, return ROM offset (or 0) |
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*/ |
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static uint32 find_rom_data(uint32 start, uint32 end, const uint8 *data, uint32 data_len) |
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{ |
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uint32 ofs = start; |
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while (ofs < end) { |
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if (!memcmp((void *)(ROM_BASE + ofs), data, data_len)) |
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return ofs; |
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ofs++; |
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} |
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return 0; |
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} |
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/* |
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* Search ROM resource by type/ID, return ROM offset of resource data |
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*/ |
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static uint32 rsrc_ptr = 0; |
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// id = 4711 means "find any ID" |
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static uint32 find_rom_resource(uint32 s_type, int16 s_id = 4711, bool cont = false) |
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{ |
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uint32 *lp = (uint32 *)(ROM_BASE + 0x1a); |
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uint32 x = ntohl(*lp); |
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uint8 *bp = (uint8 *)(ROM_BASE + x + 5); |
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uint32 header_size = *bp; |
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if (!cont) |
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rsrc_ptr = x; |
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else if (rsrc_ptr == 0) |
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return 0; |
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for (;;) { |
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lp = (uint32 *)(ROM_BASE + rsrc_ptr); |
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rsrc_ptr = ntohl(*lp); |
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if (rsrc_ptr == 0) |
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break; |
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rsrc_ptr += header_size; |
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lp = (uint32 *)(ROM_BASE + rsrc_ptr + 4); |
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uint32 data = ntohl(*lp); lp++; |
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uint32 type = ntohl(*lp); lp++; |
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int16 id = ntohs(*(int16 *)lp); |
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if (type == s_type && (id == s_id || s_id == 4711)) |
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return data; |
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} |
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return 0; |
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} |
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/* |
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* Search offset of A-Trap routine in ROM |
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*/ |
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static uint32 find_rom_trap(uint16 trap) |
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{ |
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uint32 *lp = (uint32 *)(ROM_BASE + 0x22); |
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lp = (uint32 *)(ROM_BASE + ntohl(*lp)); |
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if (trap > 0xa800) |
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return ntohl(lp[trap & 0x3ff]); |
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else |
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return ntohl(lp[(trap & 0xff) + 0x400]); |
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} |
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/* |
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* List of audio sifters installed in ROM and System file |
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*/ |
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struct sift_entry { |
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uint32 type; |
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int16 id; |
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}; |
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static sift_entry sifter_list[32]; |
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static int num_sifters; |
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void AddSifter(uint32 type, int16 id) |
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{ |
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if (FindSifter(type, id)) |
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return; |
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D(bug(" adding sifter type %c%c%c%c (%08x), id %d\n", type >> 24, (type >> 16) & 0xff, (type >> 8) & 0xff, type & 0xff, type, id)); |
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sifter_list[num_sifters].type = type; |
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sifter_list[num_sifters].id = id; |
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num_sifters++; |
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} |
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bool FindSifter(uint32 type, int16 id) |
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{ |
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for (int i=0; i<num_sifters; i++) { |
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if (sifter_list[i].type == type && sifter_list[i].id == id) |
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return true; |
297 |
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} |
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return false; |
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} |
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302 |
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/* |
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* Driver stubs |
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*/ |
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static const uint8 sony_driver[] = { // Replacement for .Sony driver |
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// Driver header |
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SonyDriverFlags >> 8, SonyDriverFlags & 0xff, 0, 0, 0, 0, 0, 0, |
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0x00, 0x18, // Open() offset |
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0x00, 0x1c, // Prime() offset |
311 |
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0x00, 0x20, // Control() offset |
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0x00, 0x2c, // Status() offset |
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0x00, 0x52, // Close() offset |
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0x05, 0x2e, 0x53, 0x6f, 0x6e, 0x79, // ".Sony" |
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316 |
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// Open() |
317 |
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M68K_EMUL_OP_SONY_OPEN >> 8, M68K_EMUL_OP_SONY_OPEN & 0xff, |
318 |
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0x4e, 0x75, // rts |
319 |
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320 |
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// Prime() |
321 |
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M68K_EMUL_OP_SONY_PRIME >> 8, M68K_EMUL_OP_SONY_PRIME & 0xff, |
322 |
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0x60, 0x0e, // bra IOReturn |
323 |
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324 |
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// Control() |
325 |
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M68K_EMUL_OP_SONY_CONTROL >> 8, M68K_EMUL_OP_SONY_CONTROL & 0xff, |
326 |
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0x0c, 0x68, 0x00, 0x01, 0x00, 0x1a, // cmp.w #1,$1a(a0) |
327 |
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0x66, 0x04, // bne IOReturn |
328 |
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0x4e, 0x75, // rts |
329 |
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330 |
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// Status() |
331 |
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M68K_EMUL_OP_SONY_STATUS >> 8, M68K_EMUL_OP_SONY_STATUS & 0xff, |
332 |
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333 |
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// IOReturn |
334 |
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0x32, 0x28, 0x00, 0x06, // move.w 6(a0),d1 |
335 |
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0x08, 0x01, 0x00, 0x09, // btst #9,d1 |
336 |
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0x67, 0x0c, // beq 1 |
337 |
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0x4a, 0x40, // tst.w d0 |
338 |
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0x6f, 0x02, // ble 2 |
339 |
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0x42, 0x40, // clr.w d0 |
340 |
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0x31, 0x40, 0x00, 0x10, //2 move.w d0,$10(a0) |
341 |
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0x4e, 0x75, // rts |
342 |
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0x4a, 0x40, //1 tst.w d0 |
343 |
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0x6f, 0x04, // ble 3 |
344 |
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0x42, 0x40, // clr.w d0 |
345 |
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0x4e, 0x75, // rts |
346 |
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0x2f, 0x38, 0x08, 0xfc, //3 move.l $8fc,-(sp) |
347 |
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0x4e, 0x75, // rts |
348 |
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349 |
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// Close() |
350 |
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0x70, 0xe8, // moveq #-24,d0 |
351 |
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0x4e, 0x75 // rts |
352 |
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}; |
353 |
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354 |
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static const uint8 disk_driver[] = { // Generic disk driver |
355 |
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// Driver header |
356 |
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DiskDriverFlags >> 8, DiskDriverFlags & 0xff, 0, 0, 0, 0, 0, 0, |
357 |
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0x00, 0x18, // Open() offset |
358 |
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0x00, 0x1c, // Prime() offset |
359 |
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0x00, 0x20, // Control() offset |
360 |
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0x00, 0x2c, // Status() offset |
361 |
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0x00, 0x52, // Close() offset |
362 |
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0x05, 0x2e, 0x44, 0x69, 0x73, 0x6b, // ".Disk" |
363 |
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364 |
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// Open() |
365 |
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M68K_EMUL_OP_DISK_OPEN >> 8, M68K_EMUL_OP_DISK_OPEN & 0xff, |
366 |
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0x4e, 0x75, // rts |
367 |
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368 |
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// Prime() |
369 |
|
|
M68K_EMUL_OP_DISK_PRIME >> 8, M68K_EMUL_OP_DISK_PRIME & 0xff, |
370 |
|
|
0x60, 0x0e, // bra IOReturn |
371 |
|
|
|
372 |
|
|
// Control() |
373 |
|
|
M68K_EMUL_OP_DISK_CONTROL >> 8, M68K_EMUL_OP_DISK_CONTROL & 0xff, |
374 |
|
|
0x0c, 0x68, 0x00, 0x01, 0x00, 0x1a, // cmp.w #1,$1a(a0) |
375 |
|
|
0x66, 0x04, // bne IOReturn |
376 |
|
|
0x4e, 0x75, // rts |
377 |
|
|
|
378 |
|
|
// Status() |
379 |
|
|
M68K_EMUL_OP_DISK_STATUS >> 8, M68K_EMUL_OP_DISK_STATUS & 0xff, |
380 |
|
|
|
381 |
|
|
// IOReturn |
382 |
|
|
0x32, 0x28, 0x00, 0x06, // move.w 6(a0),d1 |
383 |
|
|
0x08, 0x01, 0x00, 0x09, // btst #9,d1 |
384 |
|
|
0x67, 0x0c, // beq 1 |
385 |
|
|
0x4a, 0x40, // tst.w d0 |
386 |
|
|
0x6f, 0x02, // ble 2 |
387 |
|
|
0x42, 0x40, // clr.w d0 |
388 |
|
|
0x31, 0x40, 0x00, 0x10, //2 move.w d0,$10(a0) |
389 |
|
|
0x4e, 0x75, // rts |
390 |
|
|
0x4a, 0x40, //1 tst.w d0 |
391 |
|
|
0x6f, 0x04, // ble 3 |
392 |
|
|
0x42, 0x40, // clr.w d0 |
393 |
|
|
0x4e, 0x75, // rts |
394 |
|
|
0x2f, 0x38, 0x08, 0xfc, //3 move.l $8fc,-(sp) |
395 |
|
|
0x4e, 0x75, // rts |
396 |
|
|
|
397 |
|
|
// Close() |
398 |
|
|
0x70, 0xe8, // moveq #-24,d0 |
399 |
|
|
0x4e, 0x75 // rts |
400 |
|
|
}; |
401 |
|
|
|
402 |
|
|
static const uint8 cdrom_driver[] = { // CD-ROM driver |
403 |
|
|
// Driver header |
404 |
|
|
CDROMDriverFlags >> 8, CDROMDriverFlags & 0xff, 0, 0, 0, 0, 0, 0, |
405 |
|
|
0x00, 0x1c, // Open() offset |
406 |
|
|
0x00, 0x20, // Prime() offset |
407 |
|
|
0x00, 0x24, // Control() offset |
408 |
|
|
0x00, 0x30, // Status() offset |
409 |
|
|
0x00, 0x56, // Close() offset |
410 |
|
|
0x08, 0x2e, 0x41, 0x70, 0x70, 0x6c, 0x65, 0x43, 0x44, 0x00, // ".AppleCD" |
411 |
|
|
|
412 |
|
|
// Open() |
413 |
|
|
M68K_EMUL_OP_CDROM_OPEN >> 8, M68K_EMUL_OP_CDROM_OPEN & 0xff, |
414 |
|
|
0x4e, 0x75, // rts |
415 |
|
|
|
416 |
|
|
// Prime() |
417 |
|
|
M68K_EMUL_OP_CDROM_PRIME >> 8, M68K_EMUL_OP_CDROM_PRIME & 0xff, |
418 |
|
|
0x60, 0x0e, // bra IOReturn |
419 |
|
|
|
420 |
|
|
// Control() |
421 |
|
|
M68K_EMUL_OP_CDROM_CONTROL >> 8, M68K_EMUL_OP_CDROM_CONTROL & 0xff, |
422 |
|
|
0x0c, 0x68, 0x00, 0x01, 0x00, 0x1a, // cmp.w #1,$1a(a0) |
423 |
|
|
0x66, 0x04, // bne IOReturn |
424 |
|
|
0x4e, 0x75, // rts |
425 |
|
|
|
426 |
|
|
// Status() |
427 |
|
|
M68K_EMUL_OP_CDROM_STATUS >> 8, M68K_EMUL_OP_CDROM_STATUS & 0xff, |
428 |
|
|
|
429 |
|
|
// IOReturn |
430 |
|
|
0x32, 0x28, 0x00, 0x06, // move.w 6(a0),d1 |
431 |
|
|
0x08, 0x01, 0x00, 0x09, // btst #9,d1 |
432 |
|
|
0x67, 0x0c, // beq 1 |
433 |
|
|
0x4a, 0x40, // tst.w d0 |
434 |
|
|
0x6f, 0x02, // ble 2 |
435 |
|
|
0x42, 0x40, // clr.w d0 |
436 |
|
|
0x31, 0x40, 0x00, 0x10, //2 move.w d0,$10(a0) |
437 |
|
|
0x4e, 0x75, // rts |
438 |
|
|
0x4a, 0x40, //1 tst.w d0 |
439 |
|
|
0x6f, 0x04, // ble 3 |
440 |
|
|
0x42, 0x40, // clr.w d0 |
441 |
|
|
0x4e, 0x75, // rts |
442 |
|
|
0x2f, 0x38, 0x08, 0xfc, //3 move.l $8fc,-(sp) |
443 |
|
|
0x4e, 0x75, // rts |
444 |
|
|
|
445 |
|
|
// Close() |
446 |
|
|
0x70, 0xe8, // moveq #-24,d0 |
447 |
|
|
0x4e, 0x75 // rts |
448 |
|
|
}; |
449 |
|
|
|
450 |
|
|
#ifdef __linux__ |
451 |
|
|
static uint32 serial_nothing_tvect[2] = {(uint32)SerialNothing, 0}; |
452 |
|
|
static uint32 serial_open_tvect[2] = {(uint32)SerialOpen, 0}; |
453 |
|
|
static uint32 serial_prime_in_tvect[2] = {(uint32)SerialPrimeIn, 0}; |
454 |
|
|
static uint32 serial_prime_out_tvect[2] = {(uint32)SerialPrimeOut, 0}; |
455 |
|
|
static uint32 serial_control_tvect[2] = {(uint32)SerialControl, 0}; |
456 |
|
|
static uint32 serial_status_tvect[2] = {(uint32)SerialStatus, 0}; |
457 |
|
|
static uint32 serial_close_tvect[2] = {(uint32)SerialClose, 0}; |
458 |
|
|
#endif |
459 |
|
|
|
460 |
|
|
static const uint32 ain_driver[] = { // .AIn driver header |
461 |
|
|
0x4d000000, 0x00000000, |
462 |
|
|
0x00200040, 0x00600080, |
463 |
|
|
0x00a0042e, 0x41496e00, |
464 |
|
|
0x00000000, 0x00000000, |
465 |
|
|
0xaafe0700, 0x00000000, |
466 |
|
|
0x00000000, 0x00179822, |
467 |
|
|
#ifdef __linux__ |
468 |
|
|
0x00010004, (uint32)serial_nothing_tvect, |
469 |
|
|
#else |
470 |
|
|
0x00010004, (uint32)SerialNothing, |
471 |
|
|
#endif |
472 |
|
|
0x00000000, 0x00000000, |
473 |
|
|
0xaafe0700, 0x00000000, |
474 |
|
|
0x00000000, 0x00179822, |
475 |
|
|
#ifdef __linux__ |
476 |
|
|
0x00010004, (uint32)serial_prime_in_tvect, |
477 |
|
|
#else |
478 |
|
|
0x00010004, (uint32)SerialPrimeIn, |
479 |
|
|
#endif |
480 |
|
|
0x00000000, 0x00000000, |
481 |
|
|
0xaafe0700, 0x00000000, |
482 |
|
|
0x00000000, 0x00179822, |
483 |
|
|
#ifdef __linux__ |
484 |
|
|
0x00010004, (uint32)serial_control_tvect, |
485 |
|
|
#else |
486 |
|
|
0x00010004, (uint32)SerialControl, |
487 |
|
|
#endif |
488 |
|
|
0x00000000, 0x00000000, |
489 |
|
|
0xaafe0700, 0x00000000, |
490 |
|
|
0x00000000, 0x00179822, |
491 |
|
|
#ifdef __linux__ |
492 |
|
|
0x00010004, (uint32)serial_status_tvect, |
493 |
|
|
#else |
494 |
|
|
0x00010004, (uint32)SerialStatus, |
495 |
|
|
#endif |
496 |
|
|
0x00000000, 0x00000000, |
497 |
|
|
0xaafe0700, 0x00000000, |
498 |
|
|
0x00000000, 0x00179822, |
499 |
|
|
#ifdef __linux__ |
500 |
|
|
0x00010004, (uint32)serial_nothing_tvect, |
501 |
|
|
#else |
502 |
|
|
0x00010004, (uint32)SerialNothing, |
503 |
|
|
#endif |
504 |
|
|
0x00000000, 0x00000000, |
505 |
|
|
}; |
506 |
|
|
|
507 |
|
|
static const uint32 aout_driver[] = { // .AOut driver header |
508 |
|
|
0x4d000000, 0x00000000, |
509 |
|
|
0x00200040, 0x00600080, |
510 |
|
|
0x00a0052e, 0x414f7574, |
511 |
|
|
0x00000000, 0x00000000, |
512 |
|
|
0xaafe0700, 0x00000000, |
513 |
|
|
0x00000000, 0x00179822, |
514 |
|
|
#ifdef __linux__ |
515 |
|
|
0x00010004, (uint32)serial_open_tvect, |
516 |
|
|
#else |
517 |
|
|
0x00010004, (uint32)SerialOpen, |
518 |
|
|
#endif |
519 |
|
|
0x00000000, 0x00000000, |
520 |
|
|
0xaafe0700, 0x00000000, |
521 |
|
|
0x00000000, 0x00179822, |
522 |
|
|
#ifdef __linux__ |
523 |
|
|
0x00010004, (uint32)serial_prime_out_tvect, |
524 |
|
|
#else |
525 |
|
|
0x00010004, (uint32)SerialPrimeOut, |
526 |
|
|
#endif |
527 |
|
|
0x00000000, 0x00000000, |
528 |
|
|
0xaafe0700, 0x00000000, |
529 |
|
|
0x00000000, 0x00179822, |
530 |
|
|
#ifdef __linux__ |
531 |
|
|
0x00010004, (uint32)serial_control_tvect, |
532 |
|
|
#else |
533 |
|
|
0x00010004, (uint32)SerialControl, |
534 |
|
|
#endif |
535 |
|
|
0x00000000, 0x00000000, |
536 |
|
|
0xaafe0700, 0x00000000, |
537 |
|
|
0x00000000, 0x00179822, |
538 |
|
|
#ifdef __linux__ |
539 |
|
|
0x00010004, (uint32)serial_status_tvect, |
540 |
|
|
#else |
541 |
|
|
0x00010004, (uint32)SerialStatus, |
542 |
|
|
#endif |
543 |
|
|
0x00000000, 0x00000000, |
544 |
|
|
0xaafe0700, 0x00000000, |
545 |
|
|
0x00000000, 0x00179822, |
546 |
|
|
#ifdef __linux__ |
547 |
|
|
0x00010004, (uint32)serial_close_tvect, |
548 |
|
|
#else |
549 |
|
|
0x00010004, (uint32)SerialClose, |
550 |
|
|
#endif |
551 |
|
|
0x00000000, 0x00000000, |
552 |
|
|
}; |
553 |
|
|
|
554 |
|
|
static const uint32 bin_driver[] = { // .BIn driver header |
555 |
|
|
0x4d000000, 0x00000000, |
556 |
|
|
0x00200040, 0x00600080, |
557 |
|
|
0x00a0042e, 0x42496e00, |
558 |
|
|
0x00000000, 0x00000000, |
559 |
|
|
0xaafe0700, 0x00000000, |
560 |
|
|
0x00000000, 0x00179822, |
561 |
|
|
#ifdef __linux__ |
562 |
|
|
0x00010004, (uint32)serial_nothing_tvect, |
563 |
|
|
#else |
564 |
|
|
0x00010004, (uint32)SerialNothing, |
565 |
|
|
#endif |
566 |
|
|
0x00000000, 0x00000000, |
567 |
|
|
0xaafe0700, 0x00000000, |
568 |
|
|
0x00000000, 0x00179822, |
569 |
|
|
#ifdef __linux__ |
570 |
|
|
0x00010004, (uint32)serial_prime_in_tvect, |
571 |
|
|
#else |
572 |
|
|
0x00010004, (uint32)SerialPrimeIn, |
573 |
|
|
#endif |
574 |
|
|
0x00000000, 0x00000000, |
575 |
|
|
0xaafe0700, 0x00000000, |
576 |
|
|
0x00000000, 0x00179822, |
577 |
|
|
#ifdef __linux__ |
578 |
|
|
0x00010004, (uint32)serial_control_tvect, |
579 |
|
|
#else |
580 |
|
|
0x00010004, (uint32)SerialControl, |
581 |
|
|
#endif |
582 |
|
|
0x00000000, 0x00000000, |
583 |
|
|
0xaafe0700, 0x00000000, |
584 |
|
|
0x00000000, 0x00179822, |
585 |
|
|
#ifdef __linux__ |
586 |
|
|
0x00010004, (uint32)serial_status_tvect, |
587 |
|
|
#else |
588 |
|
|
0x00010004, (uint32)SerialStatus, |
589 |
|
|
#endif |
590 |
|
|
0x00000000, 0x00000000, |
591 |
|
|
0xaafe0700, 0x00000000, |
592 |
|
|
0x00000000, 0x00179822, |
593 |
|
|
#ifdef __linux__ |
594 |
|
|
0x00010004, (uint32)serial_nothing_tvect, |
595 |
|
|
#else |
596 |
|
|
0x00010004, (uint32)SerialNothing, |
597 |
|
|
#endif |
598 |
|
|
0x00000000, 0x00000000, |
599 |
|
|
}; |
600 |
|
|
|
601 |
|
|
static const uint32 bout_driver[] = { // .BOut driver header |
602 |
|
|
0x4d000000, 0x00000000, |
603 |
|
|
0x00200040, 0x00600080, |
604 |
|
|
0x00a0052e, 0x424f7574, |
605 |
|
|
0x00000000, 0x00000000, |
606 |
|
|
0xaafe0700, 0x00000000, |
607 |
|
|
0x00000000, 0x00179822, |
608 |
|
|
#ifdef __linux__ |
609 |
|
|
0x00010004, (uint32)serial_open_tvect, |
610 |
|
|
#else |
611 |
|
|
0x00010004, (uint32)SerialOpen, |
612 |
|
|
#endif |
613 |
|
|
0x00000000, 0x00000000, |
614 |
|
|
0xaafe0700, 0x00000000, |
615 |
|
|
0x00000000, 0x00179822, |
616 |
|
|
#ifdef __linux__ |
617 |
|
|
0x00010004, (uint32)serial_prime_out_tvect, |
618 |
|
|
#else |
619 |
|
|
0x00010004, (uint32)SerialPrimeOut, |
620 |
|
|
#endif |
621 |
|
|
0x00000000, 0x00000000, |
622 |
|
|
0xaafe0700, 0x00000000, |
623 |
|
|
0x00000000, 0x00179822, |
624 |
|
|
#ifdef __linux__ |
625 |
|
|
0x00010004, (uint32)serial_control_tvect, |
626 |
|
|
#else |
627 |
|
|
0x00010004, (uint32)SerialControl, |
628 |
|
|
#endif |
629 |
|
|
0x00000000, 0x00000000, |
630 |
|
|
0xaafe0700, 0x00000000, |
631 |
|
|
0x00000000, 0x00179822, |
632 |
|
|
#ifdef __linux__ |
633 |
|
|
0x00010004, (uint32)serial_status_tvect, |
634 |
|
|
#else |
635 |
|
|
0x00010004, (uint32)SerialStatus, |
636 |
|
|
#endif |
637 |
|
|
0x00000000, 0x00000000, |
638 |
|
|
0xaafe0700, 0x00000000, |
639 |
|
|
0x00000000, 0x00179822, |
640 |
|
|
#ifdef __linux__ |
641 |
|
|
0x00010004, (uint32)serial_close_tvect, |
642 |
|
|
#else |
643 |
|
|
0x00010004, (uint32)SerialClose, |
644 |
|
|
#endif |
645 |
|
|
0x00000000, 0x00000000, |
646 |
|
|
}; |
647 |
|
|
|
648 |
|
|
static const uint8 adbop_patch[] = { // Call ADBOp() completion procedure |
649 |
|
|
// The completion procedure may call ADBOp() again! |
650 |
|
|
0x40, 0xe7, // move sr,-(sp) |
651 |
|
|
0x00, 0x7c, 0x07, 0x00, // ori #$0700,sr |
652 |
|
|
M68K_EMUL_OP_ADBOP >> 8, M68K_EMUL_OP_ADBOP & 0xff, |
653 |
|
|
0x48, 0xe7, 0x70, 0xf0, // movem.l d1-d3/a0-a3,-(sp) |
654 |
|
|
0x26, 0x48, // move.l a0,a3 |
655 |
|
|
0x4a, 0xab, 0x00, 0x04, // tst.l 4(a3) |
656 |
|
|
0x67, 0x00, 0x00, 0x18, // beq 1 |
657 |
|
|
0x20, 0x53, // move.l (a3),a0 |
658 |
|
|
0x22, 0x6b, 0x00, 0x04, // move.l 4(a3),a1 |
659 |
|
|
0x24, 0x6b, 0x00, 0x08, // move.l 8(a3),a2 |
660 |
|
|
0x26, 0x78, 0x0c, 0xf8, // move.l $cf8,a3 |
661 |
|
|
0x4e, 0x91, // jsr (a1) |
662 |
|
|
0x70, 0x00, // moveq #0,d0 |
663 |
|
|
0x60, 0x00, 0x00, 0x04, // bra 2 |
664 |
|
|
0x70, 0xff, //1 moveq #-1,d0 |
665 |
|
|
0x4c, 0xdf, 0x0f, 0x0e, //2 movem.l (sp)+,d1-d3/a0-a3 |
666 |
|
|
0x46, 0xdf, // move (sp)+,sr |
667 |
|
|
0x4e, 0x75 // rts |
668 |
|
|
}; |
669 |
|
|
|
670 |
|
|
|
671 |
|
|
/* |
672 |
|
|
* Install ROM patches (RAMBase and KernelDataAddr must be set) |
673 |
|
|
*/ |
674 |
|
|
|
675 |
|
|
bool PatchROM(void) |
676 |
|
|
{ |
677 |
|
|
// Print ROM info |
678 |
|
|
D(bug("Checksum: %08lx\n", ntohl(*(uint32 *)ROM_BASE))); |
679 |
|
|
D(bug("Version: %04x\n", ntohs(*(uint16 *)(ROM_BASE + 8)))); |
680 |
|
|
D(bug("Sub Version: %04x\n", ntohs(*(uint16 *)(ROM_BASE + 18)))); |
681 |
|
|
D(bug("Nanokernel ID: %s\n", (char *)ROM_BASE + 0x30d064)); |
682 |
|
|
D(bug("Resource Map at %08lx\n", ntohl(*(uint32 *)(ROM_BASE + 26)))); |
683 |
|
|
D(bug("Trap Tables at %08lx\n\n", ntohl(*(uint32 *)(ROM_BASE + 34)))); |
684 |
|
|
|
685 |
|
|
// Detect ROM type |
686 |
|
|
if (!memcmp((void *)(ROM_BASE + 0x30d064), "Boot TNT", 8)) |
687 |
|
|
ROMType = ROMTYPE_TNT; |
688 |
|
|
else if (!memcmp((void *)(ROM_BASE + 0x30d064), "Boot Alchemy", 12)) |
689 |
|
|
ROMType = ROMTYPE_ALCHEMY; |
690 |
|
|
else if (!memcmp((void *)(ROM_BASE + 0x30d064), "Boot Zanzibar", 13)) |
691 |
|
|
ROMType = ROMTYPE_ZANZIBAR; |
692 |
|
|
else if (!memcmp((void *)(ROM_BASE + 0x30d064), "Boot Gazelle", 12)) |
693 |
|
|
ROMType = ROMTYPE_GAZELLE; |
694 |
|
|
else if (!memcmp((void *)(ROM_BASE + 0x30d064), "NewWorld", 8)) |
695 |
|
|
ROMType = ROMTYPE_NEWWORLD; |
696 |
|
|
else |
697 |
|
|
return false; |
698 |
|
|
|
699 |
|
|
// Apply patches |
700 |
|
|
if (!patch_nanokernel_boot()) return false; |
701 |
|
|
if (!patch_68k_emul()) return false; |
702 |
|
|
if (!patch_nanokernel()) return false; |
703 |
|
|
if (!patch_68k()) return false; |
704 |
|
|
|
705 |
|
|
#ifdef M68K_BREAK_POINT |
706 |
|
|
// Install 68k breakpoint |
707 |
|
|
uint16 *wp = (uint16 *)(ROM_BASE + M68K_BREAK_POINT); |
708 |
|
|
*wp++ = htons(M68K_EMUL_BREAK); |
709 |
|
|
*wp = htons(M68K_EMUL_RETURN); |
710 |
|
|
#endif |
711 |
|
|
|
712 |
|
|
#ifdef POWERPC_BREAK_POINT |
713 |
|
|
// Install PowerPC breakpoint |
714 |
|
|
uint32 *lp = (uint32 *)(ROM_BASE + POWERPC_BREAK_POINT); |
715 |
|
|
*lp = htonl(0); |
716 |
|
|
#endif |
717 |
|
|
|
718 |
|
|
// Copy 68k emulator to 2MB boundary |
719 |
|
|
memcpy((void *)(ROM_BASE + ROM_SIZE), (void *)(ROM_BASE + ROM_SIZE - 0x100000), 0x100000); |
720 |
|
|
return true; |
721 |
|
|
} |
722 |
|
|
|
723 |
|
|
|
724 |
|
|
/* |
725 |
|
|
* Nanokernel boot routine patches |
726 |
|
|
*/ |
727 |
|
|
|
728 |
|
|
static bool patch_nanokernel_boot(void) |
729 |
|
|
{ |
730 |
|
|
uint32 *lp; |
731 |
|
|
|
732 |
|
|
// ROM boot structure patches |
733 |
|
|
lp = (uint32 *)(ROM_BASE + 0x30d000); |
734 |
|
|
lp[0x9c >> 2] = htonl(KernelDataAddr); // LA_InfoRecord |
735 |
|
|
lp[0xa0 >> 2] = htonl(KernelDataAddr); // LA_KernelData |
736 |
|
|
lp[0xa4 >> 2] = htonl(KernelDataAddr + 0x1000); // LA_EmulatorData |
737 |
|
|
lp[0xa8 >> 2] = htonl(ROM_BASE + 0x480000); // LA_DispatchTable |
738 |
|
|
lp[0xac >> 2] = htonl(ROM_BASE + 0x460000); // LA_EmulatorCode |
739 |
|
|
lp[0x360 >> 2] = htonl(0); // Physical RAM base (? on NewWorld ROM, this contains -1) |
740 |
|
|
lp[0xfd8 >> 2] = htonl(ROM_BASE + 0x2a); // 68k reset vector |
741 |
|
|
|
742 |
|
|
// Skip SR/BAT/SDR init |
743 |
|
|
if (ROMType == ROMTYPE_GAZELLE || ROMType == ROMTYPE_NEWWORLD) { |
744 |
|
|
lp = (uint32 *)(ROM_BASE + 0x310000); |
745 |
|
|
*lp++ = htonl(POWERPC_NOP); |
746 |
|
|
*lp = htonl(0x38000000); |
747 |
|
|
} |
748 |
|
|
static const uint32 sr_init_loc[] = {0x3101b0, 0x3101b0, 0x3101b0, 0x3101ec, 0x310200}; |
749 |
|
|
lp = (uint32 *)(ROM_BASE + 0x310008); |
750 |
|
|
*lp = htonl(0x48000000 | (sr_init_loc[ROMType] - 8) & 0xffff); // b ROM_BASE+0x3101b0 |
751 |
|
|
lp = (uint32 *)(ROM_BASE + sr_init_loc[ROMType]); |
752 |
|
|
*lp++ = htonl(0x80200000 + XLM_KERNEL_DATA); // lwz r1,(pointer to Kernel Data) |
753 |
|
|
*lp++ = htonl(0x3da0dead); // lis r13,0xdead (start of kernel memory) |
754 |
|
|
*lp++ = htonl(0x3dc00010); // lis r14,0x0010 (size of page table) |
755 |
|
|
*lp = htonl(0x3de00010); // lis r15,0x0010 (size of kernel memory) |
756 |
|
|
|
757 |
|
|
// Don't read PVR |
758 |
|
|
static const uint32 pvr_loc[] = {0x3103b0, 0x3103b4, 0x3103b4, 0x310400, 0x310438}; |
759 |
|
|
lp = (uint32 *)(ROM_BASE + pvr_loc[ROMType]); |
760 |
|
|
*lp = htonl(0x81800000 + XLM_PVR); // lwz r12,(theoretical PVR) |
761 |
|
|
|
762 |
|
|
// Set CPU specific data (even if ROM doesn't have support for that CPU) |
763 |
|
|
lp = (uint32 *)(ROM_BASE + pvr_loc[ROMType]); |
764 |
|
|
if (ntohl(lp[6]) != 0x2c0c0001) |
765 |
|
|
return false; |
766 |
|
|
uint32 ofs = ntohl(lp[7]) & 0xffff; |
767 |
|
|
D(bug("ofs %08lx\n", ofs)); |
768 |
|
|
lp[8] = htonl((ntohl(lp[8]) & 0xffff) | 0x48000000); // beq -> b |
769 |
|
|
uint32 loc = (ntohl(lp[8]) & 0xffff) + (uint32)(lp+8) - ROM_BASE; |
770 |
|
|
D(bug("loc %08lx\n", loc)); |
771 |
|
|
lp = (uint32 *)(ROM_BASE + ofs + 0x310000); |
772 |
|
|
switch (PVR >> 16) { |
773 |
|
|
case 1: // 601 |
774 |
|
|
lp[0] = htonl(0x1000); // Page size |
775 |
|
|
lp[1] = htonl(0x8000); // Data cache size |
776 |
|
|
lp[2] = htonl(0x8000); // Inst cache size |
777 |
|
|
lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size |
778 |
|
|
lp[4] = htonl(0x00010040); // Unified caches/Inst cache line size |
779 |
|
|
lp[5] = htonl(0x00400020); // Data cache line size/Data cache block size touch |
780 |
|
|
lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size |
781 |
|
|
lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc |
782 |
|
|
lp[8] = htonl(0x01000002); // TLB total size/TLB assoc |
783 |
|
|
break; |
784 |
|
|
case 3: // 603 |
785 |
|
|
lp[0] = htonl(0x1000); // Page size |
786 |
|
|
lp[1] = htonl(0x2000); // Data cache size |
787 |
|
|
lp[2] = htonl(0x2000); // Inst cache size |
788 |
|
|
lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size |
789 |
|
|
lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size |
790 |
|
|
lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch |
791 |
|
|
lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size |
792 |
|
|
lp[7] = htonl(0x00020002); // Inst cache assoc/Data cache assoc |
793 |
|
|
lp[8] = htonl(0x00400002); // TLB total size/TLB assoc |
794 |
|
|
break; |
795 |
|
|
case 4: // 604 |
796 |
|
|
lp[0] = htonl(0x1000); // Page size |
797 |
|
|
lp[1] = htonl(0x4000); // Data cache size |
798 |
|
|
lp[2] = htonl(0x4000); // Inst cache size |
799 |
|
|
lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size |
800 |
|
|
lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size |
801 |
|
|
lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch |
802 |
|
|
lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size |
803 |
|
|
lp[7] = htonl(0x00040004); // Inst cache assoc/Data cache assoc |
804 |
|
|
lp[8] = htonl(0x00800002); // TLB total size/TLB assoc |
805 |
|
|
break; |
806 |
|
|
// case 5: // 740? |
807 |
|
|
case 6: // 603e |
808 |
|
|
case 7: // 603ev |
809 |
|
|
lp[0] = htonl(0x1000); // Page size |
810 |
|
|
lp[1] = htonl(0x4000); // Data cache size |
811 |
|
|
lp[2] = htonl(0x4000); // Inst cache size |
812 |
|
|
lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size |
813 |
|
|
lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size |
814 |
|
|
lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch |
815 |
|
|
lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size |
816 |
|
|
lp[7] = htonl(0x00040004); // Inst cache assoc/Data cache assoc |
817 |
|
|
lp[8] = htonl(0x00400002); // TLB total size/TLB assoc |
818 |
|
|
break; |
819 |
|
|
case 8: // 750 |
820 |
|
|
lp[0] = htonl(0x1000); // Page size |
821 |
|
|
lp[1] = htonl(0x8000); // Data cache size |
822 |
|
|
lp[2] = htonl(0x8000); // Inst cache size |
823 |
|
|
lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size |
824 |
|
|
lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size |
825 |
|
|
lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch |
826 |
|
|
lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size |
827 |
|
|
lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc |
828 |
|
|
lp[8] = htonl(0x00800002); // TLB total size/TLB assoc |
829 |
|
|
break; |
830 |
|
|
case 9: // 604e |
831 |
|
|
case 10: // 604ev5 |
832 |
|
|
lp[0] = htonl(0x1000); // Page size |
833 |
|
|
lp[1] = htonl(0x8000); // Data cache size |
834 |
|
|
lp[2] = htonl(0x8000); // Inst cache size |
835 |
|
|
lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size |
836 |
|
|
lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size |
837 |
|
|
lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch |
838 |
|
|
lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size |
839 |
|
|
lp[7] = htonl(0x00040004); // Inst cache assoc/Data cache assoc |
840 |
|
|
lp[8] = htonl(0x00800002); // TLB total size/TLB assoc |
841 |
|
|
break; |
842 |
|
|
// case 11: // X704? |
843 |
|
|
case 12: // ??? |
844 |
|
|
lp[0] = htonl(0x1000); // Page size |
845 |
|
|
lp[1] = htonl(0x8000); // Data cache size |
846 |
|
|
lp[2] = htonl(0x8000); // Inst cache size |
847 |
|
|
lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size |
848 |
|
|
lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size |
849 |
|
|
lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch |
850 |
|
|
lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size |
851 |
|
|
lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc |
852 |
|
|
lp[8] = htonl(0x00800002); // TLB total size/TLB assoc |
853 |
|
|
break; |
854 |
|
|
case 13: // ??? |
855 |
|
|
lp[0] = htonl(0x1000); // Page size |
856 |
|
|
lp[1] = htonl(0x8000); // Data cache size |
857 |
|
|
lp[2] = htonl(0x8000); // Inst cache size |
858 |
|
|
lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size |
859 |
|
|
lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size |
860 |
|
|
lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch |
861 |
|
|
lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size |
862 |
|
|
lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc |
863 |
|
|
lp[8] = htonl(0x01000004); // TLB total size/TLB assoc |
864 |
|
|
break; |
865 |
|
|
// case 50: // 821 |
866 |
|
|
// case 80: // 860 |
867 |
|
|
case 96: // ??? |
868 |
|
|
lp[0] = htonl(0x1000); // Page size |
869 |
|
|
lp[1] = htonl(0x8000); // Data cache size |
870 |
|
|
lp[2] = htonl(0x8000); // Inst cache size |
871 |
|
|
lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size |
872 |
|
|
lp[4] = htonl(0x00010020); // Unified caches/Inst cache line size |
873 |
|
|
lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch |
874 |
|
|
lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size |
875 |
|
|
lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc |
876 |
|
|
lp[8] = htonl(0x00800004); // TLB total size/TLB assoc |
877 |
|
|
break; |
878 |
|
|
default: |
879 |
|
|
printf("WARNING: Unknown CPU type\n"); |
880 |
|
|
break; |
881 |
|
|
} |
882 |
|
|
|
883 |
|
|
// Don't set SPRG3, don't test MQ |
884 |
|
|
lp = (uint32 *)(ROM_BASE + loc + 0x20); |
885 |
|
|
*lp++ = htonl(POWERPC_NOP); |
886 |
|
|
lp++; |
887 |
|
|
*lp++ = htonl(POWERPC_NOP); |
888 |
|
|
lp++; |
889 |
|
|
*lp = htonl(POWERPC_NOP); |
890 |
|
|
|
891 |
|
|
// Don't read MSR |
892 |
|
|
lp = (uint32 *)(ROM_BASE + loc + 0x40); |
893 |
|
|
*lp = htonl(0x39c00000); // li r14,0 |
894 |
|
|
|
895 |
|
|
// Don't write to DEC |
896 |
|
|
lp = (uint32 *)(ROM_BASE + loc + 0x70); |
897 |
|
|
*lp++ = htonl(POWERPC_NOP); |
898 |
|
|
loc = (ntohl(lp[0]) & 0xffff) + (uint32)lp - ROM_BASE; |
899 |
|
|
D(bug("loc %08lx\n", loc)); |
900 |
|
|
|
901 |
|
|
// Don't set SPRG3 |
902 |
|
|
lp = (uint32 *)(ROM_BASE + loc + 0x2c); |
903 |
|
|
*lp = htonl(POWERPC_NOP); |
904 |
|
|
|
905 |
|
|
// Don't read PVR |
906 |
|
|
static const uint32 pvr_ofs[] = {0x138, 0x138, 0x138, 0x140, 0x148}; |
907 |
|
|
lp = (uint32 *)(ROM_BASE + loc + pvr_ofs[ROMType]); |
908 |
|
|
*lp = htonl(0x82e00000 + XLM_PVR); // lwz r23,(theoretical PVR) |
909 |
|
|
lp = (uint32 *)(ROM_BASE + loc + 0x170); |
910 |
|
|
if (ntohl(*lp) == 0x7eff42a6) // NewWorld ROM |
911 |
|
|
*lp = htonl(0x82e00000 + XLM_PVR); // lwz r23,(theoretical PVR) |
912 |
|
|
lp = (uint32 *)(ROM_BASE + 0x313134); |
913 |
|
|
if (ntohl(*lp) == 0x7e5f42a6) |
914 |
|
|
*lp = htonl(0x82400000 + XLM_PVR); // lwz r18,(theoretical PVR) |
915 |
|
|
lp = (uint32 *)(ROM_BASE + 0x3131f4); |
916 |
|
|
if (ntohl(*lp) == 0x7e5f42a6) // NewWorld ROM |
917 |
|
|
*lp = htonl(0x82400000 + XLM_PVR); // lwz r18,(theoretical PVR) |
918 |
|
|
|
919 |
|
|
// Don't read SDR1 |
920 |
|
|
static const uint32 sdr1_ofs[] = {0x174, 0x174, 0x174, 0x17c, 0x19c}; |
921 |
|
|
lp = (uint32 *)(ROM_BASE + loc + sdr1_ofs[ROMType]); |
922 |
|
|
*lp++ = htonl(0x3d00dead); // lis r8,0xdead (pointer to page table) |
923 |
|
|
*lp++ = htonl(0x3ec0001f); // lis r22,0x001f (size of page table) |
924 |
|
|
*lp = htonl(POWERPC_NOP); |
925 |
|
|
|
926 |
|
|
// Don't clear page table |
927 |
|
|
static const uint32 pgtb_ofs[] = {0x198, 0x198, 0x198, 0x1a0, 0x1c4}; |
928 |
|
|
lp = (uint32 *)(ROM_BASE + loc + pgtb_ofs[ROMType]); |
929 |
|
|
*lp = htonl(POWERPC_NOP); |
930 |
|
|
|
931 |
|
|
// Don't invalidate TLB |
932 |
|
|
static const uint32 tlb_ofs[] = {0x1a0, 0x1a0, 0x1a0, 0x1a8, 0x1cc}; |
933 |
|
|
lp = (uint32 *)(ROM_BASE + loc + tlb_ofs[ROMType]); |
934 |
|
|
*lp = htonl(POWERPC_NOP); |
935 |
|
|
|
936 |
|
|
// Don't create RAM descriptor table |
937 |
|
|
static const uint32 desc_ofs[] = {0x350, 0x350, 0x350, 0x358, 0x37c}; |
938 |
|
|
lp = (uint32 *)(ROM_BASE + loc + desc_ofs[ROMType]); |
939 |
|
|
*lp = htonl(POWERPC_NOP); |
940 |
|
|
|
941 |
|
|
// Don't load SRs and BATs |
942 |
|
|
static const uint32 sr_ofs[] = {0x3d8, 0x3d8, 0x3d8, 0x3e0, 0x404}; |
943 |
|
|
lp = (uint32 *)(ROM_BASE + loc + sr_ofs[ROMType]); |
944 |
|
|
*lp = htonl(POWERPC_NOP); |
945 |
|
|
|
946 |
|
|
// Don't mess with SRs |
947 |
|
|
static const uint32 sr2_ofs[] = {0x312118, 0x312118, 0x312118, 0x312118, 0x3121b4}; |
948 |
|
|
lp = (uint32 *)(ROM_BASE + sr2_ofs[ROMType]); |
949 |
|
|
*lp = htonl(POWERPC_BLR); |
950 |
|
|
|
951 |
|
|
// Don't check performance monitor |
952 |
|
|
static const uint32 pm_ofs[] = {0x313148, 0x313148, 0x313148, 0x313148, 0x313218}; |
953 |
|
|
lp = (uint32 *)(ROM_BASE + pm_ofs[ROMType]); |
954 |
|
|
while (ntohl(*lp) != 0x7e58eba6) lp++; |
955 |
|
|
*lp++ = htonl(POWERPC_NOP); |
956 |
|
|
while (ntohl(*lp) != 0x7e78eaa6) lp++; |
957 |
|
|
*lp++ = htonl(POWERPC_NOP); |
958 |
|
|
while (ntohl(*lp) != 0x7e59eba6) lp++; |
959 |
|
|
*lp++ = htonl(POWERPC_NOP); |
960 |
|
|
while (ntohl(*lp) != 0x7e79eaa6) lp++; |
961 |
|
|
*lp++ = htonl(POWERPC_NOP); |
962 |
|
|
while (ntohl(*lp) != 0x7e5aeba6) lp++; |
963 |
|
|
*lp++ = htonl(POWERPC_NOP); |
964 |
|
|
while (ntohl(*lp) != 0x7e7aeaa6) lp++; |
965 |
|
|
*lp++ = htonl(POWERPC_NOP); |
966 |
|
|
while (ntohl(*lp) != 0x7e5beba6) lp++; |
967 |
|
|
*lp++ = htonl(POWERPC_NOP); |
968 |
|
|
while (ntohl(*lp) != 0x7e7beaa6) lp++; |
969 |
|
|
*lp++ = htonl(POWERPC_NOP); |
970 |
|
|
while (ntohl(*lp) != 0x7e5feba6) lp++; |
971 |
|
|
*lp++ = htonl(POWERPC_NOP); |
972 |
|
|
while (ntohl(*lp) != 0x7e7feaa6) lp++; |
973 |
|
|
*lp++ = htonl(POWERPC_NOP); |
974 |
|
|
while (ntohl(*lp) != 0x7e5ceba6) lp++; |
975 |
|
|
*lp++ = htonl(POWERPC_NOP); |
976 |
|
|
while (ntohl(*lp) != 0x7e7ceaa6) lp++; |
977 |
|
|
*lp++ = htonl(POWERPC_NOP); |
978 |
|
|
while (ntohl(*lp) != 0x7e5deba6) lp++; |
979 |
|
|
*lp++ = htonl(POWERPC_NOP); |
980 |
|
|
while (ntohl(*lp) != 0x7e7deaa6) lp++; |
981 |
|
|
*lp++ = htonl(POWERPC_NOP); |
982 |
|
|
while (ntohl(*lp) != 0x7e5eeba6) lp++; |
983 |
|
|
*lp++ = htonl(POWERPC_NOP); |
984 |
|
|
while (ntohl(*lp) != 0x7e7eeaa6) lp++; |
985 |
|
|
*lp++ = htonl(POWERPC_NOP); |
986 |
|
|
|
987 |
|
|
// Jump to 68k emulator |
988 |
|
|
static const uint32 jump68k_ofs[] = {0x40c, 0x40c, 0x40c, 0x414, 0x438}; |
989 |
|
|
lp = (uint32 *)(ROM_BASE + loc + jump68k_ofs[ROMType]); |
990 |
|
|
*lp++ = htonl(0x80610634); // lwz r3,0x0634(r1) (pointer to Emulator Data) |
991 |
|
|
*lp++ = htonl(0x8081119c); // lwz r4,0x119c(r1) (pointer to opcode table) |
992 |
|
|
*lp++ = htonl(0x80011184); // lwz r0,0x1184(r1) (pointer to emulator init routine) |
993 |
|
|
*lp++ = htonl(0x7c0903a6); // mtctr r0 |
994 |
|
|
*lp = htonl(POWERPC_BCTR); |
995 |
|
|
return true; |
996 |
|
|
} |
997 |
|
|
|
998 |
|
|
|
999 |
|
|
/* |
1000 |
|
|
* 68k emulator patches |
1001 |
|
|
*/ |
1002 |
|
|
|
1003 |
|
|
static bool patch_68k_emul(void) |
1004 |
|
|
{ |
1005 |
|
|
uint32 *lp; |
1006 |
|
|
uint32 base; |
1007 |
|
|
|
1008 |
|
|
// Overwrite twi instructions |
1009 |
|
|
static const uint32 twi_loc[] = {0x36e680, 0x36e6c0, 0x36e6c0, 0x36e6c0, 0x36e740}; |
1010 |
|
|
base = twi_loc[ROMType]; |
1011 |
|
|
lp = (uint32 *)(ROM_BASE + base); |
1012 |
|
|
*lp++ = htonl(0x48000000 + 0x36f900 - base); // b 0x36f900 (Emulator start) |
1013 |
|
|
*lp++ = htonl(0x48000000 + 0x36fa00 - base - 4); // b 0x36fa00 (Mixed mode) |
1014 |
|
|
*lp++ = htonl(0x48000000 + 0x36fb00 - base - 8); // b 0x36fb00 (Reset/FC1E opcode) |
1015 |
|
|
*lp++ = htonl(0x48000000 + 0x36fc00 - base - 12); // FE0A opcode |
1016 |
|
|
*lp++ = htonl(POWERPC_ILLEGAL); // Interrupt |
1017 |
|
|
*lp++ = htonl(POWERPC_ILLEGAL); // ? |
1018 |
|
|
*lp++ = htonl(POWERPC_ILLEGAL); |
1019 |
|
|
*lp++ = htonl(POWERPC_ILLEGAL); |
1020 |
|
|
*lp++ = htonl(POWERPC_ILLEGAL); |
1021 |
|
|
*lp++ = htonl(POWERPC_ILLEGAL); |
1022 |
|
|
*lp++ = htonl(POWERPC_ILLEGAL); |
1023 |
|
|
*lp++ = htonl(POWERPC_ILLEGAL); |
1024 |
|
|
*lp++ = htonl(POWERPC_ILLEGAL); |
1025 |
|
|
*lp++ = htonl(POWERPC_ILLEGAL); |
1026 |
|
|
*lp++ = htonl(POWERPC_ILLEGAL); |
1027 |
|
|
*lp = htonl(POWERPC_ILLEGAL); |
1028 |
|
|
|
1029 |
|
|
#if EMULATED_PPC |
1030 |
|
|
// Install EMUL_RETURN, EXEC_RETURN and EMUL_OP opcodes |
1031 |
|
|
lp = (uint32 *)(ROM_BASE + 0x380000 + (M68K_EMUL_RETURN << 3)); |
1032 |
|
|
*lp++ = htonl(POWERPC_EMUL_OP); |
1033 |
|
|
*lp++ = htonl(0x4bf66e80); // b 0x366084 |
1034 |
|
|
*lp++ = htonl(POWERPC_EMUL_OP | 1); |
1035 |
|
|
*lp++ = htonl(0x4bf66e78); // b 0x366084 |
1036 |
|
|
for (int i=0; i<OP_MAX; i++) { |
1037 |
|
|
*lp++ = htonl(POWERPC_EMUL_OP | (i + 2)); |
1038 |
|
|
*lp++ = htonl(0x4bf66e70 - i*8); // b 0x366084 |
1039 |
|
|
} |
1040 |
|
|
#else |
1041 |
|
|
// Install EMUL_RETURN, EXEC_RETURN and EMUL_OP opcodes |
1042 |
|
|
lp = (uint32 *)(ROM_BASE + 0x380000 + (M68K_EMUL_RETURN << 3)); |
1043 |
|
|
*lp++ = htonl(0x80000000 + XLM_EMUL_RETURN_PROC); // lwz r0,XLM_EMUL_RETURN_PROC |
1044 |
|
|
*lp++ = htonl(0x4bf705fc); // b 0x36f800 |
1045 |
|
|
*lp++ = htonl(0x80000000 + XLM_EXEC_RETURN_PROC); // lwz r0,XLM_EXEC_RETURN_PROC |
1046 |
|
|
*lp++ = htonl(0x4bf705f4); // b 0x36f800 |
1047 |
|
|
for (int i=0; i<OP_MAX; i++) { |
1048 |
|
|
*lp++ = htonl(0x38a00000 + i); // li r5,OP_* |
1049 |
|
|
*lp++ = htonl(0x4bf705f4 - i*8); // b 0x36f808 |
1050 |
|
|
} |
1051 |
|
|
|
1052 |
|
|
// Extra routines for EMUL_RETURN/EXEC_RETURN/EMUL_OP |
1053 |
|
|
lp = (uint32 *)(ROM_BASE + 0x36f800); |
1054 |
|
|
*lp++ = htonl(0x7c0803a6); // mtlr r0 |
1055 |
|
|
*lp++ = htonl(0x4e800020); // blr |
1056 |
|
|
|
1057 |
|
|
*lp++ = htonl(0x80000000 + XLM_EMUL_OP_PROC); // lwz r0,XLM_EMUL_OP_PROC |
1058 |
|
|
*lp++ = htonl(0x7c0803a6); // mtlr r0 |
1059 |
|
|
*lp = htonl(0x4e800020); // blr |
1060 |
|
|
#endif |
1061 |
|
|
|
1062 |
|
|
// Extra routine for 68k emulator start |
1063 |
|
|
lp = (uint32 *)(ROM_BASE + 0x36f900); |
1064 |
|
|
*lp++ = htonl(0x7c2903a6); // mtctr r1 |
1065 |
|
|
*lp++ = htonl(0x80200000 + XLM_IRQ_NEST); // lwz r1,XLM_IRQ_NEST |
1066 |
|
|
*lp++ = htonl(0x38210001); // addi r1,r1,1 |
1067 |
|
|
*lp++ = htonl(0x90200000 + XLM_IRQ_NEST); // stw r1,XLM_IRQ_NEST |
1068 |
|
|
*lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz r1,XLM_KERNEL_DATA |
1069 |
|
|
*lp++ = htonl(0x90c10018); // stw r6,0x18(r1) |
1070 |
|
|
*lp++ = htonl(0x7cc902a6); // mfctr r6 |
1071 |
|
|
*lp++ = htonl(0x90c10004); // stw r6,$0004(r1) |
1072 |
|
|
*lp++ = htonl(0x80c1065c); // lwz r6,$065c(r1) |
1073 |
|
|
*lp++ = htonl(0x90e6013c); // stw r7,$013c(r6) |
1074 |
|
|
*lp++ = htonl(0x91060144); // stw r8,$0144(r6) |
1075 |
|
|
*lp++ = htonl(0x9126014c); // stw r9,$014c(r6) |
1076 |
|
|
*lp++ = htonl(0x91460154); // stw r10,$0154(r6) |
1077 |
|
|
*lp++ = htonl(0x9166015c); // stw r11,$015c(r6) |
1078 |
|
|
*lp++ = htonl(0x91860164); // stw r12,$0164(r6) |
1079 |
|
|
*lp++ = htonl(0x91a6016c); // stw r13,$016c(r6) |
1080 |
|
|
*lp++ = htonl(0x7da00026); // mfcr r13 |
1081 |
|
|
*lp++ = htonl(0x80e10660); // lwz r7,$0660(r1) |
1082 |
|
|
*lp++ = htonl(0x7d8802a6); // mflr r12 |
1083 |
|
|
*lp++ = htonl(0x50e74001); // rlwimi. r7,r7,8,$80000000 |
1084 |
|
|
*lp++ = htonl(0x814105f0); // lwz r10,0x05f0(r1) |
1085 |
|
|
*lp++ = htonl(0x7d4803a6); // mtlr r10 |
1086 |
|
|
*lp++ = htonl(0x7d8a6378); // mr r10,r12 |
1087 |
|
|
*lp++ = htonl(0x3d600002); // lis r11,0x0002 |
1088 |
|
|
*lp++ = htonl(0x616bf072); // ori r11,r11,0xf072 (MSR) |
1089 |
|
|
*lp++ = htonl(0x50e7deb4); // rlwimi r7,r7,27,$00000020 |
1090 |
|
|
*lp = htonl(0x4e800020); // blr |
1091 |
|
|
|
1092 |
|
|
// Extra routine for Mixed Mode |
1093 |
|
|
lp = (uint32 *)(ROM_BASE + 0x36fa00); |
1094 |
|
|
*lp++ = htonl(0x7c2903a6); // mtctr r1 |
1095 |
|
|
*lp++ = htonl(0x80200000 + XLM_IRQ_NEST); // lwz r1,XLM_IRQ_NEST |
1096 |
|
|
*lp++ = htonl(0x38210001); // addi r1,r1,1 |
1097 |
|
|
*lp++ = htonl(0x90200000 + XLM_IRQ_NEST); // stw r1,XLM_IRQ_NEST |
1098 |
|
|
*lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz r1,XLM_KERNEL_DATA |
1099 |
|
|
*lp++ = htonl(0x90c10018); // stw r6,0x18(r1) |
1100 |
|
|
*lp++ = htonl(0x7cc902a6); // mfctr r6 |
1101 |
|
|
*lp++ = htonl(0x90c10004); // stw r6,$0004(r1) |
1102 |
|
|
*lp++ = htonl(0x80c1065c); // lwz r6,$065c(r1) |
1103 |
|
|
*lp++ = htonl(0x90e6013c); // stw r7,$013c(r6) |
1104 |
|
|
*lp++ = htonl(0x91060144); // stw r8,$0144(r6) |
1105 |
|
|
*lp++ = htonl(0x9126014c); // stw r9,$014c(r6) |
1106 |
|
|
*lp++ = htonl(0x91460154); // stw r10,$0154(r6) |
1107 |
|
|
*lp++ = htonl(0x9166015c); // stw r11,$015c(r6) |
1108 |
|
|
*lp++ = htonl(0x91860164); // stw r12,$0164(r6) |
1109 |
|
|
*lp++ = htonl(0x91a6016c); // stw r13,$016c(r6) |
1110 |
|
|
*lp++ = htonl(0x7da00026); // mfcr r13 |
1111 |
|
|
*lp++ = htonl(0x80e10660); // lwz r7,$0660(r1) |
1112 |
|
|
*lp++ = htonl(0x7d8802a6); // mflr r12 |
1113 |
|
|
*lp++ = htonl(0x50e74001); // rlwimi. r7,r7,8,$80000000 |
1114 |
|
|
*lp++ = htonl(0x814105f4); // lwz r10,0x05f4(r1) |
1115 |
|
|
*lp++ = htonl(0x7d4803a6); // mtlr r10 |
1116 |
|
|
*lp++ = htonl(0x7d8a6378); // mr r10,r12 |
1117 |
|
|
*lp++ = htonl(0x3d600002); // lis r11,0x0002 |
1118 |
|
|
*lp++ = htonl(0x616bf072); // ori r11,r11,0xf072 (MSR) |
1119 |
|
|
*lp++ = htonl(0x50e7deb4); // rlwimi r7,r7,27,$00000020 |
1120 |
|
|
*lp = htonl(0x4e800020); // blr |
1121 |
|
|
|
1122 |
|
|
// Extra routine for Reset/FC1E opcode |
1123 |
|
|
lp = (uint32 *)(ROM_BASE + 0x36fc00); |
1124 |
|
|
*lp++ = htonl(0x7c2903a6); // mtctr r1 |
1125 |
|
|
*lp++ = htonl(0x80200000 + XLM_IRQ_NEST); // lwz r1,XLM_IRQ_NEST |
1126 |
|
|
*lp++ = htonl(0x38210001); // addi r1,r1,1 |
1127 |
|
|
*lp++ = htonl(0x90200000 + XLM_IRQ_NEST); // stw r1,XLM_IRQ_NEST |
1128 |
|
|
*lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz r1,XLM_KERNEL_DATA |
1129 |
|
|
*lp++ = htonl(0x90c10018); // stw r6,0x18(r1) |
1130 |
|
|
*lp++ = htonl(0x7cc902a6); // mfctr r6 |
1131 |
|
|
*lp++ = htonl(0x90c10004); // stw r6,$0004(r1) |
1132 |
|
|
*lp++ = htonl(0x80c1065c); // lwz r6,$065c(r1) |
1133 |
|
|
*lp++ = htonl(0x90e6013c); // stw r7,$013c(r6) |
1134 |
|
|
*lp++ = htonl(0x91060144); // stw r8,$0144(r6) |
1135 |
|
|
*lp++ = htonl(0x9126014c); // stw r9,$014c(r6) |
1136 |
|
|
*lp++ = htonl(0x91460154); // stw r10,$0154(r6) |
1137 |
|
|
*lp++ = htonl(0x9166015c); // stw r11,$015c(r6) |
1138 |
|
|
*lp++ = htonl(0x91860164); // stw r12,$0164(r6) |
1139 |
|
|
*lp++ = htonl(0x91a6016c); // stw r13,$016c(r6) |
1140 |
|
|
*lp++ = htonl(0x7da00026); // mfcr r13 |
1141 |
|
|
*lp++ = htonl(0x80e10660); // lwz r7,$0660(r1) |
1142 |
|
|
*lp++ = htonl(0x7d8802a6); // mflr r12 |
1143 |
|
|
*lp++ = htonl(0x50e74001); // rlwimi. r7,r7,8,$80000000 |
1144 |
|
|
*lp++ = htonl(0x814105f4); // lwz r10,0x05f8(r1) |
1145 |
|
|
*lp++ = htonl(0x7d4803a6); // mtlr r10 |
1146 |
|
|
*lp++ = htonl(0x7d8a6378); // mr r10,r12 |
1147 |
|
|
*lp++ = htonl(0x3d600002); // lis r11,0x0002 |
1148 |
|
|
*lp++ = htonl(0x616bf072); // ori r11,r11,0xf072 (MSR) |
1149 |
|
|
*lp++ = htonl(0x50e7deb4); // rlwimi r7,r7,27,$00000020 |
1150 |
|
|
*lp = htonl(0x4e800020); // blr |
1151 |
|
|
|
1152 |
|
|
// Extra routine for FE0A opcode (QuickDraw 3D needs this) |
1153 |
|
|
lp = (uint32 *)(ROM_BASE + 0x36fc00); |
1154 |
|
|
*lp++ = htonl(0x7c2903a6); // mtctr r1 |
1155 |
|
|
*lp++ = htonl(0x80200000 + XLM_IRQ_NEST); // lwz r1,XLM_IRQ_NEST |
1156 |
|
|
*lp++ = htonl(0x38210001); // addi r1,r1,1 |
1157 |
|
|
*lp++ = htonl(0x90200000 + XLM_IRQ_NEST); // stw r1,XLM_IRQ_NEST |
1158 |
|
|
*lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz r1,XLM_KERNEL_DATA |
1159 |
|
|
*lp++ = htonl(0x90c10018); // stw r6,0x18(r1) |
1160 |
|
|
*lp++ = htonl(0x7cc902a6); // mfctr r6 |
1161 |
|
|
*lp++ = htonl(0x90c10004); // stw r6,$0004(r1) |
1162 |
|
|
*lp++ = htonl(0x80c1065c); // lwz r6,$065c(r1) |
1163 |
|
|
*lp++ = htonl(0x90e6013c); // stw r7,$013c(r6) |
1164 |
|
|
*lp++ = htonl(0x91060144); // stw r8,$0144(r6) |
1165 |
|
|
*lp++ = htonl(0x9126014c); // stw r9,$014c(r6) |
1166 |
|
|
*lp++ = htonl(0x91460154); // stw r10,$0154(r6) |
1167 |
|
|
*lp++ = htonl(0x9166015c); // stw r11,$015c(r6) |
1168 |
|
|
*lp++ = htonl(0x91860164); // stw r12,$0164(r6) |
1169 |
|
|
*lp++ = htonl(0x91a6016c); // stw r13,$016c(r6) |
1170 |
|
|
*lp++ = htonl(0x7da00026); // mfcr r13 |
1171 |
|
|
*lp++ = htonl(0x80e10660); // lwz r7,$0660(r1) |
1172 |
|
|
*lp++ = htonl(0x7d8802a6); // mflr r12 |
1173 |
|
|
*lp++ = htonl(0x50e74001); // rlwimi. r7,r7,8,$80000000 |
1174 |
|
|
*lp++ = htonl(0x814105f4); // lwz r10,0x05fc(r1) |
1175 |
|
|
*lp++ = htonl(0x7d4803a6); // mtlr r10 |
1176 |
|
|
*lp++ = htonl(0x7d8a6378); // mr r10,r12 |
1177 |
|
|
*lp++ = htonl(0x3d600002); // lis r11,0x0002 |
1178 |
|
|
*lp++ = htonl(0x616bf072); // ori r11,r11,0xf072 (MSR) |
1179 |
|
|
*lp++ = htonl(0x50e7deb4); // rlwimi r7,r7,27,$00000020 |
1180 |
|
|
*lp = htonl(0x4e800020); // blr |
1181 |
|
|
|
1182 |
|
|
// Patch DR emulator to jump to right address when an interrupt occurs |
1183 |
|
|
lp = (uint32 *)(ROM_BASE + 0x370000); |
1184 |
|
|
while (lp < (uint32 *)(ROM_BASE + 0x380000)) { |
1185 |
|
|
if (ntohl(*lp) == 0x4ca80020) // bclr 5,8 |
1186 |
|
|
goto dr_found; |
1187 |
|
|
lp++; |
1188 |
|
|
} |
1189 |
|
|
D(bug("DR emulator patch location not found\n")); |
1190 |
|
|
return false; |
1191 |
|
|
dr_found: |
1192 |
|
|
lp++; |
1193 |
|
|
*lp = htonl(0x48000000 + 0xf000 - (((uint32)lp - ROM_BASE) & 0xffff)); // b DR_CACHE_BASE+0x1f000 |
1194 |
|
|
lp = (uint32 *)(ROM_BASE + 0x37f000); |
1195 |
|
|
*lp++ = htonl(0x3c000000 + ((ROM_BASE + 0x46d0a4) >> 16)); // lis r0,xxx |
1196 |
|
|
*lp++ = htonl(0x60000000 + ((ROM_BASE + 0x46d0a4) & 0xffff)); // ori r0,r0,xxx |
1197 |
|
|
*lp++ = htonl(0x7c0903a6); // mtctr r0 |
1198 |
|
|
*lp = htonl(POWERPC_BCTR); // bctr |
1199 |
|
|
return true; |
1200 |
|
|
} |
1201 |
|
|
|
1202 |
|
|
|
1203 |
|
|
/* |
1204 |
|
|
* Nanokernel patches |
1205 |
|
|
*/ |
1206 |
|
|
|
1207 |
|
|
static bool patch_nanokernel(void) |
1208 |
|
|
{ |
1209 |
|
|
uint32 *lp; |
1210 |
|
|
|
1211 |
|
|
// Patch Mixed Mode trap |
1212 |
|
|
lp = (uint32 *)(ROM_BASE + 0x313c90); // Don't translate virtual->physical |
1213 |
|
|
while (ntohl(*lp) != 0x3ba10320) lp++; |
1214 |
|
|
lp++; |
1215 |
|
|
*lp++ = htonl(0x7f7fdb78); // mr r31,r27 |
1216 |
|
|
lp++; |
1217 |
|
|
*lp = htonl(POWERPC_NOP); |
1218 |
|
|
|
1219 |
|
|
lp = (uint32 *)(ROM_BASE + 0x313c3c); // Don't activate PPC exception table |
1220 |
|
|
while (ntohl(*lp) != 0x39010420) lp++; |
1221 |
|
|
*lp++ = htonl(0x39000000 + MODE_NATIVE); // li r8,MODE_NATIVE |
1222 |
|
|
*lp = htonl(0x91000000 + XLM_RUN_MODE); // stw r8,XLM_RUN_MODE |
1223 |
|
|
|
1224 |
|
|
lp = (uint32 *)(ROM_BASE + 0x312e88); // Don't modify MSR to turn on FPU |
1225 |
|
|
while (ntohl(*lp) != 0x556b04e2) lp++; |
1226 |
|
|
lp -= 4; |
1227 |
|
|
*lp++ = htonl(POWERPC_NOP); |
1228 |
|
|
lp++; |
1229 |
|
|
*lp++ = htonl(POWERPC_NOP); |
1230 |
|
|
lp++; |
1231 |
|
|
*lp = htonl(POWERPC_NOP); |
1232 |
|
|
|
1233 |
|
|
lp = (uint32 *)(ROM_BASE + 0x312b3c); // Always save FPU state |
1234 |
|
|
while (ntohl(*lp) != 0x81010668) lp++; |
1235 |
|
|
lp--; |
1236 |
|
|
*lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff)); // bl 0x00312e88 |
1237 |
|
|
|
1238 |
|
|
lp = (uint32 *)(ROM_BASE + 0x312b44); // Don't read DEC |
1239 |
|
|
while (ntohl(*lp) != 0x7ff602a6) lp++; |
1240 |
|
|
*lp = htonl(0x3be00000); // li r31,0 |
1241 |
|
|
|
1242 |
|
|
lp = (uint32 *)(ROM_BASE + 0x312b50); // Don't write DEC |
1243 |
|
|
while (ntohl(*lp) != 0x7d1603a6) lp++; |
1244 |
|
|
#if 1 |
1245 |
|
|
*lp++ = htonl(POWERPC_NOP); |
1246 |
|
|
*lp = htonl(POWERPC_NOP); |
1247 |
|
|
#else |
1248 |
|
|
*lp++ = htonl(0x39000040); // li r8,0x40 |
1249 |
|
|
*lp = htonl(0x990600e4); // stb r8,0xe4(r6) |
1250 |
|
|
#endif |
1251 |
|
|
|
1252 |
|
|
lp = (uint32 *)(ROM_BASE + 0x312b9c); // Always restore FPU state |
1253 |
|
|
while (ntohl(*lp) != 0x7c00092d) lp++; |
1254 |
|
|
lp--; |
1255 |
|
|
*lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff)); // bl 0x00312ddc |
1256 |
|
|
|
1257 |
|
|
lp = (uint32 *)(ROM_BASE + 0x312a68); // Don't activate 68k exception table |
1258 |
|
|
while (ntohl(*lp) != 0x39010360) lp++; |
1259 |
|
|
*lp++ = htonl(0x39000000 + MODE_68K); // li r8,MODE_68K |
1260 |
|
|
*lp = htonl(0x91000000 + XLM_RUN_MODE); // stw r8,XLM_RUN_MODE |
1261 |
|
|
|
1262 |
|
|
// Patch 68k emulator trap routine |
1263 |
|
|
lp = (uint32 *)(ROM_BASE + 0x312994); // Always restore FPU state |
1264 |
|
|
while (ntohl(*lp) != 0x39260040) lp++; |
1265 |
|
|
lp--; |
1266 |
|
|
*lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff)); // bl 0x00312dd4 |
1267 |
|
|
|
1268 |
|
|
lp = (uint32 *)(ROM_BASE + 0x312dd8); // Don't modify MSR to turn on FPU |
1269 |
|
|
while (ntohl(*lp) != 0x810600e4) lp++; |
1270 |
|
|
lp--; |
1271 |
|
|
*lp++ = htonl(POWERPC_NOP); |
1272 |
|
|
lp += 2; |
1273 |
|
|
*lp++ = htonl(POWERPC_NOP); |
1274 |
|
|
lp++; |
1275 |
|
|
*lp++ = htonl(POWERPC_NOP); |
1276 |
|
|
*lp++ = htonl(POWERPC_NOP); |
1277 |
|
|
*lp = htonl(POWERPC_NOP); |
1278 |
|
|
|
1279 |
|
|
// Patch trap return routine |
1280 |
|
|
lp = (uint32 *)(ROM_BASE + 0x312c20); |
1281 |
|
|
while (ntohl(*lp) != 0x7d5a03a6) lp++; |
1282 |
|
|
*lp++ = htonl(0x7d4903a6); // mtctr r10 |
1283 |
|
|
*lp++ = htonl(0x7daff120); // mtcr r13 |
1284 |
|
|
*lp = htonl(0x48000000 + 0x8000 - (((uint32)lp - ROM_BASE) & 0xffff)); // b ROM_BASE+0x318000 |
1285 |
|
|
uint32 xlp = ((uint32)(lp+1) - ROM_BASE) & 0xffff; |
1286 |
|
|
|
1287 |
|
|
lp = (uint32 *)(ROM_BASE + 0x312c50); // Replace rfi |
1288 |
|
|
while (ntohl(*lp) != 0x4c000064) lp++; |
1289 |
|
|
*lp = htonl(POWERPC_BCTR); |
1290 |
|
|
|
1291 |
|
|
lp = (uint32 *)(ROM_BASE + 0x318000); |
1292 |
|
|
*lp++ = htonl(0x81400000 + XLM_IRQ_NEST); // lwz r10,XLM_IRQ_NEST |
1293 |
|
|
*lp++ = htonl(0x394affff); // subi r10,r10,1 |
1294 |
|
|
*lp++ = htonl(0x91400000 + XLM_IRQ_NEST); // stw r10,XLM_IRQ_NEST |
1295 |
|
|
*lp = htonl(0x48000000 + ((xlp - 0x800c) & 0x03fffffc)); // b ROM_BASE+0x312c2c |
1296 |
|
|
/* |
1297 |
|
|
// Disable FE0A/FE06 opcodes |
1298 |
|
|
lp = (uint32 *)(ROM_BASE + 0x3144ac); |
1299 |
|
|
*lp++ = htonl(POWERPC_NOP); |
1300 |
|
|
*lp += 8; |
1301 |
|
|
*/ |
1302 |
|
|
return true; |
1303 |
|
|
} |
1304 |
|
|
|
1305 |
|
|
|
1306 |
|
|
/* |
1307 |
|
|
* 68k boot routine patches |
1308 |
|
|
*/ |
1309 |
|
|
|
1310 |
|
|
static bool patch_68k(void) |
1311 |
|
|
{ |
1312 |
|
|
uint32 *lp; |
1313 |
|
|
uint16 *wp; |
1314 |
|
|
uint8 *bp; |
1315 |
|
|
uint32 base; |
1316 |
|
|
|
1317 |
|
|
// Remove 68k RESET instruction |
1318 |
|
|
static const uint8 reset_dat[] = {0x4e, 0x70}; |
1319 |
|
|
if ((base = find_rom_data(0xc8, 0x120, reset_dat, sizeof(reset_dat))) == 0) return false; |
1320 |
|
|
D(bug("reset %08lx\n", base)); |
1321 |
|
|
wp = (uint16 *)(ROM_BASE + base); |
1322 |
|
|
*wp = htons(M68K_NOP); |
1323 |
|
|
|
1324 |
|
|
// Fake reading PowerMac ID (via Universal) |
1325 |
|
|
static const uint8 powermac_id_dat[] = {0x45, 0xf9, 0x5f, 0xff, 0xff, 0xfc, 0x20, 0x12, 0x72, 0x00}; |
1326 |
|
|
if ((base = find_rom_data(0xe000, 0x15000, powermac_id_dat, sizeof(powermac_id_dat))) == 0) return false; |
1327 |
|
|
D(bug("powermac_id %08lx\n", base)); |
1328 |
|
|
wp = (uint16 *)(ROM_BASE + base); |
1329 |
|
|
*wp++ = htons(0x203c); // move.l #id,d0 |
1330 |
|
|
*wp++ = htons(0); |
1331 |
|
|
// if (ROMType == ROMTYPE_NEWWORLD) |
1332 |
|
|
// *wp++ = htons(0x3035); // (PowerMac 9500 ID) |
1333 |
|
|
// else |
1334 |
|
|
*wp++ = htons(0x3020); // (PowerMac 9500 ID) |
1335 |
|
|
*wp++ = htons(0xb040); // cmp.w d0,d0 |
1336 |
|
|
*wp = htons(0x4ed6); // jmp (a6) |
1337 |
|
|
|
1338 |
|
|
// Patch UniversalInfo |
1339 |
|
|
if (ROMType == ROMTYPE_NEWWORLD) { |
1340 |
|
|
static const uint8 univ_info_dat[] = {0x3f, 0xff, 0x04, 0x00}; |
1341 |
|
|
if ((base = find_rom_data(0x14000, 0x16000, univ_info_dat, sizeof(univ_info_dat))) == 0) return false; |
1342 |
|
|
D(bug("universal_info %08lx\n", base)); |
1343 |
|
|
lp = (uint32 *)(ROM_BASE + base - 0x14); |
1344 |
|
|
lp[0x00 >> 2] = htonl(ADDR_MAP_PATCH_SPACE - (base - 0x14)); |
1345 |
|
|
lp[0x10 >> 2] = htonl(0xcc003d11); // Make it like the PowerMac 9500 UniversalInfo |
1346 |
|
|
lp[0x14 >> 2] = htonl(0x3fff0401); |
1347 |
|
|
lp[0x18 >> 2] = htonl(0x0300001c); |
1348 |
|
|
lp[0x1c >> 2] = htonl(0x000108c4); |
1349 |
|
|
lp[0x24 >> 2] = htonl(0xc301bf26); |
1350 |
|
|
lp[0x28 >> 2] = htonl(0x00000861); |
1351 |
|
|
lp[0x58 >> 2] = htonl(0x30200000); |
1352 |
|
|
lp[0x60 >> 2] = htonl(0x0000003d); |
1353 |
|
|
} else if (ROMType == ROMTYPE_ZANZIBAR) { |
1354 |
|
|
base = 0x12b70; |
1355 |
|
|
lp = (uint32 *)(ROM_BASE + base - 0x14); |
1356 |
|
|
lp[0x00 >> 2] = htonl(ADDR_MAP_PATCH_SPACE - (base - 0x14)); |
1357 |
|
|
lp[0x10 >> 2] = htonl(0xcc003d11); // Make it like the PowerMac 9500 UniversalInfo |
1358 |
|
|
lp[0x14 >> 2] = htonl(0x3fff0401); |
1359 |
|
|
lp[0x18 >> 2] = htonl(0x0300001c); |
1360 |
|
|
lp[0x1c >> 2] = htonl(0x000108c4); |
1361 |
|
|
lp[0x24 >> 2] = htonl(0xc301bf26); |
1362 |
|
|
lp[0x28 >> 2] = htonl(0x00000861); |
1363 |
|
|
lp[0x58 >> 2] = htonl(0x30200000); |
1364 |
|
|
lp[0x60 >> 2] = htonl(0x0000003d); |
1365 |
|
|
} |
1366 |
|
|
|
1367 |
|
|
// Construct AddrMap for NewWorld ROM |
1368 |
|
|
if (ROMType == ROMTYPE_NEWWORLD || ROMType == ROMTYPE_ZANZIBAR) { |
1369 |
|
|
lp = (uint32 *)(ROM_BASE + ADDR_MAP_PATCH_SPACE); |
1370 |
|
|
memset(lp - 10, 0, 0x128); |
1371 |
|
|
lp[-10] = htonl(0x0300001c); |
1372 |
|
|
lp[-9] = htonl(0x000108c4); |
1373 |
|
|
lp[-4] = htonl(0x00300000); |
1374 |
|
|
lp[-2] = htonl(0x11010000); |
1375 |
|
|
lp[-1] = htonl(0xf8000000); |
1376 |
|
|
lp[0] = htonl(0xffc00000); |
1377 |
|
|
lp[2] = htonl(0xf3016000); |
1378 |
|
|
lp[3] = htonl(0xf3012000); |
1379 |
|
|
lp[4] = htonl(0xf3012000); |
1380 |
|
|
lp[24] = htonl(0xf3018000); |
1381 |
|
|
lp[25] = htonl(0xf3010000); |
1382 |
|
|
lp[34] = htonl(0xf3011000); |
1383 |
|
|
lp[38] = htonl(0xf3015000); |
1384 |
|
|
lp[39] = htonl(0xf3014000); |
1385 |
|
|
lp[43] = htonl(0xf3000000); |
1386 |
|
|
lp[48] = htonl(0xf8000000); |
1387 |
|
|
} |
1388 |
|
|
|
1389 |
|
|
// Don't initialize VIA (via Universal) |
1390 |
|
|
static const uint8 via_init_dat[] = {0x08, 0x00, 0x00, 0x02, 0x67, 0x00, 0x00, 0x2c, 0x24, 0x68, 0x00, 0x08}; |
1391 |
|
|
if ((base = find_rom_data(0xe000, 0x15000, via_init_dat, sizeof(via_init_dat))) == 0) return false; |
1392 |
|
|
D(bug("via_init %08lx\n", base)); |
1393 |
|
|
wp = (uint16 *)(ROM_BASE + base + 4); |
1394 |
|
|
*wp = htons(0x6000); // bra |
1395 |
|
|
|
1396 |
|
|
static const uint8 via_init2_dat[] = {0x24, 0x68, 0x00, 0x08, 0x00, 0x12, 0x00, 0x30, 0x4e, 0x71}; |
1397 |
|
|
if ((base = find_rom_data(0xa000, 0x10000, via_init2_dat, sizeof(via_init2_dat))) == 0) return false; |
1398 |
|
|
D(bug("via_init2 %08lx\n", base)); |
1399 |
|
|
wp = (uint16 *)(ROM_BASE + base); |
1400 |
|
|
*wp = htons(0x4ed6); // jmp (a6) |
1401 |
|
|
|
1402 |
|
|
static const uint8 via_init3_dat[] = {0x22, 0x68, 0x00, 0x08, 0x28, 0x3c, 0x20, 0x00, 0x01, 0x00}; |
1403 |
|
|
if ((base = find_rom_data(0xa000, 0x10000, via_init3_dat, sizeof(via_init3_dat))) == 0) return false; |
1404 |
|
|
D(bug("via_init3 %08lx\n", base)); |
1405 |
|
|
wp = (uint16 *)(ROM_BASE + base); |
1406 |
|
|
*wp = htons(0x4ed6); // jmp (a6) |
1407 |
|
|
|
1408 |
|
|
// Don't RunDiags, get BootGlobs pointer directly |
1409 |
|
|
if (ROMType == ROMTYPE_NEWWORLD) { |
1410 |
|
|
static const uint8 run_diags_dat[] = {0x60, 0xff, 0x00, 0x0c}; |
1411 |
|
|
if ((base = find_rom_data(0x110, 0x128, run_diags_dat, sizeof(run_diags_dat))) == 0) return false; |
1412 |
|
|
D(bug("run_diags %08lx\n", base)); |
1413 |
|
|
wp = (uint16 *)(ROM_BASE + base); |
1414 |
|
|
*wp++ = htons(0x4df9); // lea xxx,a6 |
1415 |
|
|
*wp++ = htons((RAMBase + RAMSize - 0x1c) >> 16); |
1416 |
|
|
*wp = htons((RAMBase + RAMSize - 0x1c) & 0xffff); |
1417 |
|
|
} else { |
1418 |
|
|
static const uint8 run_diags_dat[] = {0x74, 0x00, 0x2f, 0x0e}; |
1419 |
|
|
if ((base = find_rom_data(0xd0, 0xf0, run_diags_dat, sizeof(run_diags_dat))) == 0) return false; |
1420 |
|
|
D(bug("run_diags %08lx\n", base)); |
1421 |
|
|
wp = (uint16 *)(ROM_BASE + base - 6); |
1422 |
|
|
*wp++ = htons(0x4df9); // lea xxx,a6 |
1423 |
|
|
*wp++ = htons((RAMBase + RAMSize - 0x1c) >> 16); |
1424 |
|
|
*wp = htons((RAMBase + RAMSize - 0x1c) & 0xffff); |
1425 |
|
|
} |
1426 |
|
|
|
1427 |
|
|
// Replace NVRAM routines |
1428 |
|
|
static const uint8 nvram1_dat[] = {0x48, 0xe7, 0x01, 0x0e, 0x24, 0x68, 0x00, 0x08, 0x08, 0x83, 0x00, 0x1f}; |
1429 |
|
|
if ((base = find_rom_data(0x7000, 0xc000, nvram1_dat, sizeof(nvram1_dat))) == 0) return false; |
1430 |
|
|
D(bug("nvram1 %08lx\n", base)); |
1431 |
|
|
wp = (uint16 *)(ROM_BASE + base); |
1432 |
|
|
*wp++ = htons(M68K_EMUL_OP_XPRAM1); |
1433 |
|
|
*wp = htons(M68K_RTS); |
1434 |
|
|
|
1435 |
|
|
if (ROMType == ROMTYPE_NEWWORLD) { |
1436 |
|
|
static const uint8 nvram2_dat[] = {0x48, 0xe7, 0x1c, 0xe0, 0x4f, 0xef, 0xff, 0xb4}; |
1437 |
|
|
if ((base = find_rom_data(0xa000, 0xd000, nvram2_dat, sizeof(nvram2_dat))) == 0) return false; |
1438 |
|
|
D(bug("nvram2 %08lx\n", base)); |
1439 |
|
|
wp = (uint16 *)(ROM_BASE + base); |
1440 |
|
|
*wp++ = htons(M68K_EMUL_OP_XPRAM2); |
1441 |
|
|
*wp = htons(0x4ed3); // jmp (a3) |
1442 |
|
|
|
1443 |
|
|
static const uint8 nvram3_dat[] = {0x48, 0xe7, 0xdc, 0xe0, 0x4f, 0xef, 0xff, 0xb4}; |
1444 |
|
|
if ((base = find_rom_data(0xa000, 0xd000, nvram3_dat, sizeof(nvram3_dat))) == 0) return false; |
1445 |
|
|
D(bug("nvram3 %08lx\n", base)); |
1446 |
|
|
wp = (uint16 *)(ROM_BASE + base); |
1447 |
|
|
*wp++ = htons(M68K_EMUL_OP_XPRAM3); |
1448 |
|
|
*wp = htons(0x4ed3); // jmp (a3) |
1449 |
|
|
|
1450 |
|
|
static const uint8 nvram4_dat[] = {0x4e, 0x56, 0xff, 0xa8, 0x48, 0xe7, 0x1f, 0x38, 0x16, 0x2e, 0x00, 0x13}; |
1451 |
|
|
if ((base = find_rom_data(0xa000, 0xd000, nvram4_dat, sizeof(nvram4_dat))) == 0) return false; |
1452 |
|
|
D(bug("nvram4 %08lx\n", base)); |
1453 |
|
|
wp = (uint16 *)(ROM_BASE + base + 16); |
1454 |
|
|
*wp++ = htons(0x1a2e); // move.b ($000f,a6),d5 |
1455 |
|
|
*wp++ = htons(0x000f); |
1456 |
|
|
*wp++ = htons(M68K_EMUL_OP_NVRAM3); |
1457 |
|
|
*wp++ = htons(0x4cee); // movem.l ($ff88,a6),d3-d7/a2-a4 |
1458 |
|
|
*wp++ = htons(0x1cf8); |
1459 |
|
|
*wp++ = htons(0xff88); |
1460 |
|
|
*wp++ = htons(0x4e5e); // unlk a6 |
1461 |
|
|
*wp = htons(M68K_RTS); |
1462 |
|
|
|
1463 |
|
|
static const uint8 nvram5_dat[] = {0x0c, 0x80, 0x03, 0x00, 0x00, 0x00, 0x66, 0x0a, 0x70, 0x00, 0x21, 0xf8, 0x02, 0x0c, 0x01, 0xe4}; |
1464 |
|
|
if ((base = find_rom_data(0xa000, 0xd000, nvram5_dat, sizeof(nvram5_dat))) == 0) return false; |
1465 |
|
|
D(bug("nvram5 %08lx\n", base)); |
1466 |
|
|
wp = (uint16 *)(ROM_BASE + base + 6); |
1467 |
|
|
*wp = htons(M68K_NOP); |
1468 |
|
|
|
1469 |
|
|
static const uint8 nvram6_dat[] = {0x2f, 0x0a, 0x24, 0x48, 0x4f, 0xef, 0xff, 0xa0, 0x20, 0x0f}; |
1470 |
|
|
if ((base = find_rom_data(0x9000, 0xb000, nvram6_dat, sizeof(nvram6_dat))) == 0) return false; |
1471 |
|
|
D(bug("nvram6 %08lx\n", base)); |
1472 |
|
|
wp = (uint16 *)(ROM_BASE + base); |
1473 |
|
|
*wp++ = htons(0x7000); // moveq #0,d0 |
1474 |
|
|
*wp++ = htons(0x2080); // move.l d0,(a0) |
1475 |
|
|
*wp++ = htons(0x4228); // clr.b 4(a0) |
1476 |
|
|
*wp++ = htons(0x0004); |
1477 |
|
|
*wp = htons(M68K_RTS); |
1478 |
|
|
|
1479 |
|
|
static const uint8 nvram7_dat[] = {0x42, 0x2a, 0x00, 0x04, 0x4f, 0xef, 0x00, 0x60, 0x24, 0x5f, 0x4e, 0x75, 0x4f, 0xef, 0xff, 0xa0, 0x20, 0x0f}; |
1480 |
|
|
base = find_rom_data(0x9000, 0xb000, nvram7_dat, sizeof(nvram7_dat)); |
1481 |
|
|
if (base) { |
1482 |
|
|
D(bug("nvram7 %08lx\n", base)); |
1483 |
|
|
wp = (uint16 *)(ROM_BASE + base + 12); |
1484 |
|
|
*wp = htons(M68K_RTS); |
1485 |
|
|
} |
1486 |
|
|
} else { |
1487 |
|
|
static const uint8 nvram2_dat[] = {0x4e, 0xd6, 0x06, 0x41, 0x13, 0x00}; |
1488 |
|
|
if ((base = find_rom_data(0x7000, 0xb000, nvram2_dat, sizeof(nvram2_dat))) == 0) return false; |
1489 |
|
|
D(bug("nvram2 %08lx\n", base)); |
1490 |
|
|
wp = (uint16 *)(ROM_BASE + base + 2); |
1491 |
|
|
*wp++ = htons(M68K_EMUL_OP_XPRAM2); |
1492 |
|
|
*wp = htons(0x4ed3); // jmp (a3) |
1493 |
|
|
|
1494 |
|
|
static const uint32 nvram3_loc[] = {0x582f0, 0xa0a0, 0x7e50, 0xa1d0, 0}; |
1495 |
|
|
wp = (uint16 *)(ROM_BASE + nvram3_loc[ROMType]); |
1496 |
|
|
*wp++ = htons(0x202f); // move.l 4(sp),d0 |
1497 |
|
|
*wp++ = htons(0x0004); |
1498 |
|
|
*wp++ = htons(M68K_EMUL_OP_NVRAM1); |
1499 |
|
|
if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_GAZELLE) |
1500 |
|
|
*wp = htons(M68K_RTS); |
1501 |
|
|
else { |
1502 |
|
|
*wp++ = htons(0x1f40); // move.b d0,8(sp) |
1503 |
|
|
*wp++ = htons(0x0008); |
1504 |
|
|
*wp++ = htons(0x4e74); // rtd #4 |
1505 |
|
|
*wp = htons(0x0004); |
1506 |
|
|
} |
1507 |
|
|
|
1508 |
|
|
static const uint32 nvram4_loc[] = {0x58460, 0xa0f0, 0x7f40, 0xa220, 0}; |
1509 |
|
|
wp = (uint16 *)(ROM_BASE + nvram4_loc[ROMType]); |
1510 |
|
|
if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_GAZELLE) { |
1511 |
|
|
*wp++ = htons(0x202f); // move.l 4(sp),d0 |
1512 |
|
|
*wp++ = htons(0x0004); |
1513 |
|
|
*wp++ = htons(0x122f); // move.b 11(sp),d1 |
1514 |
|
|
*wp++ = htons(0x000b); |
1515 |
|
|
*wp++ = htons(M68K_EMUL_OP_NVRAM2); |
1516 |
|
|
*wp = htons(M68K_RTS); |
1517 |
|
|
} else { |
1518 |
|
|
*wp++ = htons(0x202f); // move.l 6(sp),d0 |
1519 |
|
|
*wp++ = htons(0x0006); |
1520 |
|
|
*wp++ = htons(0x122f); // move.b 4(sp),d1 |
1521 |
|
|
*wp++ = htons(0x0004); |
1522 |
|
|
*wp++ = htons(M68K_EMUL_OP_NVRAM2); |
1523 |
|
|
*wp++ = htons(0x4e74); // rtd #6 |
1524 |
|
|
*wp = htons(0x0006); |
1525 |
|
|
} |
1526 |
|
|
} |
1527 |
|
|
|
1528 |
|
|
// Fix MemTop/BootGlobs during system startup |
1529 |
|
|
static const uint8 mem_top_dat[] = {0x2c, 0x6c, 0xff, 0xec, 0x2a, 0x4c, 0xdb, 0xec, 0xff, 0xf4}; |
1530 |
|
|
if ((base = find_rom_data(0x120, 0x180, mem_top_dat, sizeof(mem_top_dat))) == 0) return false; |
1531 |
|
|
D(bug("mem_top %08lx\n", base)); |
1532 |
|
|
wp = (uint16 *)(ROM_BASE + base); |
1533 |
|
|
*wp++ = htons(M68K_EMUL_OP_FIX_MEMTOP); |
1534 |
|
|
*wp = htons(M68K_NOP); |
1535 |
|
|
|
1536 |
|
|
// Don't initialize SCC (via 0x1ac) |
1537 |
|
|
static const uint8 scc_init_dat[] = {0x48, 0xe7, 0x38, 0xfe}; |
1538 |
|
|
if ((base = find_rom_data(0x190, 0x1f0, scc_init_dat, sizeof(scc_init_dat))) == 0) return false; |
1539 |
|
|
D(bug("scc_init %08lx\n", base)); |
1540 |
|
|
wp = (uint16 *)(ROM_BASE + base - 2); |
1541 |
|
|
wp = (uint16 *)(ROM_BASE + ntohs(*wp) + base - 2); |
1542 |
|
|
*wp++ = htons(M68K_EMUL_OP_RESET); |
1543 |
|
|
*wp = htons(M68K_RTS); |
1544 |
|
|
|
1545 |
|
|
// Don't EnableExtCache (via 0x1f6) and don't DisableIntSources(via 0x1fc) |
1546 |
|
|
static const uint8 ext_cache_dat[] = {0x4e, 0x7b, 0x00, 0x02}; |
1547 |
|
|
if ((base = find_rom_data(0x1d0, 0x230, ext_cache_dat, sizeof(ext_cache_dat))) == 0) return false; |
1548 |
|
|
D(bug("ext_cache %08lx\n", base)); |
1549 |
|
|
lp = (uint32 *)(ROM_BASE + base + 6); |
1550 |
|
|
wp = (uint16 *)(ROM_BASE + ntohl(*lp) + base + 6); |
1551 |
|
|
*wp = htons(M68K_RTS); |
1552 |
|
|
lp = (uint32 *)(ROM_BASE + base + 12); |
1553 |
|
|
wp = (uint16 *)(ROM_BASE + ntohl(*lp) + base + 12); |
1554 |
|
|
*wp = htons(M68K_RTS); |
1555 |
|
|
|
1556 |
|
|
// Fake CPU speed test (SetupTimeK) |
1557 |
|
|
static const uint8 timek_dat[] = {0x0c, 0x38, 0x00, 0x04, 0x01, 0x2f, 0x6d, 0x3c}; |
1558 |
|
|
if ((base = find_rom_data(0x400, 0x500, timek_dat, sizeof(timek_dat))) == 0) return false; |
1559 |
|
|
D(bug("timek %08lx\n", base)); |
1560 |
|
|
wp = (uint16 *)(ROM_BASE + base); |
1561 |
|
|
*wp++ = htons(0x31fc); // move.w #xxx,TimeDBRA |
1562 |
|
|
*wp++ = htons(100); |
1563 |
|
|
*wp++ = htons(0x0d00); |
1564 |
|
|
*wp++ = htons(0x31fc); // move.w #xxx,TimeSCCDBRA |
1565 |
|
|
*wp++ = htons(100); |
1566 |
|
|
*wp++ = htons(0x0d02); |
1567 |
|
|
*wp++ = htons(0x31fc); // move.w #xxx,TimeSCSIDBRA |
1568 |
|
|
*wp++ = htons(100); |
1569 |
|
|
*wp++ = htons(0x0b24); |
1570 |
|
|
*wp++ = htons(0x31fc); // move.w #xxx,TimeRAMDBRA |
1571 |
|
|
*wp++ = htons(100); |
1572 |
|
|
*wp++ = htons(0x0cea); |
1573 |
|
|
*wp = htons(M68K_RTS); |
1574 |
|
|
|
1575 |
|
|
// Relocate jump tables ($2000..) |
1576 |
|
|
static const uint8 jump_tab_dat[] = {0x41, 0xfa, 0x00, 0x0e, 0x21, 0xc8, 0x20, 0x10, 0x4e, 0x75}; |
1577 |
|
|
if ((base = find_rom_data(0x3000, 0x6000, jump_tab_dat, sizeof(jump_tab_dat))) == 0) return false; |
1578 |
|
|
D(bug("jump_tab %08lx\n", base)); |
1579 |
|
|
lp = (uint32 *)(ROM_BASE + base + 16); |
1580 |
|
|
for (;;) { |
1581 |
|
|
D(bug(" %08lx\n", (uint32)lp - ROM_BASE)); |
1582 |
|
|
while ((ntohl(*lp) & 0xff000000) == 0xff000000) { |
1583 |
|
|
*lp = htonl((ntohl(*lp) & (ROM_SIZE-1)) + ROM_BASE); |
1584 |
|
|
lp++; |
1585 |
|
|
} |
1586 |
|
|
while (!ntohl(*lp)) lp++; |
1587 |
|
|
if (ntohl(*lp) != 0x41fa000e) |
1588 |
|
|
break; |
1589 |
|
|
lp += 4; |
1590 |
|
|
} |
1591 |
|
|
|
1592 |
|
|
// Create SysZone at start of Mac RAM (SetSysAppZone, via 0x22a) |
1593 |
|
|
static const uint8 sys_zone_dat[] = {0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x40, 0x00}; |
1594 |
|
|
if ((base = find_rom_data(0x600, 0x900, sys_zone_dat, sizeof(sys_zone_dat))) == 0) return false; |
1595 |
|
|
D(bug("sys_zone %08lx\n", base)); |
1596 |
|
|
lp = (uint32 *)(ROM_BASE + base); |
1597 |
|
|
*lp++ = htonl(RAMBase ? RAMBase : 0x3000); |
1598 |
|
|
*lp = htonl(RAMBase ? RAMBase + 0x1800 : 0x4800); |
1599 |
|
|
|
1600 |
|
|
// Set boot stack at RAMBase+4MB and fix logical/physical RAM size (CompBootStack) |
1601 |
|
|
// The RAM size fix must be done after InitMemMgr! |
1602 |
|
|
static const uint8 boot_stack_dat[] = {0x08, 0x38, 0x00, 0x06, 0x24, 0x0b}; |
1603 |
|
|
if ((base = find_rom_data(0x580, 0x800, boot_stack_dat, sizeof(boot_stack_dat))) == 0) return false; |
1604 |
|
|
D(bug("boot_stack %08lx\n", base)); |
1605 |
|
|
wp = (uint16 *)(ROM_BASE + base); |
1606 |
|
|
*wp++ = htons(0x207c); // move.l #RAMBase+0x3ffffe,a0 |
1607 |
|
|
*wp++ = htons((RAMBase + 0x3ffffe) >> 16); |
1608 |
|
|
*wp++ = htons((RAMBase + 0x3ffffe) & 0xffff); |
1609 |
|
|
*wp++ = htons(M68K_EMUL_OP_FIX_MEMSIZE); |
1610 |
|
|
*wp = htons(M68K_RTS); |
1611 |
|
|
|
1612 |
|
|
// Get PowerPC page size (InitVMemMgr, via 0x240) |
1613 |
|
|
static const uint8 page_size_dat[] = {0x20, 0x30, 0x81, 0xf2, 0x5f, 0xff, 0xef, 0xd8, 0x00, 0x10}; |
1614 |
|
|
if ((base = find_rom_data(0xb000, 0x12000, page_size_dat, sizeof(page_size_dat))) == 0) return false; |
1615 |
|
|
D(bug("page_size %08lx\n", base)); |
1616 |
|
|
wp = (uint16 *)(ROM_BASE + base); |
1617 |
|
|
*wp++ = htons(0x203c); // move.l #$1000,d0 |
1618 |
|
|
*wp++ = htons(0); |
1619 |
|
|
*wp++ = htons(0x1000); |
1620 |
|
|
*wp++ = htons(M68K_NOP); |
1621 |
|
|
*wp = htons(M68K_NOP); |
1622 |
|
|
|
1623 |
|
|
// Gestalt PowerPC page size, RAM size (InitGestalt, via 0x25c) |
1624 |
|
|
static const uint8 page_size2_dat[] = {0x26, 0x79, 0x5f, 0xff, 0xef, 0xd8, 0x25, 0x6b, 0x00, 0x10, 0x00, 0x1e}; |
1625 |
|
|
if ((base = find_rom_data(0x50000, 0x70000, page_size2_dat, sizeof(page_size2_dat))) == 0) return false; |
1626 |
|
|
D(bug("page_size2 %08lx\n", base)); |
1627 |
|
|
wp = (uint16 *)(ROM_BASE + base); |
1628 |
|
|
*wp++ = htons(0x257c); // move.l #$1000,$1e(a2) |
1629 |
|
|
*wp++ = htons(0); |
1630 |
|
|
*wp++ = htons(0x1000); |
1631 |
|
|
*wp++ = htons(0x001e); |
1632 |
|
|
*wp++ = htons(0x157c); // move.b #PVR,$1d(a2) |
1633 |
|
|
*wp++ = htons(PVR >> 16); |
1634 |
|
|
*wp++ = htons(0x001d); |
1635 |
|
|
*wp++ = htons(0x263c); // move.l #RAMSize,d3 |
1636 |
|
|
*wp++ = htons(RAMSize >> 16); |
1637 |
|
|
*wp++ = htons(RAMSize & 0xffff); |
1638 |
|
|
*wp++ = htons(M68K_NOP); |
1639 |
|
|
*wp++ = htons(M68K_NOP); |
1640 |
|
|
*wp = htons(M68K_NOP); |
1641 |
|
|
if (ROMType == ROMTYPE_NEWWORLD) |
1642 |
|
|
wp = (uint16 *)(ROM_BASE + base + 0x4a); |
1643 |
|
|
else |
1644 |
|
|
wp = (uint16 *)(ROM_BASE + base + 0x28); |
1645 |
|
|
*wp++ = htons(M68K_NOP); |
1646 |
|
|
*wp = htons(M68K_NOP); |
1647 |
|
|
|
1648 |
|
|
// Gestalt CPU/bus clock speed (InitGestalt, via 0x25c) |
1649 |
|
|
if (ROMType == ROMTYPE_ZANZIBAR) { |
1650 |
|
|
wp = (uint16 *)(ROM_BASE + 0x5d87a); |
1651 |
|
|
*wp++ = htons(0x203c); // move.l #Hz,d0 |
1652 |
|
|
*wp++ = htons(BusClockSpeed >> 16); |
1653 |
|
|
*wp++ = htons(BusClockSpeed & 0xffff); |
1654 |
|
|
*wp++ = htons(M68K_NOP); |
1655 |
|
|
*wp = htons(M68K_NOP); |
1656 |
|
|
wp = (uint16 *)(ROM_BASE + 0x5d888); |
1657 |
|
|
*wp++ = htons(0x203c); // move.l #Hz,d0 |
1658 |
|
|
*wp++ = htons(CPUClockSpeed >> 16); |
1659 |
|
|
*wp++ = htons(CPUClockSpeed & 0xffff); |
1660 |
|
|
*wp++ = htons(M68K_NOP); |
1661 |
|
|
*wp = htons(M68K_NOP); |
1662 |
|
|
} |
1663 |
|
|
|
1664 |
|
|
// Don't write to GC interrupt mask register (via 0x262) |
1665 |
|
|
if (ROMType != ROMTYPE_NEWWORLD) { |
1666 |
|
|
static const uint8 gc_mask_dat[] = {0x83, 0xa8, 0x00, 0x24, 0x4e, 0x71}; |
1667 |
|
|
if ((base = find_rom_data(0x13000, 0x20000, gc_mask_dat, sizeof(gc_mask_dat))) == 0) return false; |
1668 |
|
|
D(bug("gc_mask %08lx\n", base)); |
1669 |
|
|
wp = (uint16 *)(ROM_BASE + base); |
1670 |
|
|
*wp++ = htons(M68K_NOP); |
1671 |
|
|
*wp = htons(M68K_NOP); |
1672 |
|
|
wp = (uint16 *)(ROM_BASE + base + 0x40); |
1673 |
|
|
*wp++ = htons(M68K_NOP); |
1674 |
|
|
*wp = htons(M68K_NOP); |
1675 |
|
|
wp = (uint16 *)(ROM_BASE + base + 0x78); |
1676 |
|
|
*wp++ = htons(M68K_NOP); |
1677 |
|
|
*wp = htons(M68K_NOP); |
1678 |
|
|
wp = (uint16 *)(ROM_BASE + base + 0x96); |
1679 |
|
|
*wp++ = htons(M68K_NOP); |
1680 |
|
|
*wp = htons(M68K_NOP); |
1681 |
|
|
|
1682 |
|
|
static const uint8 gc_mask2_dat[] = {0x02, 0xa8, 0x00, 0x00, 0x00, 0x80, 0x00, 0x24}; |
1683 |
|
|
if ((base = find_rom_data(0x13000, 0x20000, gc_mask2_dat, sizeof(gc_mask2_dat))) == 0) return false; |
1684 |
|
|
D(bug("gc_mask2 %08lx\n", base)); |
1685 |
|
|
wp = (uint16 *)(ROM_BASE + base); |
1686 |
|
|
for (int i=0; i<5; i++) { |
1687 |
|
|
*wp++ = htons(M68K_NOP); |
1688 |
|
|
*wp++ = htons(M68K_NOP); |
1689 |
|
|
*wp++ = htons(M68K_NOP); |
1690 |
|
|
*wp++ = htons(M68K_NOP); |
1691 |
|
|
wp += 2; |
1692 |
|
|
} |
1693 |
|
|
if (ROMType == ROMTYPE_ZANZIBAR) { |
1694 |
|
|
for (int i=0; i<6; i++) { |
1695 |
|
|
*wp++ = htons(M68K_NOP); |
1696 |
|
|
*wp++ = htons(M68K_NOP); |
1697 |
|
|
*wp++ = htons(M68K_NOP); |
1698 |
|
|
*wp++ = htons(M68K_NOP); |
1699 |
|
|
wp += 2; |
1700 |
|
|
} |
1701 |
|
|
} |
1702 |
|
|
} |
1703 |
|
|
|
1704 |
|
|
// Don't initialize Cuda (via 0x274) |
1705 |
|
|
static const uint8 cuda_init_dat[] = {0x08, 0xa9, 0x00, 0x04, 0x16, 0x00, 0x4e, 0x71, 0x13, 0x7c, 0x00, 0x84, 0x1c, 0x00, 0x4e, 0x71}; |
1706 |
|
|
if ((base = find_rom_data(0xa000, 0x12000, cuda_init_dat, sizeof(cuda_init_dat))) == 0) return false; |
1707 |
|
|
D(bug("cuda_init %08lx\n", base)); |
1708 |
|
|
wp = (uint16 *)(ROM_BASE + base); |
1709 |
|
|
*wp++ = htons(M68K_NOP); |
1710 |
|
|
*wp++ = htons(M68K_NOP); |
1711 |
|
|
*wp++ = htons(M68K_NOP); |
1712 |
|
|
*wp++ = htons(M68K_NOP); |
1713 |
|
|
*wp++ = htons(M68K_NOP); |
1714 |
|
|
*wp++ = htons(M68K_NOP); |
1715 |
|
|
*wp = htons(M68K_NOP); |
1716 |
|
|
|
1717 |
|
|
// Patch GetCPUSpeed (via 0x27a) (some ROMs have two of them) |
1718 |
|
|
static const uint8 cpu_speed_dat[] = {0x20, 0x30, 0x81, 0xf2, 0x5f, 0xff, 0xef, 0xd8, 0x00, 0x04, 0x4c, 0x7c}; |
1719 |
|
|
if ((base = find_rom_data(0x6000, 0x9000, cpu_speed_dat, sizeof(cpu_speed_dat))) == 0) return false; |
1720 |
|
|
D(bug("cpu_speed %08lx\n", base)); |
1721 |
|
|
wp = (uint16 *)(ROM_BASE + base); |
1722 |
|
|
*wp++ = htons(0x203c); // move.l #(MHz<<16)|MHz,d0 |
1723 |
|
|
*wp++ = htons(CPUClockSpeed / 1000000); |
1724 |
|
|
*wp++ = htons(CPUClockSpeed / 1000000); |
1725 |
|
|
*wp = htons(M68K_RTS); |
1726 |
|
|
if ((base = find_rom_data(base, 0x9000, cpu_speed_dat, sizeof(cpu_speed_dat))) != 0) { |
1727 |
|
|
D(bug("cpu_speed2 %08lx\n", base)); |
1728 |
|
|
wp = (uint16 *)(ROM_BASE + base); |
1729 |
|
|
*wp++ = htons(0x203c); // move.l #(MHz<<16)|MHz,d0 |
1730 |
|
|
*wp++ = htons(CPUClockSpeed / 1000000); |
1731 |
|
|
*wp++ = htons(CPUClockSpeed / 1000000); |
1732 |
|
|
*wp = htons(M68K_RTS); |
1733 |
|
|
} |
1734 |
|
|
|
1735 |
|
|
// Don't poke VIA in InitTimeMgr (via 0x298) |
1736 |
|
|
static const uint8 time_via_dat[] = {0x40, 0xe7, 0x00, 0x7c, 0x07, 0x00, 0x28, 0x78, 0x01, 0xd4, 0x43, 0xec, 0x10, 0x00}; |
1737 |
|
|
if ((base = find_rom_data(0x30000, 0x40000, time_via_dat, sizeof(time_via_dat))) == 0) return false; |
1738 |
|
|
D(bug("time_via %08lx\n", base)); |
1739 |
|
|
wp = (uint16 *)(ROM_BASE + base); |
1740 |
|
|
*wp++ = htons(0x4cdf); // movem.l (sp)+,d0-d5/a0-a4 |
1741 |
|
|
*wp++ = htons(0x1f3f); |
1742 |
|
|
*wp = htons(M68K_RTS); |
1743 |
|
|
|
1744 |
|
|
// Don't read from 0xff800000 (Name Registry, Open Firmware?) (via 0x2a2) |
1745 |
|
|
// Remove this if FE03 works!! |
1746 |
|
|
static const uint8 open_firmware_dat[] = {0x2f, 0x79, 0xff, 0x80, 0x00, 0x00, 0x00, 0xfc}; |
1747 |
|
|
if ((base = find_rom_data(0x48000, 0x58000, open_firmware_dat, sizeof(open_firmware_dat))) == 0) return false; |
1748 |
|
|
D(bug("open_firmware %08lx\n", base)); |
1749 |
|
|
wp = (uint16 *)(ROM_BASE + base); |
1750 |
|
|
*wp++ = htons(0x2f7c); // move.l #deadbeef,0xfc(a7) |
1751 |
|
|
*wp++ = htons(0xdead); |
1752 |
|
|
*wp++ = htons(0xbeef); |
1753 |
|
|
*wp = htons(0x00fc); |
1754 |
|
|
wp = (uint16 *)(ROM_BASE + base + 0x1a); |
1755 |
|
|
*wp++ = htons(M68K_NOP); // (FE03 opcode, tries to jump to 0xdeadbeef) |
1756 |
|
|
*wp = htons(M68K_NOP); |
1757 |
|
|
|
1758 |
|
|
// Don't EnableExtCache (via 0x2b2) |
1759 |
|
|
static const uint8 ext_cache2_dat[] = {0x4f, 0xef, 0xff, 0xec, 0x20, 0x4f, 0x10, 0xbc, 0x00, 0x01, 0x11, 0x7c, 0x00, 0x1b}; |
1760 |
|
|
if ((base = find_rom_data(0x13000, 0x20000, ext_cache2_dat, sizeof(ext_cache2_dat))) == 0) return false; |
1761 |
|
|
D(bug("ext_cache2 %08lx\n", base)); |
1762 |
|
|
wp = (uint16 *)(ROM_BASE + base); |
1763 |
|
|
*wp = htons(M68K_RTS); |
1764 |
|
|
|
1765 |
|
|
// Don't install Time Manager task for 60Hz interrupt (Enable60HzInts, via 0x2b8) |
1766 |
|
|
if (ROMType == ROMTYPE_NEWWORLD) { |
1767 |
|
|
static const uint8 tm_task_dat[] = {0x30, 0x3c, 0x4e, 0x2b, 0xa9, 0xc9}; |
1768 |
|
|
if ((base = find_rom_data(0x2e0, 0x320, tm_task_dat, sizeof(tm_task_dat))) == 0) return false; |
1769 |
|
|
D(bug("tm_task %08lx\n", base)); |
1770 |
|
|
wp = (uint16 *)(ROM_BASE + base + 28); |
1771 |
|
|
*wp++ = htons(M68K_NOP); |
1772 |
|
|
*wp++ = htons(M68K_NOP); |
1773 |
|
|
*wp++ = htons(M68K_NOP); |
1774 |
|
|
*wp++ = htons(M68K_NOP); |
1775 |
|
|
*wp++ = htons(M68K_NOP); |
1776 |
|
|
*wp = htons(M68K_NOP); |
1777 |
|
|
} else { |
1778 |
|
|
static const uint8 tm_task_dat[] = {0x20, 0x3c, 0x73, 0x79, 0x73, 0x61}; |
1779 |
|
|
if ((base = find_rom_data(0x280, 0x300, tm_task_dat, sizeof(tm_task_dat))) == 0) return false; |
1780 |
|
|
D(bug("tm_task %08lx\n", base)); |
1781 |
|
|
wp = (uint16 *)(ROM_BASE + base - 6); |
1782 |
|
|
*wp++ = htons(M68K_NOP); |
1783 |
|
|
*wp++ = htons(M68K_NOP); |
1784 |
|
|
*wp = htons(M68K_NOP); |
1785 |
|
|
} |
1786 |
|
|
|
1787 |
|
|
// Don't read PVR from 0x5fffef80 in DriverServicesLib (via 0x316) |
1788 |
|
|
if (ROMType != ROMTYPE_NEWWORLD) { |
1789 |
|
|
uint32 dsl_offset = find_rom_resource(FOURCC('n','l','i','b'), -16401); |
1790 |
|
|
if (ROMType == ROMTYPE_ZANZIBAR) { |
1791 |
|
|
static const uint8 dsl_pvr_dat[] = {0x40, 0x82, 0x00, 0x40, 0x38, 0x60, 0xef, 0x80, 0x3c, 0x63, 0x60, 0x00, 0x80, 0x83, 0x00, 0x00, 0x54, 0x84, 0x84, 0x3e}; |
1792 |
|
|
if ((base = find_rom_data(dsl_offset, dsl_offset + 0x6000, dsl_pvr_dat, sizeof(dsl_pvr_dat))) == 0) return false; |
1793 |
|
|
} else { |
1794 |
|
|
static const uint8 dsl_pvr_dat[] = {0x3b, 0xc3, 0x00, 0x00, 0x30, 0x84, 0xff, 0xa0, 0x40, 0x82, 0x00, 0x44, 0x80, 0x84, 0xef, 0xe0, 0x54, 0x84, 0x84, 0x3e}; |
1795 |
|
|
if ((base = find_rom_data(dsl_offset, dsl_offset + 0x6000, dsl_pvr_dat, sizeof(dsl_pvr_dat))) == 0) return false; |
1796 |
|
|
} |
1797 |
|
|
D(bug("dsl_pvr %08lx\n", base)); |
1798 |
|
|
lp = (uint32 *)(ROM_BASE + base + 12); |
1799 |
|
|
*lp = htonl(0x3c800000 | (PVR >> 16)); // lis r4,PVR |
1800 |
|
|
|
1801 |
|
|
// Don't read bus clock from 0x5fffef88 in DriverServicesLib (via 0x316) |
1802 |
|
|
if (ROMType == ROMTYPE_ZANZIBAR) { |
1803 |
|
|
static const uint8 dsl_bus_dat[] = {0x81, 0x07, 0x00, 0x00, 0x39, 0x20, 0x42, 0x40, 0x81, 0x62, 0xff, 0x20}; |
1804 |
|
|
if ((base = find_rom_data(dsl_offset, dsl_offset + 0x6000, dsl_bus_dat, sizeof(dsl_bus_dat))) == 0) return false; |
1805 |
|
|
D(bug("dsl_bus %08lx\n", base)); |
1806 |
|
|
lp = (uint32 *)(ROM_BASE + base); |
1807 |
|
|
*lp = htonl(0x81000000 + XLM_BUS_CLOCK); // lwz r8,(bus clock speed) |
1808 |
|
|
} else { |
1809 |
|
|
static const uint8 dsl_bus_dat[] = {0x80, 0x83, 0xef, 0xe8, 0x80, 0x62, 0x00, 0x10, 0x7c, 0x04, 0x03, 0x96}; |
1810 |
|
|
if ((base = find_rom_data(dsl_offset, dsl_offset + 0x6000, dsl_bus_dat, sizeof(dsl_bus_dat))) == 0) return false; |
1811 |
|
|
D(bug("dsl_bus %08lx\n", base)); |
1812 |
|
|
lp = (uint32 *)(ROM_BASE + base); |
1813 |
|
|
*lp = htonl(0x80800000 + XLM_BUS_CLOCK); // lwz r4,(bus clock speed) |
1814 |
|
|
} |
1815 |
|
|
} |
1816 |
|
|
|
1817 |
|
|
// Don't open InterruptTreeTNT in MotherBoardHAL init in DriverServicesLib init |
1818 |
|
|
if (ROMType == ROMTYPE_ZANZIBAR) { |
1819 |
|
|
lp = (uint32 *)(ROM_BASE + find_rom_resource(FOURCC('n','l','i','b'), -16408) + 0x16c); |
1820 |
|
|
*lp = htonl(0x38600000); // li r3,0 |
1821 |
|
|
} |
1822 |
|
|
|
1823 |
|
|
// Patch Name Registry |
1824 |
|
|
static const uint8 name_reg_dat[] = {0x70, 0xff, 0xab, 0xeb}; |
1825 |
|
|
if ((base = find_rom_data(0x300, 0x380, name_reg_dat, sizeof(name_reg_dat))) == 0) return false; |
1826 |
|
|
D(bug("name_reg %08lx\n", base)); |
1827 |
|
|
wp = (uint16 *)(ROM_BASE + base); |
1828 |
|
|
*wp = htons(M68K_EMUL_OP_NAME_REGISTRY); |
1829 |
|
|
|
1830 |
|
|
#if DISABLE_SCSI |
1831 |
|
|
// Fake SCSI Manager |
1832 |
|
|
// Remove this if SCSI Manager works!! |
1833 |
|
|
static const uint8 scsi_mgr_a_dat[] = {0x4e, 0x56, 0x00, 0x00, 0x20, 0x3c, 0x00, 0x00, 0x04, 0x0c, 0xa7, 0x1e}; |
1834 |
|
|
static const uint8 scsi_mgr_b_dat[] = {0x4e, 0x56, 0x00, 0x00, 0x2f, 0x0c, 0x20, 0x3c, 0x00, 0x00, 0x04, 0x0c, 0xa7, 0x1e}; |
1835 |
|
|
if ((base = find_rom_data(0x1c000, 0x28000, scsi_mgr_a_dat, sizeof(scsi_mgr_a_dat))) == 0) { |
1836 |
|
|
if ((base = find_rom_data(0x1c000, 0x28000, scsi_mgr_b_dat, sizeof(scsi_mgr_b_dat))) == 0) return false; |
1837 |
|
|
} |
1838 |
|
|
D(bug("scsi_mgr %08lx\n", base)); |
1839 |
|
|
wp = (uint16 *)(ROM_BASE + base); |
1840 |
|
|
*wp++ = htons(0x21fc); // move.l #xxx,0x624 (SCSIAtomic) |
1841 |
|
|
*wp++ = htons((ROM_BASE + base + 18) >> 16); |
1842 |
|
|
*wp++ = htons((ROM_BASE + base + 18) & 0xffff); |
1843 |
|
|
*wp++ = htons(0x0624); |
1844 |
|
|
*wp++ = htons(0x21fc); // move.l #xxx,0xe54 (SCSIDispatch) |
1845 |
|
|
*wp++ = htons((ROM_BASE + base + 22) >> 16); |
1846 |
|
|
*wp++ = htons((ROM_BASE + base + 22) & 0xffff); |
1847 |
|
|
*wp++ = htons(0x0e54); |
1848 |
|
|
*wp++ = htons(M68K_RTS); |
1849 |
|
|
*wp++ = htons(M68K_EMUL_OP_SCSI_ATOMIC); |
1850 |
|
|
*wp++ = htons(M68K_RTS); |
1851 |
|
|
*wp++ = htons(M68K_EMUL_OP_SCSI_DISPATCH); |
1852 |
|
|
*wp = htons(0x4ed0); // jmp (a0) |
1853 |
|
|
wp = (uint16 *)(ROM_BASE + base + 0x20); |
1854 |
|
|
*wp++ = htons(0x7000); // moveq #0,d0 |
1855 |
|
|
*wp = htons(M68K_RTS); |
1856 |
|
|
#endif |
1857 |
|
|
|
1858 |
|
|
#if DISABLE_SCSI |
1859 |
|
|
// Don't access SCSI variables |
1860 |
|
|
// Remove this if SCSI Manager works!! |
1861 |
|
|
if (ROMType == ROMTYPE_NEWWORLD) { |
1862 |
|
|
static const uint8 scsi_var_dat[] = {0x70, 0x01, 0xa0, 0x89, 0x4a, 0x6e, 0xfe, 0xac, 0x4f, 0xef, 0x00, 0x10, 0x66, 0x00}; |
1863 |
|
|
if ((base = find_rom_data(0x1f500, 0x1f600, scsi_var_dat, sizeof(scsi_var_dat))) != 0) { |
1864 |
|
|
D(bug("scsi_var %08lx\n", base)); |
1865 |
|
|
wp = (uint16 *)(ROM_BASE + base + 12); |
1866 |
|
|
*wp = htons(0x6000); // bra |
1867 |
|
|
} |
1868 |
|
|
|
1869 |
|
|
static const uint8 scsi_var2_dat[] = {0x4e, 0x56, 0xfc, 0x58, 0x48, 0xe7, 0x1f, 0x38}; |
1870 |
|
|
if ((base = find_rom_data(0x1f700, 0x1f800, scsi_var2_dat, sizeof(scsi_var2_dat))) != 0) { |
1871 |
|
|
D(bug("scsi_var2 %08lx\n", base)); |
1872 |
|
|
wp = (uint16 *)(ROM_BASE + base); |
1873 |
|
|
*wp++ = htons(0x7000); // moveq #0,d0 |
1874 |
|
|
*wp = htons(M68K_RTS); // bra |
1875 |
|
|
} |
1876 |
|
|
} |
1877 |
|
|
#endif |
1878 |
|
|
|
1879 |
|
|
// Don't wait in ADBInit (via 0x36c) |
1880 |
|
|
static const uint8 adb_init_dat[] = {0x08, 0x2b, 0x00, 0x05, 0x01, 0x5d, 0x66, 0xf8}; |
1881 |
|
|
if ((base = find_rom_data(0x31000, 0x3d000, adb_init_dat, sizeof(adb_init_dat))) == 0) return false; |
1882 |
|
|
D(bug("adb_init %08lx\n", base)); |
1883 |
|
|
wp = (uint16 *)(ROM_BASE + base + 6); |
1884 |
|
|
*wp = htons(M68K_NOP); |
1885 |
|
|
|
1886 |
|
|
// Modify check in InitResources() so that addresses >0x80000000 work |
1887 |
|
|
static const uint8 init_res_dat[] = {0x4a, 0xb8, 0x0a, 0x50, 0x6e, 0x20}; |
1888 |
|
|
if ((base = find_rom_data(0x78000, 0x8c000, init_res_dat, sizeof(init_res_dat))) == 0) return false; |
1889 |
|
|
D(bug("init_res %08lx\n", base)); |
1890 |
|
|
bp = (uint8 *)(ROM_BASE + base + 4); |
1891 |
|
|
*bp = 0x66; |
1892 |
|
|
|
1893 |
|
|
// Modify vCheckLoad() so that we can patch resources (68k Resource Manager) |
1894 |
|
|
static const uint8 check_load_dat[] = {0x20, 0x78, 0x07, 0xf0, 0x4e, 0xd0}; |
1895 |
|
|
if ((base = find_rom_data(0x78000, 0x8c000, check_load_dat, sizeof(check_load_dat))) == 0) return false; |
1896 |
|
|
D(bug("check_load %08lx\n", base)); |
1897 |
|
|
wp = (uint16 *)(ROM_BASE + base); |
1898 |
|
|
*wp++ = htons(M68K_JMP); |
1899 |
|
|
*wp++ = htons((ROM_BASE + CHECK_LOAD_PATCH_SPACE) >> 16); |
1900 |
|
|
*wp = htons((ROM_BASE + CHECK_LOAD_PATCH_SPACE) & 0xffff); |
1901 |
|
|
wp = (uint16 *)(ROM_BASE + CHECK_LOAD_PATCH_SPACE); |
1902 |
|
|
*wp++ = htons(0x2f03); // move.l d3,-(a7) |
1903 |
|
|
*wp++ = htons(0x2078); // move.l $07f0,a0 |
1904 |
|
|
*wp++ = htons(0x07f0); |
1905 |
|
|
*wp++ = htons(M68K_JSR_A0); |
1906 |
|
|
*wp++ = htons(M68K_EMUL_OP_CHECKLOAD); |
1907 |
|
|
*wp = htons(M68K_RTS); |
1908 |
|
|
|
1909 |
|
|
// Replace .Sony driver |
1910 |
|
|
sony_offset = find_rom_resource(FOURCC('D','R','V','R'), 4); |
1911 |
|
|
if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_NEWWORLD) |
1912 |
|
|
sony_offset = find_rom_resource(FOURCC('D','R','V','R'), 4, true); // First DRVR 4 is .MFMFloppy |
1913 |
|
|
if (sony_offset == 0) { |
1914 |
|
|
sony_offset = find_rom_resource(FOURCC('n','d','r','v'), -20196); // NewWorld 1.6 has "PCFloppy" ndrv |
1915 |
|
|
if (sony_offset == 0) |
1916 |
|
|
return false; |
1917 |
|
|
lp = (uint32 *)(ROM_BASE + rsrc_ptr + 8); |
1918 |
|
|
*lp = htonl(FOURCC('D','R','V','R')); |
1919 |
|
|
wp = (uint16 *)(ROM_BASE + rsrc_ptr + 12); |
1920 |
|
|
*wp = htons(4); |
1921 |
|
|
} |
1922 |
|
|
D(bug("sony_offset %08lx\n", sony_offset)); |
1923 |
|
|
memcpy((void *)(ROM_BASE + sony_offset), sony_driver, sizeof(sony_driver)); |
1924 |
|
|
|
1925 |
|
|
// Install .Disk and .AppleCD drivers |
1926 |
|
|
memcpy((void *)(ROM_BASE + sony_offset + 0x100), disk_driver, sizeof(disk_driver)); |
1927 |
|
|
memcpy((void *)(ROM_BASE + sony_offset + 0x200), cdrom_driver, sizeof(cdrom_driver)); |
1928 |
|
|
|
1929 |
|
|
// Install serial drivers |
1930 |
|
|
memcpy((void *)(ROM_BASE + sony_offset + 0x300), ain_driver, sizeof(ain_driver)); |
1931 |
|
|
memcpy((void *)(ROM_BASE + sony_offset + 0x400), aout_driver, sizeof(aout_driver)); |
1932 |
|
|
memcpy((void *)(ROM_BASE + sony_offset + 0x500), bin_driver, sizeof(bin_driver)); |
1933 |
|
|
memcpy((void *)(ROM_BASE + sony_offset + 0x600), bout_driver, sizeof(bout_driver)); |
1934 |
|
|
|
1935 |
|
|
// Copy icons to ROM |
1936 |
|
|
SonyDiskIconAddr = ROM_BASE + sony_offset + 0x800; |
1937 |
|
|
memcpy((void *)(ROM_BASE + sony_offset + 0x800), SonyDiskIcon, sizeof(SonyDiskIcon)); |
1938 |
|
|
SonyDriveIconAddr = ROM_BASE + sony_offset + 0xa00; |
1939 |
|
|
memcpy((void *)(ROM_BASE + sony_offset + 0xa00), SonyDriveIcon, sizeof(SonyDriveIcon)); |
1940 |
|
|
DiskIconAddr = ROM_BASE + sony_offset + 0xc00; |
1941 |
|
|
memcpy((void *)(ROM_BASE + sony_offset + 0xc00), DiskIcon, sizeof(DiskIcon)); |
1942 |
|
|
CDROMIconAddr = ROM_BASE + sony_offset + 0xe00; |
1943 |
|
|
memcpy((void *)(ROM_BASE + sony_offset + 0xe00), CDROMIcon, sizeof(CDROMIcon)); |
1944 |
|
|
|
1945 |
|
|
// Patch driver install routine |
1946 |
|
|
static const uint8 drvr_install_dat[] = {0xa7, 0x1e, 0x21, 0xc8, 0x01, 0x1c, 0x4e, 0x75}; |
1947 |
|
|
if ((base = find_rom_data(0xb00, 0xd00, drvr_install_dat, sizeof(drvr_install_dat))) == 0) return false; |
1948 |
|
|
D(bug("drvr_install %08lx\n", base)); |
1949 |
|
|
wp = (uint16 *)(ROM_BASE + base + 8); |
1950 |
|
|
*wp++ = htons(M68K_EMUL_OP_INSTALL_DRIVERS); |
1951 |
|
|
*wp = htons(M68K_RTS); |
1952 |
|
|
|
1953 |
|
|
// Don't install serial drivers from ROM |
1954 |
|
|
if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_NEWWORLD) { |
1955 |
|
|
wp = (uint16 *)(ROM_BASE + find_rom_resource(FOURCC('S','E','R','D'), 0)); |
1956 |
|
|
*wp = htons(M68K_RTS); |
1957 |
|
|
} else { |
1958 |
|
|
wp = (uint16 *)(ROM_BASE + find_rom_resource(FOURCC('s','l','0','5'), 2) + 0xc4); |
1959 |
|
|
*wp++ = htons(M68K_NOP); |
1960 |
|
|
*wp++ = htons(M68K_NOP); |
1961 |
|
|
*wp++ = htons(M68K_NOP); |
1962 |
|
|
*wp++ = htons(M68K_NOP); |
1963 |
|
|
*wp = htons(0x7000); // moveq #0,d0 |
1964 |
|
|
wp = (uint16 *)(ROM_BASE + find_rom_resource(FOURCC('s','l','0','5'), 2) + 0x8ee); |
1965 |
|
|
*wp = htons(M68K_NOP); |
1966 |
|
|
} |
1967 |
|
|
uint32 nsrd_offset = find_rom_resource(FOURCC('n','s','r','d'), 1); |
1968 |
|
|
if (nsrd_offset) { |
1969 |
|
|
lp = (uint32 *)(ROM_BASE + rsrc_ptr + 8); |
1970 |
|
|
*lp = htonl(FOURCC('x','s','r','d')); |
1971 |
|
|
} |
1972 |
|
|
|
1973 |
|
|
// Replace ADBOp() |
1974 |
|
|
memcpy((void *)(ROM_BASE + find_rom_trap(0xa07c)), adbop_patch, sizeof(adbop_patch)); |
1975 |
|
|
|
1976 |
|
|
// Replace Time Manager |
1977 |
|
|
wp = (uint16 *)(ROM_BASE + find_rom_trap(0xa058)); |
1978 |
|
|
*wp++ = htons(M68K_EMUL_OP_INSTIME); |
1979 |
|
|
*wp = htons(M68K_RTS); |
1980 |
|
|
wp = (uint16 *)(ROM_BASE + find_rom_trap(0xa059)); |
1981 |
|
|
*wp++ = htons(0x40e7); // move sr,-(sp) |
1982 |
|
|
*wp++ = htons(0x007c); // ori #$0700,sr |
1983 |
|
|
*wp++ = htons(0x0700); |
1984 |
|
|
*wp++ = htons(M68K_EMUL_OP_RMVTIME); |
1985 |
|
|
*wp++ = htons(0x46df); // move (sp)+,sr |
1986 |
|
|
*wp = htons(M68K_RTS); |
1987 |
|
|
wp = (uint16 *)(ROM_BASE + find_rom_trap(0xa05a)); |
1988 |
|
|
*wp++ = htons(0x40e7); // move sr,-(sp) |
1989 |
|
|
*wp++ = htons(0x007c); // ori #$0700,sr |
1990 |
|
|
*wp++ = htons(0x0700); |
1991 |
|
|
*wp++ = htons(M68K_EMUL_OP_PRIMETIME); |
1992 |
|
|
*wp++ = htons(0x46df); // move (sp)+,sr |
1993 |
|
|
*wp = htons(M68K_RTS); |
1994 |
|
|
wp = (uint16 *)(ROM_BASE + find_rom_trap(0xa093)); |
1995 |
|
|
*wp++ = htons(M68K_EMUL_OP_MICROSECONDS); |
1996 |
|
|
*wp = htons(M68K_RTS); |
1997 |
|
|
|
1998 |
|
|
// Disable Egret Manager |
1999 |
|
|
static const uint8 egret_dat[] = {0x2f, 0x30, 0x81, 0xe2, 0x20, 0x10, 0x00, 0x18}; |
2000 |
|
|
if ((base = find_rom_data(0xa000, 0x10000, egret_dat, sizeof(egret_dat))) == 0) return false; |
2001 |
|
|
D(bug("egret %08lx\n", base)); |
2002 |
|
|
wp = (uint16 *)(ROM_BASE + base); |
2003 |
|
|
*wp++ = htons(0x7000); |
2004 |
|
|
*wp = htons(M68K_RTS); |
2005 |
|
|
|
2006 |
|
|
// Don't call FE0A opcode in Shutdown Manager |
2007 |
|
|
static const uint8 shutdown_dat[] = {0x40, 0xe7, 0x00, 0x7c, 0x07, 0x00, 0x48, 0xe7, 0x3f, 0x00, 0x2c, 0x00, 0x2e, 0x01}; |
2008 |
|
|
if ((base = find_rom_data(0x30000, 0x40000, shutdown_dat, sizeof(shutdown_dat))) == 0) return false; |
2009 |
|
|
D(bug("shutdown %08lx\n", base)); |
2010 |
|
|
wp = (uint16 *)(ROM_BASE + base); |
2011 |
|
|
if (ROMType == ROMTYPE_ZANZIBAR) |
2012 |
|
|
*wp = htons(M68K_RTS); |
2013 |
|
|
else |
2014 |
|
|
wp[-2] = htons(0x6000); // bra |
2015 |
|
|
|
2016 |
|
|
// Patch PowerOff() |
2017 |
|
|
wp = (uint16 *)(ROM_BASE + find_rom_trap(0xa05b)); // PowerOff() |
2018 |
|
|
*wp = htons(M68K_EMUL_RETURN); |
2019 |
|
|
|
2020 |
|
|
// Patch VIA interrupt handler |
2021 |
|
|
static const uint8 via_int_dat[] = {0x70, 0x7f, 0xc0, 0x29, 0x1a, 0x00, 0xc0, 0x29, 0x1c, 0x00}; |
2022 |
|
|
if ((base = find_rom_data(0x13000, 0x1c000, via_int_dat, sizeof(via_int_dat))) == 0) return false; |
2023 |
|
|
D(bug("via_int %08lx\n", base)); |
2024 |
|
|
uint32 level1_int = ROM_BASE + base; |
2025 |
|
|
wp = (uint16 *)level1_int; // Level 1 handler |
2026 |
|
|
*wp++ = htons(0x7002); // moveq #2,d0 (60Hz interrupt) |
2027 |
|
|
*wp++ = htons(M68K_NOP); |
2028 |
|
|
*wp++ = htons(M68K_NOP); |
2029 |
|
|
*wp++ = htons(M68K_NOP); |
2030 |
|
|
*wp = htons(M68K_NOP); |
2031 |
|
|
|
2032 |
|
|
static const uint8 via_int2_dat[] = {0x13, 0x7c, 0x00, 0x02, 0x1a, 0x00, 0x4e, 0x71, 0x52, 0xb8, 0x01, 0x6a}; |
2033 |
|
|
if ((base = find_rom_data(0x10000, 0x18000, via_int2_dat, sizeof(via_int2_dat))) == 0) return false; |
2034 |
|
|
D(bug("via_int2 %08lx\n", base)); |
2035 |
|
|
wp = (uint16 *)(ROM_BASE + base); // 60Hz handler |
2036 |
|
|
*wp++ = htons(M68K_EMUL_OP_IRQ); |
2037 |
|
|
*wp++ = htons(0x4a80); // tst.l d0 |
2038 |
|
|
*wp++ = htons(0x6700); // beq xxx |
2039 |
|
|
*wp = htons(0xffe8); |
2040 |
|
|
|
2041 |
|
|
if (ROMType == ROMTYPE_NEWWORLD) { |
2042 |
|
|
static const uint8 via_int3_dat[] = {0x48, 0xe7, 0xf0, 0xf0, 0x76, 0x01, 0x60, 0x26}; |
2043 |
|
|
if ((base = find_rom_data(0x15000, 0x18000, via_int3_dat, sizeof(via_int3_dat))) == 0) return false; |
2044 |
|
|
D(bug("via_int3 %08lx\n", base)); |
2045 |
|
|
wp = (uint16 *)(ROM_BASE + base); // CHRP level 1 handler |
2046 |
|
|
*wp++ = htons(M68K_JMP); |
2047 |
|
|
*wp++ = htons((level1_int - 12) >> 16); |
2048 |
|
|
*wp = htons((level1_int - 12) & 0xffff); |
2049 |
|
|
} |
2050 |
|
|
|
2051 |
|
|
// Patch PutScrap() for clipboard exchange with host OS |
2052 |
|
|
uint32 put_scrap = find_rom_trap(0xa9fe); // PutScrap() |
2053 |
|
|
wp = (uint16 *)(ROM_BASE + PUT_SCRAP_PATCH_SPACE); |
2054 |
|
|
*wp++ = htons(M68K_EMUL_OP_PUT_SCRAP); |
2055 |
|
|
*wp++ = htons(M68K_JMP); |
2056 |
|
|
*wp++ = htons((ROM_BASE + put_scrap) >> 16); |
2057 |
|
|
*wp++ = htons((ROM_BASE + put_scrap) & 0xffff); |
2058 |
|
|
lp = (uint32 *)(ROM_BASE + 0x22); |
2059 |
|
|
lp = (uint32 *)(ROM_BASE + ntohl(*lp)); |
2060 |
|
|
lp[0xa9fe & 0x3ff] = htonl(PUT_SCRAP_PATCH_SPACE); |
2061 |
|
|
|
2062 |
|
|
// Patch GetScrap() for clipboard exchange with host OS |
2063 |
|
|
uint32 get_scrap = find_rom_trap(0xa9fd); // GetScrap() |
2064 |
|
|
wp = (uint16 *)(ROM_BASE + GET_SCRAP_PATCH_SPACE); |
2065 |
|
|
*wp++ = htons(M68K_EMUL_OP_GET_SCRAP); |
2066 |
|
|
*wp++ = htons(M68K_JMP); |
2067 |
|
|
*wp++ = htons((ROM_BASE + get_scrap) >> 16); |
2068 |
|
|
*wp++ = htons((ROM_BASE + get_scrap) & 0xffff); |
2069 |
|
|
lp = (uint32 *)(ROM_BASE + 0x22); |
2070 |
|
|
lp = (uint32 *)(ROM_BASE + ntohl(*lp)); |
2071 |
|
|
lp[0xa9fd & 0x3ff] = htonl(GET_SCRAP_PATCH_SPACE); |
2072 |
|
|
|
2073 |
|
|
#if __BEOS__ |
2074 |
|
|
// Patch SynchIdleTime() |
2075 |
|
|
if (PrefsFindBool("idlewait")) { |
2076 |
|
|
wp = (uint16 *)(ROM_BASE + find_rom_trap(0xabf7) + 4); // SynchIdleTime() |
2077 |
|
|
D(bug("SynchIdleTime at %08lx\n", wp)); |
2078 |
|
|
if (ntohs(*wp) == 0x2078) { |
2079 |
|
|
*wp++ = htons(M68K_EMUL_OP_IDLE_TIME); |
2080 |
|
|
*wp = htons(M68K_NOP); |
2081 |
|
|
} else { |
2082 |
|
|
D(bug("SynchIdleTime patch not installed\n")); |
2083 |
|
|
} |
2084 |
|
|
} |
2085 |
|
|
#endif |
2086 |
|
|
|
2087 |
|
|
// Construct list of all sifters used by sound components in ROM |
2088 |
|
|
D(bug("Searching for sound components with type sdev in ROM\n")); |
2089 |
|
|
uint32 thing = find_rom_resource(FOURCC('t','h','n','g')); |
2090 |
|
|
while (thing) { |
2091 |
|
|
thing += ROM_BASE; |
2092 |
|
|
D(bug(" found %c%c%c%c %c%c%c%c\n", ReadMacInt8(thing), ReadMacInt8(thing + 1), ReadMacInt8(thing + 2), ReadMacInt8(thing + 3), ReadMacInt8(thing + 4), ReadMacInt8(thing + 5), ReadMacInt8(thing + 6), ReadMacInt8(thing + 7))); |
2093 |
|
|
if (ReadMacInt32(thing) == FOURCC('s','d','e','v') && ReadMacInt32(thing + 4) == FOURCC('s','i','n','g')) { |
2094 |
|
|
WriteMacInt32(thing + 4, FOURCC('a','w','g','c')); |
2095 |
|
|
D(bug(" found sdev component at offset %08x in ROM\n", thing)); |
2096 |
|
|
AddSifter(ReadMacInt32(thing + componentResType), ReadMacInt16(thing + componentResID)); |
2097 |
|
|
if (ReadMacInt32(thing + componentPFCount)) |
2098 |
|
|
AddSifter(ReadMacInt32(thing + componentPFResType), ReadMacInt16(thing + componentPFResID)); |
2099 |
|
|
} |
2100 |
|
|
thing = find_rom_resource(FOURCC('t','h','n','g'), 4711, true); |
2101 |
|
|
} |
2102 |
|
|
|
2103 |
|
|
// Patch component code |
2104 |
|
|
D(bug("Patching sifters in ROM\n")); |
2105 |
|
|
for (int i=0; i<num_sifters; i++) { |
2106 |
|
|
if ((thing = find_rom_resource(sifter_list[i].type, sifter_list[i].id)) != 0) { |
2107 |
|
|
D(bug(" patching type %08x, id %d\n", sifter_list[i].type, sifter_list[i].id)); |
2108 |
|
|
// Install 68k glue code |
2109 |
|
|
uint16 *wp = (uint16 *)(ROM_BASE + thing); |
2110 |
|
|
*wp++ = htons(0x4e56); *wp++ = htons(0x0000); // link a6,#0 |
2111 |
|
|
*wp++ = htons(0x48e7); *wp++ = htons(0x8018); // movem.l d0/a3-a4,-(a7) |
2112 |
|
|
*wp++ = htons(0x266e); *wp++ = htons(0x000c); // movea.l $c(a6),a3 |
2113 |
|
|
*wp++ = htons(0x286e); *wp++ = htons(0x0008); // movea.l $8(a6),a4 |
2114 |
|
|
*wp++ = htons(M68K_EMUL_OP_AUDIO_DISPATCH); |
2115 |
|
|
*wp++ = htons(0x2d40); *wp++ = htons(0x0010); // move.l d0,$10(a6) |
2116 |
|
|
*wp++ = htons(0x4cdf); *wp++ = htons(0x1801); // movem.l (a7)+,d0/a3-a4 |
2117 |
|
|
*wp++ = htons(0x4e5e); // unlk a6 |
2118 |
|
|
*wp++ = htons(0x4e74); *wp++ = htons(0x0008); // rtd #8 |
2119 |
|
|
} |
2120 |
|
|
} |
2121 |
|
|
return true; |
2122 |
|
|
} |
2123 |
|
|
|
2124 |
|
|
|
2125 |
|
|
/* |
2126 |
|
|
* Install .Sony, disk and CD-ROM drivers |
2127 |
|
|
*/ |
2128 |
|
|
|
2129 |
|
|
void InstallDrivers(void) |
2130 |
|
|
{ |
2131 |
|
|
D(bug("Installing drivers...\n")); |
2132 |
|
|
M68kRegisters r; |
2133 |
|
|
uint8 pb[SIZEOF_IOParam]; |
2134 |
|
|
|
2135 |
|
|
// Open .Sony driver |
2136 |
|
|
WriteMacInt8((uint32)pb + ioPermssn, 0); |
2137 |
|
|
WriteMacInt32((uint32)pb + ioNamePtr, (uint32)"\005.Sony"); |
2138 |
|
|
r.a[0] = (uint32)pb; |
2139 |
|
|
Execute68kTrap(0xa000, &r); // Open() |
2140 |
|
|
|
2141 |
|
|
// Install disk driver |
2142 |
|
|
r.a[0] = ROM_BASE + sony_offset + 0x100; |
2143 |
|
|
r.d[0] = (uint32)DiskRefNum; |
2144 |
|
|
Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem() |
2145 |
|
|
r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~DiskRefNum * 4); // Get driver handle from Unit Table |
2146 |
|
|
Execute68kTrap(0xa029, &r); // HLock() |
2147 |
|
|
uint32 dce = ReadMacInt32(r.a[0]); |
2148 |
|
|
WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x100); |
2149 |
|
|
WriteMacInt16(dce + dCtlFlags, DiskDriverFlags); |
2150 |
|
|
|
2151 |
|
|
// Open disk driver |
2152 |
|
|
WriteMacInt32((uint32)pb + ioNamePtr, (uint32)"\005.Disk"); |
2153 |
|
|
r.a[0] = (uint32)pb; |
2154 |
|
|
Execute68kTrap(0xa000, &r); // Open() |
2155 |
|
|
|
2156 |
|
|
// Install CD-ROM driver unless nocdrom option given |
2157 |
|
|
if (!PrefsFindBool("nocdrom")) { |
2158 |
|
|
|
2159 |
|
|
// Install CD-ROM driver |
2160 |
|
|
r.a[0] = ROM_BASE + sony_offset + 0x200; |
2161 |
|
|
r.d[0] = (uint32)CDROMRefNum; |
2162 |
|
|
Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem() |
2163 |
|
|
r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~CDROMRefNum * 4); // Get driver handle from Unit Table |
2164 |
|
|
Execute68kTrap(0xa029, &r); // HLock() |
2165 |
|
|
dce = ReadMacInt32(r.a[0]); |
2166 |
|
|
WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x200); |
2167 |
|
|
WriteMacInt16(dce + dCtlFlags, CDROMDriverFlags); |
2168 |
|
|
|
2169 |
|
|
// Open CD-ROM driver |
2170 |
|
|
WriteMacInt32((uint32)pb + ioNamePtr, (uint32)"\010.AppleCD"); |
2171 |
|
|
r.a[0] = (uint32)pb; |
2172 |
|
|
Execute68kTrap(0xa000, &r); // Open() |
2173 |
|
|
} |
2174 |
|
|
|
2175 |
|
|
// Install serial drivers |
2176 |
|
|
r.a[0] = ROM_BASE + sony_offset + 0x300; |
2177 |
|
|
r.d[0] = (uint32)-6; |
2178 |
|
|
Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem() |
2179 |
|
|
r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~(-6) * 4); // Get driver handle from Unit Table |
2180 |
|
|
Execute68kTrap(0xa029, &r); // HLock() |
2181 |
|
|
dce = ReadMacInt32(r.a[0]); |
2182 |
|
|
WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x300); |
2183 |
|
|
WriteMacInt16(dce + dCtlFlags, 0x4d00); |
2184 |
|
|
|
2185 |
|
|
r.a[0] = ROM_BASE + sony_offset + 0x400; |
2186 |
|
|
r.d[0] = (uint32)-7; |
2187 |
|
|
Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem() |
2188 |
|
|
r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~(-7) * 4); // Get driver handle from Unit Table |
2189 |
|
|
Execute68kTrap(0xa029, &r); // HLock() |
2190 |
|
|
dce = ReadMacInt32(r.a[0]); |
2191 |
|
|
WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x400); |
2192 |
|
|
WriteMacInt16(dce + dCtlFlags, 0x4e00); |
2193 |
|
|
|
2194 |
|
|
r.a[0] = ROM_BASE + sony_offset + 0x500; |
2195 |
|
|
r.d[0] = (uint32)-8; |
2196 |
|
|
Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem() |
2197 |
|
|
r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~(-8) * 4); // Get driver handle from Unit Table |
2198 |
|
|
Execute68kTrap(0xa029, &r); // HLock() |
2199 |
|
|
dce = ReadMacInt32(r.a[0]); |
2200 |
|
|
WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x500); |
2201 |
|
|
WriteMacInt16(dce + dCtlFlags, 0x4d00); |
2202 |
|
|
|
2203 |
|
|
r.a[0] = ROM_BASE + sony_offset + 0x600; |
2204 |
|
|
r.d[0] = (uint32)-9; |
2205 |
|
|
Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem() |
2206 |
|
|
r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~(-9) * 4); // Get driver handle from Unit Table |
2207 |
|
|
Execute68kTrap(0xa029, &r); // HLock() |
2208 |
|
|
dce = ReadMacInt32(r.a[0]); |
2209 |
|
|
WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x600); |
2210 |
|
|
WriteMacInt16(dce + dCtlFlags, 0x4e00); |
2211 |
|
|
} |