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root/cebix/SheepShaver/src/rom_patches.cpp
Revision: 1.4
Committed: 2003-05-17T08:42:34Z (21 years, 6 months ago) by gbeauche
Branch: MAIN
Changes since 1.3: +10 -7 lines
Log Message: 
Finally enable boot on MacOS 8.6 Update CD from iMac DV
- Don't read PVR at ROM_BASE + 0x314600
- Generated code for FC1E and FE0A don't really match comments
- Move FC1E routine base to ROM_BASE + 0x36fb00
- Recognize iMacUpdate 1.1 ROM (nwrom v1.2.1)

File Contents

# User Rev Content
1 cebix 1.1 /*
2     * rom_patches.cpp - ROM patches
3     *
4     * SheepShaver (C) 1997-2002 Christian Bauer and Marc Hellwig
5     *
6     * This program is free software; you can redistribute it and/or modify
7     * it under the terms of the GNU General Public License as published by
8     * the Free Software Foundation; either version 2 of the License, or
9     * (at your option) any later version.
10     *
11     * This program is distributed in the hope that it will be useful,
12     * but WITHOUT ANY WARRANTY; without even the implied warranty of
13     * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14     * GNU General Public License for more details.
15     *
16     * You should have received a copy of the GNU General Public License
17     * along with this program; if not, write to the Free Software
18     * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19     */
20    
21     /*
22     * TODO:
23     * IRQ_NEST must be handled atomically
24     * Don't use r1 in extra routines
25     */
26    
27     #include <string.h>
28    
29     #include "sysdeps.h"
30     #include "rom_patches.h"
31     #include "main.h"
32     #include "prefs.h"
33     #include "cpu_emulation.h"
34     #include "emul_op.h"
35     #include "xlowmem.h"
36     #include "sony.h"
37     #include "disk.h"
38     #include "cdrom.h"
39     #include "audio.h"
40     #include "audio_defs.h"
41     #include "serial.h"
42     #include "macos_util.h"
43    
44     #define DEBUG 0
45     #include "debug.h"
46    
47    
48     // 68k breakpoint address
49     //#define M68K_BREAK_POINT 0x29e0 // BootMe
50     //#define M68K_BREAK_POINT 0x2a1e // Boot block code returned
51     //#define M68K_BREAK_POINT 0x3150 // CritError
52     //#define M68K_BREAK_POINT 0x187ce // Unimplemented trap
53    
54     // PowerPC breakpoint address
55     //#define POWERPC_BREAK_POINT 0x36e6c0 // 68k emulator start
56    
57     #define DISABLE_SCSI 1
58    
59    
60     // Other ROM addresses
61     const uint32 CHECK_LOAD_PATCH_SPACE = 0x2f7f00;
62     const uint32 PUT_SCRAP_PATCH_SPACE = 0x2f7f80;
63     const uint32 GET_SCRAP_PATCH_SPACE = 0x2f7fc0;
64     const uint32 ADDR_MAP_PATCH_SPACE = 0x2f8000;
65    
66     // Global variables
67     int ROMType; // ROM type
68     static uint32 sony_offset; // Offset of .Sony driver resource
69    
70     // Prototypes
71     static bool patch_nanokernel_boot(void);
72     static bool patch_68k_emul(void);
73     static bool patch_nanokernel(void);
74     static bool patch_68k(void);
75    
76    
77 gbeauche 1.2 // Decode LZSS data
78     static void decode_lzss(const uint8 *src, uint8 *dest, int size)
79     {
80     char dict[0x1000];
81     int run_mask = 0, dict_idx = 0xfee;
82     for (;;) {
83     if (run_mask < 0x100) {
84     // Start new run
85     if (--size < 0)
86     break;
87     run_mask = *src++ | 0xff00;
88     }
89     bool bit = run_mask & 1;
90     run_mask >>= 1;
91     if (bit) {
92     // Verbatim copy
93     if (--size < 0)
94     break;
95     int c = *src++;
96     dict[dict_idx++] = c;
97     *dest++ = c;
98     dict_idx &= 0xfff;
99     } else {
100     // Copy from dictionary
101     if (--size < 0)
102     break;
103     int idx = *src++;
104     if (--size < 0)
105     break;
106     int cnt = *src++;
107     idx |= (cnt << 4) & 0xf00;
108     cnt = (cnt & 0x0f) + 3;
109     while (cnt--) {
110     char c = dict[idx++];
111     dict[dict_idx++] = c;
112     *dest++ = c;
113     idx &= 0xfff;
114     dict_idx &= 0xfff;
115     }
116     }
117     }
118     }
119    
120     // Decode parcels of ROM image (MacOS 9.X and even earlier)
121     void decode_parcels(const uint8 *src, uint8 *dest, int size)
122     {
123     uint32 parcel_offset = 0x14;
124     D(bug("Offset Type Name\n"));
125     while (parcel_offset != 0) {
126     const uint32 *parcel_data = (uint32 *)(src + parcel_offset);
127 gbeauche 1.3 uint32 next_offset = ntohl(parcel_data[0]);
128 gbeauche 1.2 uint32 parcel_type = ntohl(parcel_data[1]);
129     D(bug("%08x %c%c%c%c %s\n", parcel_offset,
130     (parcel_type >> 24) & 0xff, (parcel_type >> 16) & 0xff,
131     (parcel_type >> 8) & 0xff, parcel_type & 0xff, &parcel_data[6]));
132     if (parcel_type == FOURCC('r','o','m',' ')) {
133     uint32 lzss_offset = ntohl(parcel_data[2]);
134     uint32 lzss_size = ((uint32)src + parcel_offset) - ((uint32)parcel_data + lzss_offset);
135     decode_lzss((uint8 *)parcel_data + lzss_offset, dest, lzss_size);
136     }
137 gbeauche 1.3 parcel_offset = next_offset;
138 gbeauche 1.2 }
139     }
140    
141    
142     /*
143     * Decode ROM image, 4 MB plain images or NewWorld images
144     */
145    
146     bool DecodeROM(uint8 *data, uint32 size)
147     {
148     if (size == ROM_SIZE) {
149     // Plain ROM image
150     memcpy((void *)ROM_BASE, data, ROM_SIZE);
151     return true;
152     }
153     else if (strncmp((char *)data, "<CHRP-BOOT>", 11) == 0) {
154     // CHRP compressed ROM image
155     uint32 image_offset, image_size;
156     bool decode_info_ok = false;
157    
158     char *s = strstr((char *)data, "constant lzss-offset");
159     if (s != NULL) {
160     // Probably a plain LZSS compressed ROM image
161     if (sscanf(s - 7, "%06x", &image_offset) == 1) {
162     s = strstr((char *)data, "constant lzss-size");
163     if (s != NULL && (sscanf(s - 7, "%06x", &image_size) == 1))
164     decode_info_ok = true;
165     }
166     }
167     else {
168     // Probably a MacOS 9.2.x ROM image
169     s = strstr((char *)data, "constant parcels-offset");
170     if (s != NULL) {
171     if (sscanf(s - 7, "%06x", &image_offset) == 1) {
172     s = strstr((char *)data, "constant parcels-size");
173     if (s != NULL && (sscanf(s - 7, "%06x", &image_size) == 1))
174     decode_info_ok = true;
175     }
176     }
177     }
178    
179     // No valid information to decode the ROM found?
180     if (!decode_info_ok)
181     return false;
182    
183     // Check signature, this could be a parcels-based ROM image
184     uint32 rom_signature = ntohl(*(uint32 *)(data + image_offset));
185     if (rom_signature == FOURCC('p','r','c','l')) {
186     D(bug("Offset of parcels data: %08x\n", image_offset));
187     D(bug("Size of parcels data: %08x\n", image_size));
188     decode_parcels(data + image_offset, (uint8 *)ROM_BASE, image_size);
189     }
190     else {
191     D(bug("Offset of compressed data: %08x\n", image_offset));
192     D(bug("Size of compressed data: %08x\n", image_size));
193     decode_lzss(data + image_offset, (uint8 *)ROM_BASE, image_size);
194     }
195     return true;
196     }
197     return false;
198     }
199    
200    
201 cebix 1.1 /*
202     * Search ROM for byte string, return ROM offset (or 0)
203     */
204    
205     static uint32 find_rom_data(uint32 start, uint32 end, const uint8 *data, uint32 data_len)
206     {
207     uint32 ofs = start;
208     while (ofs < end) {
209     if (!memcmp((void *)(ROM_BASE + ofs), data, data_len))
210     return ofs;
211     ofs++;
212     }
213     return 0;
214     }
215    
216    
217     /*
218     * Search ROM resource by type/ID, return ROM offset of resource data
219     */
220    
221     static uint32 rsrc_ptr = 0;
222    
223     // id = 4711 means "find any ID"
224     static uint32 find_rom_resource(uint32 s_type, int16 s_id = 4711, bool cont = false)
225     {
226     uint32 *lp = (uint32 *)(ROM_BASE + 0x1a);
227     uint32 x = ntohl(*lp);
228     uint8 *bp = (uint8 *)(ROM_BASE + x + 5);
229     uint32 header_size = *bp;
230    
231     if (!cont)
232     rsrc_ptr = x;
233     else if (rsrc_ptr == 0)
234     return 0;
235    
236     for (;;) {
237     lp = (uint32 *)(ROM_BASE + rsrc_ptr);
238     rsrc_ptr = ntohl(*lp);
239     if (rsrc_ptr == 0)
240     break;
241    
242     rsrc_ptr += header_size;
243    
244     lp = (uint32 *)(ROM_BASE + rsrc_ptr + 4);
245     uint32 data = ntohl(*lp); lp++;
246     uint32 type = ntohl(*lp); lp++;
247     int16 id = ntohs(*(int16 *)lp);
248     if (type == s_type && (id == s_id || s_id == 4711))
249     return data;
250     }
251     return 0;
252     }
253    
254    
255     /*
256     * Search offset of A-Trap routine in ROM
257     */
258    
259     static uint32 find_rom_trap(uint16 trap)
260     {
261     uint32 *lp = (uint32 *)(ROM_BASE + 0x22);
262     lp = (uint32 *)(ROM_BASE + ntohl(*lp));
263    
264     if (trap > 0xa800)
265     return ntohl(lp[trap & 0x3ff]);
266     else
267     return ntohl(lp[(trap & 0xff) + 0x400]);
268     }
269    
270    
271     /*
272     * List of audio sifters installed in ROM and System file
273     */
274    
275     struct sift_entry {
276     uint32 type;
277     int16 id;
278     };
279     static sift_entry sifter_list[32];
280     static int num_sifters;
281    
282     void AddSifter(uint32 type, int16 id)
283     {
284     if (FindSifter(type, id))
285     return;
286     D(bug(" adding sifter type %c%c%c%c (%08x), id %d\n", type >> 24, (type >> 16) & 0xff, (type >> 8) & 0xff, type & 0xff, type, id));
287     sifter_list[num_sifters].type = type;
288     sifter_list[num_sifters].id = id;
289     num_sifters++;
290     }
291    
292     bool FindSifter(uint32 type, int16 id)
293     {
294     for (int i=0; i<num_sifters; i++) {
295     if (sifter_list[i].type == type && sifter_list[i].id == id)
296     return true;
297     }
298     return false;
299     }
300    
301    
302     /*
303     * Driver stubs
304     */
305    
306     static const uint8 sony_driver[] = { // Replacement for .Sony driver
307     // Driver header
308     SonyDriverFlags >> 8, SonyDriverFlags & 0xff, 0, 0, 0, 0, 0, 0,
309     0x00, 0x18, // Open() offset
310     0x00, 0x1c, // Prime() offset
311     0x00, 0x20, // Control() offset
312     0x00, 0x2c, // Status() offset
313     0x00, 0x52, // Close() offset
314     0x05, 0x2e, 0x53, 0x6f, 0x6e, 0x79, // ".Sony"
315    
316     // Open()
317     M68K_EMUL_OP_SONY_OPEN >> 8, M68K_EMUL_OP_SONY_OPEN & 0xff,
318     0x4e, 0x75, // rts
319    
320     // Prime()
321     M68K_EMUL_OP_SONY_PRIME >> 8, M68K_EMUL_OP_SONY_PRIME & 0xff,
322     0x60, 0x0e, // bra IOReturn
323    
324     // Control()
325     M68K_EMUL_OP_SONY_CONTROL >> 8, M68K_EMUL_OP_SONY_CONTROL & 0xff,
326     0x0c, 0x68, 0x00, 0x01, 0x00, 0x1a, // cmp.w #1,$1a(a0)
327     0x66, 0x04, // bne IOReturn
328     0x4e, 0x75, // rts
329    
330     // Status()
331     M68K_EMUL_OP_SONY_STATUS >> 8, M68K_EMUL_OP_SONY_STATUS & 0xff,
332    
333     // IOReturn
334     0x32, 0x28, 0x00, 0x06, // move.w 6(a0),d1
335     0x08, 0x01, 0x00, 0x09, // btst #9,d1
336     0x67, 0x0c, // beq 1
337     0x4a, 0x40, // tst.w d0
338     0x6f, 0x02, // ble 2
339     0x42, 0x40, // clr.w d0
340     0x31, 0x40, 0x00, 0x10, //2 move.w d0,$10(a0)
341     0x4e, 0x75, // rts
342     0x4a, 0x40, //1 tst.w d0
343     0x6f, 0x04, // ble 3
344     0x42, 0x40, // clr.w d0
345     0x4e, 0x75, // rts
346     0x2f, 0x38, 0x08, 0xfc, //3 move.l $8fc,-(sp)
347     0x4e, 0x75, // rts
348    
349     // Close()
350     0x70, 0xe8, // moveq #-24,d0
351     0x4e, 0x75 // rts
352     };
353    
354     static const uint8 disk_driver[] = { // Generic disk driver
355     // Driver header
356     DiskDriverFlags >> 8, DiskDriverFlags & 0xff, 0, 0, 0, 0, 0, 0,
357     0x00, 0x18, // Open() offset
358     0x00, 0x1c, // Prime() offset
359     0x00, 0x20, // Control() offset
360     0x00, 0x2c, // Status() offset
361     0x00, 0x52, // Close() offset
362     0x05, 0x2e, 0x44, 0x69, 0x73, 0x6b, // ".Disk"
363    
364     // Open()
365     M68K_EMUL_OP_DISK_OPEN >> 8, M68K_EMUL_OP_DISK_OPEN & 0xff,
366     0x4e, 0x75, // rts
367    
368     // Prime()
369     M68K_EMUL_OP_DISK_PRIME >> 8, M68K_EMUL_OP_DISK_PRIME & 0xff,
370     0x60, 0x0e, // bra IOReturn
371    
372     // Control()
373     M68K_EMUL_OP_DISK_CONTROL >> 8, M68K_EMUL_OP_DISK_CONTROL & 0xff,
374     0x0c, 0x68, 0x00, 0x01, 0x00, 0x1a, // cmp.w #1,$1a(a0)
375     0x66, 0x04, // bne IOReturn
376     0x4e, 0x75, // rts
377    
378     // Status()
379     M68K_EMUL_OP_DISK_STATUS >> 8, M68K_EMUL_OP_DISK_STATUS & 0xff,
380    
381     // IOReturn
382     0x32, 0x28, 0x00, 0x06, // move.w 6(a0),d1
383     0x08, 0x01, 0x00, 0x09, // btst #9,d1
384     0x67, 0x0c, // beq 1
385     0x4a, 0x40, // tst.w d0
386     0x6f, 0x02, // ble 2
387     0x42, 0x40, // clr.w d0
388     0x31, 0x40, 0x00, 0x10, //2 move.w d0,$10(a0)
389     0x4e, 0x75, // rts
390     0x4a, 0x40, //1 tst.w d0
391     0x6f, 0x04, // ble 3
392     0x42, 0x40, // clr.w d0
393     0x4e, 0x75, // rts
394     0x2f, 0x38, 0x08, 0xfc, //3 move.l $8fc,-(sp)
395     0x4e, 0x75, // rts
396    
397     // Close()
398     0x70, 0xe8, // moveq #-24,d0
399     0x4e, 0x75 // rts
400     };
401    
402     static const uint8 cdrom_driver[] = { // CD-ROM driver
403     // Driver header
404     CDROMDriverFlags >> 8, CDROMDriverFlags & 0xff, 0, 0, 0, 0, 0, 0,
405     0x00, 0x1c, // Open() offset
406     0x00, 0x20, // Prime() offset
407     0x00, 0x24, // Control() offset
408     0x00, 0x30, // Status() offset
409     0x00, 0x56, // Close() offset
410     0x08, 0x2e, 0x41, 0x70, 0x70, 0x6c, 0x65, 0x43, 0x44, 0x00, // ".AppleCD"
411    
412     // Open()
413     M68K_EMUL_OP_CDROM_OPEN >> 8, M68K_EMUL_OP_CDROM_OPEN & 0xff,
414     0x4e, 0x75, // rts
415    
416     // Prime()
417     M68K_EMUL_OP_CDROM_PRIME >> 8, M68K_EMUL_OP_CDROM_PRIME & 0xff,
418     0x60, 0x0e, // bra IOReturn
419    
420     // Control()
421     M68K_EMUL_OP_CDROM_CONTROL >> 8, M68K_EMUL_OP_CDROM_CONTROL & 0xff,
422     0x0c, 0x68, 0x00, 0x01, 0x00, 0x1a, // cmp.w #1,$1a(a0)
423     0x66, 0x04, // bne IOReturn
424     0x4e, 0x75, // rts
425    
426     // Status()
427     M68K_EMUL_OP_CDROM_STATUS >> 8, M68K_EMUL_OP_CDROM_STATUS & 0xff,
428    
429     // IOReturn
430     0x32, 0x28, 0x00, 0x06, // move.w 6(a0),d1
431     0x08, 0x01, 0x00, 0x09, // btst #9,d1
432     0x67, 0x0c, // beq 1
433     0x4a, 0x40, // tst.w d0
434     0x6f, 0x02, // ble 2
435     0x42, 0x40, // clr.w d0
436     0x31, 0x40, 0x00, 0x10, //2 move.w d0,$10(a0)
437     0x4e, 0x75, // rts
438     0x4a, 0x40, //1 tst.w d0
439     0x6f, 0x04, // ble 3
440     0x42, 0x40, // clr.w d0
441     0x4e, 0x75, // rts
442     0x2f, 0x38, 0x08, 0xfc, //3 move.l $8fc,-(sp)
443     0x4e, 0x75, // rts
444    
445     // Close()
446     0x70, 0xe8, // moveq #-24,d0
447     0x4e, 0x75 // rts
448     };
449    
450     #ifdef __linux__
451     static uint32 serial_nothing_tvect[2] = {(uint32)SerialNothing, 0};
452     static uint32 serial_open_tvect[2] = {(uint32)SerialOpen, 0};
453     static uint32 serial_prime_in_tvect[2] = {(uint32)SerialPrimeIn, 0};
454     static uint32 serial_prime_out_tvect[2] = {(uint32)SerialPrimeOut, 0};
455     static uint32 serial_control_tvect[2] = {(uint32)SerialControl, 0};
456     static uint32 serial_status_tvect[2] = {(uint32)SerialStatus, 0};
457     static uint32 serial_close_tvect[2] = {(uint32)SerialClose, 0};
458     #endif
459    
460     static const uint32 ain_driver[] = { // .AIn driver header
461     0x4d000000, 0x00000000,
462     0x00200040, 0x00600080,
463     0x00a0042e, 0x41496e00,
464     0x00000000, 0x00000000,
465     0xaafe0700, 0x00000000,
466     0x00000000, 0x00179822,
467     #ifdef __linux__
468     0x00010004, (uint32)serial_nothing_tvect,
469     #else
470     0x00010004, (uint32)SerialNothing,
471     #endif
472     0x00000000, 0x00000000,
473     0xaafe0700, 0x00000000,
474     0x00000000, 0x00179822,
475     #ifdef __linux__
476     0x00010004, (uint32)serial_prime_in_tvect,
477     #else
478     0x00010004, (uint32)SerialPrimeIn,
479     #endif
480     0x00000000, 0x00000000,
481     0xaafe0700, 0x00000000,
482     0x00000000, 0x00179822,
483     #ifdef __linux__
484     0x00010004, (uint32)serial_control_tvect,
485     #else
486     0x00010004, (uint32)SerialControl,
487     #endif
488     0x00000000, 0x00000000,
489     0xaafe0700, 0x00000000,
490     0x00000000, 0x00179822,
491     #ifdef __linux__
492     0x00010004, (uint32)serial_status_tvect,
493     #else
494     0x00010004, (uint32)SerialStatus,
495     #endif
496     0x00000000, 0x00000000,
497     0xaafe0700, 0x00000000,
498     0x00000000, 0x00179822,
499     #ifdef __linux__
500     0x00010004, (uint32)serial_nothing_tvect,
501     #else
502     0x00010004, (uint32)SerialNothing,
503     #endif
504     0x00000000, 0x00000000,
505     };
506    
507     static const uint32 aout_driver[] = { // .AOut driver header
508     0x4d000000, 0x00000000,
509     0x00200040, 0x00600080,
510     0x00a0052e, 0x414f7574,
511     0x00000000, 0x00000000,
512     0xaafe0700, 0x00000000,
513     0x00000000, 0x00179822,
514     #ifdef __linux__
515     0x00010004, (uint32)serial_open_tvect,
516     #else
517     0x00010004, (uint32)SerialOpen,
518     #endif
519     0x00000000, 0x00000000,
520     0xaafe0700, 0x00000000,
521     0x00000000, 0x00179822,
522     #ifdef __linux__
523     0x00010004, (uint32)serial_prime_out_tvect,
524     #else
525     0x00010004, (uint32)SerialPrimeOut,
526     #endif
527     0x00000000, 0x00000000,
528     0xaafe0700, 0x00000000,
529     0x00000000, 0x00179822,
530     #ifdef __linux__
531     0x00010004, (uint32)serial_control_tvect,
532     #else
533     0x00010004, (uint32)SerialControl,
534     #endif
535     0x00000000, 0x00000000,
536     0xaafe0700, 0x00000000,
537     0x00000000, 0x00179822,
538     #ifdef __linux__
539     0x00010004, (uint32)serial_status_tvect,
540     #else
541     0x00010004, (uint32)SerialStatus,
542     #endif
543     0x00000000, 0x00000000,
544     0xaafe0700, 0x00000000,
545     0x00000000, 0x00179822,
546     #ifdef __linux__
547     0x00010004, (uint32)serial_close_tvect,
548     #else
549     0x00010004, (uint32)SerialClose,
550     #endif
551     0x00000000, 0x00000000,
552     };
553    
554     static const uint32 bin_driver[] = { // .BIn driver header
555     0x4d000000, 0x00000000,
556     0x00200040, 0x00600080,
557     0x00a0042e, 0x42496e00,
558     0x00000000, 0x00000000,
559     0xaafe0700, 0x00000000,
560     0x00000000, 0x00179822,
561     #ifdef __linux__
562     0x00010004, (uint32)serial_nothing_tvect,
563     #else
564     0x00010004, (uint32)SerialNothing,
565     #endif
566     0x00000000, 0x00000000,
567     0xaafe0700, 0x00000000,
568     0x00000000, 0x00179822,
569     #ifdef __linux__
570     0x00010004, (uint32)serial_prime_in_tvect,
571     #else
572     0x00010004, (uint32)SerialPrimeIn,
573     #endif
574     0x00000000, 0x00000000,
575     0xaafe0700, 0x00000000,
576     0x00000000, 0x00179822,
577     #ifdef __linux__
578     0x00010004, (uint32)serial_control_tvect,
579     #else
580     0x00010004, (uint32)SerialControl,
581     #endif
582     0x00000000, 0x00000000,
583     0xaafe0700, 0x00000000,
584     0x00000000, 0x00179822,
585     #ifdef __linux__
586     0x00010004, (uint32)serial_status_tvect,
587     #else
588     0x00010004, (uint32)SerialStatus,
589     #endif
590     0x00000000, 0x00000000,
591     0xaafe0700, 0x00000000,
592     0x00000000, 0x00179822,
593     #ifdef __linux__
594     0x00010004, (uint32)serial_nothing_tvect,
595     #else
596     0x00010004, (uint32)SerialNothing,
597     #endif
598     0x00000000, 0x00000000,
599     };
600    
601     static const uint32 bout_driver[] = { // .BOut driver header
602     0x4d000000, 0x00000000,
603     0x00200040, 0x00600080,
604     0x00a0052e, 0x424f7574,
605     0x00000000, 0x00000000,
606     0xaafe0700, 0x00000000,
607     0x00000000, 0x00179822,
608     #ifdef __linux__
609     0x00010004, (uint32)serial_open_tvect,
610     #else
611     0x00010004, (uint32)SerialOpen,
612     #endif
613     0x00000000, 0x00000000,
614     0xaafe0700, 0x00000000,
615     0x00000000, 0x00179822,
616     #ifdef __linux__
617     0x00010004, (uint32)serial_prime_out_tvect,
618     #else
619     0x00010004, (uint32)SerialPrimeOut,
620     #endif
621     0x00000000, 0x00000000,
622     0xaafe0700, 0x00000000,
623     0x00000000, 0x00179822,
624     #ifdef __linux__
625     0x00010004, (uint32)serial_control_tvect,
626     #else
627     0x00010004, (uint32)SerialControl,
628     #endif
629     0x00000000, 0x00000000,
630     0xaafe0700, 0x00000000,
631     0x00000000, 0x00179822,
632     #ifdef __linux__
633     0x00010004, (uint32)serial_status_tvect,
634     #else
635     0x00010004, (uint32)SerialStatus,
636     #endif
637     0x00000000, 0x00000000,
638     0xaafe0700, 0x00000000,
639     0x00000000, 0x00179822,
640     #ifdef __linux__
641     0x00010004, (uint32)serial_close_tvect,
642     #else
643     0x00010004, (uint32)SerialClose,
644     #endif
645     0x00000000, 0x00000000,
646     };
647    
648     static const uint8 adbop_patch[] = { // Call ADBOp() completion procedure
649     // The completion procedure may call ADBOp() again!
650     0x40, 0xe7, // move sr,-(sp)
651     0x00, 0x7c, 0x07, 0x00, // ori #$0700,sr
652     M68K_EMUL_OP_ADBOP >> 8, M68K_EMUL_OP_ADBOP & 0xff,
653     0x48, 0xe7, 0x70, 0xf0, // movem.l d1-d3/a0-a3,-(sp)
654     0x26, 0x48, // move.l a0,a3
655     0x4a, 0xab, 0x00, 0x04, // tst.l 4(a3)
656     0x67, 0x00, 0x00, 0x18, // beq 1
657     0x20, 0x53, // move.l (a3),a0
658     0x22, 0x6b, 0x00, 0x04, // move.l 4(a3),a1
659     0x24, 0x6b, 0x00, 0x08, // move.l 8(a3),a2
660     0x26, 0x78, 0x0c, 0xf8, // move.l $cf8,a3
661     0x4e, 0x91, // jsr (a1)
662     0x70, 0x00, // moveq #0,d0
663     0x60, 0x00, 0x00, 0x04, // bra 2
664     0x70, 0xff, //1 moveq #-1,d0
665     0x4c, 0xdf, 0x0f, 0x0e, //2 movem.l (sp)+,d1-d3/a0-a3
666     0x46, 0xdf, // move (sp)+,sr
667     0x4e, 0x75 // rts
668     };
669    
670    
671     /*
672     * Install ROM patches (RAMBase and KernelDataAddr must be set)
673     */
674    
675     bool PatchROM(void)
676     {
677     // Print ROM info
678     D(bug("Checksum: %08lx\n", ntohl(*(uint32 *)ROM_BASE)));
679     D(bug("Version: %04x\n", ntohs(*(uint16 *)(ROM_BASE + 8))));
680     D(bug("Sub Version: %04x\n", ntohs(*(uint16 *)(ROM_BASE + 18))));
681     D(bug("Nanokernel ID: %s\n", (char *)ROM_BASE + 0x30d064));
682     D(bug("Resource Map at %08lx\n", ntohl(*(uint32 *)(ROM_BASE + 26))));
683     D(bug("Trap Tables at %08lx\n\n", ntohl(*(uint32 *)(ROM_BASE + 34))));
684    
685     // Detect ROM type
686     if (!memcmp((void *)(ROM_BASE + 0x30d064), "Boot TNT", 8))
687     ROMType = ROMTYPE_TNT;
688     else if (!memcmp((void *)(ROM_BASE + 0x30d064), "Boot Alchemy", 12))
689     ROMType = ROMTYPE_ALCHEMY;
690     else if (!memcmp((void *)(ROM_BASE + 0x30d064), "Boot Zanzibar", 13))
691     ROMType = ROMTYPE_ZANZIBAR;
692     else if (!memcmp((void *)(ROM_BASE + 0x30d064), "Boot Gazelle", 12))
693     ROMType = ROMTYPE_GAZELLE;
694     else if (!memcmp((void *)(ROM_BASE + 0x30d064), "NewWorld", 8))
695     ROMType = ROMTYPE_NEWWORLD;
696     else
697     return false;
698    
699     // Apply patches
700     if (!patch_nanokernel_boot()) return false;
701     if (!patch_68k_emul()) return false;
702     if (!patch_nanokernel()) return false;
703     if (!patch_68k()) return false;
704    
705     #ifdef M68K_BREAK_POINT
706     // Install 68k breakpoint
707     uint16 *wp = (uint16 *)(ROM_BASE + M68K_BREAK_POINT);
708     *wp++ = htons(M68K_EMUL_BREAK);
709     *wp = htons(M68K_EMUL_RETURN);
710     #endif
711    
712     #ifdef POWERPC_BREAK_POINT
713     // Install PowerPC breakpoint
714     uint32 *lp = (uint32 *)(ROM_BASE + POWERPC_BREAK_POINT);
715     *lp = htonl(0);
716     #endif
717    
718     // Copy 68k emulator to 2MB boundary
719     memcpy((void *)(ROM_BASE + ROM_SIZE), (void *)(ROM_BASE + ROM_SIZE - 0x100000), 0x100000);
720     return true;
721     }
722    
723    
724     /*
725     * Nanokernel boot routine patches
726     */
727    
728     static bool patch_nanokernel_boot(void)
729     {
730     uint32 *lp;
731    
732     // ROM boot structure patches
733     lp = (uint32 *)(ROM_BASE + 0x30d000);
734     lp[0x9c >> 2] = htonl(KernelDataAddr); // LA_InfoRecord
735     lp[0xa0 >> 2] = htonl(KernelDataAddr); // LA_KernelData
736     lp[0xa4 >> 2] = htonl(KernelDataAddr + 0x1000); // LA_EmulatorData
737     lp[0xa8 >> 2] = htonl(ROM_BASE + 0x480000); // LA_DispatchTable
738     lp[0xac >> 2] = htonl(ROM_BASE + 0x460000); // LA_EmulatorCode
739     lp[0x360 >> 2] = htonl(0); // Physical RAM base (? on NewWorld ROM, this contains -1)
740     lp[0xfd8 >> 2] = htonl(ROM_BASE + 0x2a); // 68k reset vector
741    
742     // Skip SR/BAT/SDR init
743     if (ROMType == ROMTYPE_GAZELLE || ROMType == ROMTYPE_NEWWORLD) {
744     lp = (uint32 *)(ROM_BASE + 0x310000);
745     *lp++ = htonl(POWERPC_NOP);
746     *lp = htonl(0x38000000);
747     }
748     static const uint32 sr_init_loc[] = {0x3101b0, 0x3101b0, 0x3101b0, 0x3101ec, 0x310200};
749     lp = (uint32 *)(ROM_BASE + 0x310008);
750     *lp = htonl(0x48000000 | (sr_init_loc[ROMType] - 8) & 0xffff); // b ROM_BASE+0x3101b0
751     lp = (uint32 *)(ROM_BASE + sr_init_loc[ROMType]);
752     *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA); // lwz r1,(pointer to Kernel Data)
753     *lp++ = htonl(0x3da0dead); // lis r13,0xdead (start of kernel memory)
754     *lp++ = htonl(0x3dc00010); // lis r14,0x0010 (size of page table)
755     *lp = htonl(0x3de00010); // lis r15,0x0010 (size of kernel memory)
756    
757     // Don't read PVR
758     static const uint32 pvr_loc[] = {0x3103b0, 0x3103b4, 0x3103b4, 0x310400, 0x310438};
759     lp = (uint32 *)(ROM_BASE + pvr_loc[ROMType]);
760     *lp = htonl(0x81800000 + XLM_PVR); // lwz r12,(theoretical PVR)
761    
762     // Set CPU specific data (even if ROM doesn't have support for that CPU)
763     lp = (uint32 *)(ROM_BASE + pvr_loc[ROMType]);
764     if (ntohl(lp[6]) != 0x2c0c0001)
765     return false;
766     uint32 ofs = ntohl(lp[7]) & 0xffff;
767     D(bug("ofs %08lx\n", ofs));
768     lp[8] = htonl((ntohl(lp[8]) & 0xffff) | 0x48000000); // beq -> b
769     uint32 loc = (ntohl(lp[8]) & 0xffff) + (uint32)(lp+8) - ROM_BASE;
770     D(bug("loc %08lx\n", loc));
771     lp = (uint32 *)(ROM_BASE + ofs + 0x310000);
772     switch (PVR >> 16) {
773     case 1: // 601
774     lp[0] = htonl(0x1000); // Page size
775     lp[1] = htonl(0x8000); // Data cache size
776     lp[2] = htonl(0x8000); // Inst cache size
777     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
778     lp[4] = htonl(0x00010040); // Unified caches/Inst cache line size
779     lp[5] = htonl(0x00400020); // Data cache line size/Data cache block size touch
780     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
781     lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc
782     lp[8] = htonl(0x01000002); // TLB total size/TLB assoc
783     break;
784     case 3: // 603
785     lp[0] = htonl(0x1000); // Page size
786     lp[1] = htonl(0x2000); // Data cache size
787     lp[2] = htonl(0x2000); // Inst cache size
788     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
789     lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
790     lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
791     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
792     lp[7] = htonl(0x00020002); // Inst cache assoc/Data cache assoc
793     lp[8] = htonl(0x00400002); // TLB total size/TLB assoc
794     break;
795     case 4: // 604
796     lp[0] = htonl(0x1000); // Page size
797     lp[1] = htonl(0x4000); // Data cache size
798     lp[2] = htonl(0x4000); // Inst cache size
799     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
800     lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
801     lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
802     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
803     lp[7] = htonl(0x00040004); // Inst cache assoc/Data cache assoc
804     lp[8] = htonl(0x00800002); // TLB total size/TLB assoc
805     break;
806     // case 5: // 740?
807     case 6: // 603e
808     case 7: // 603ev
809     lp[0] = htonl(0x1000); // Page size
810     lp[1] = htonl(0x4000); // Data cache size
811     lp[2] = htonl(0x4000); // Inst cache size
812     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
813     lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
814     lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
815     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
816     lp[7] = htonl(0x00040004); // Inst cache assoc/Data cache assoc
817     lp[8] = htonl(0x00400002); // TLB total size/TLB assoc
818     break;
819     case 8: // 750
820     lp[0] = htonl(0x1000); // Page size
821     lp[1] = htonl(0x8000); // Data cache size
822     lp[2] = htonl(0x8000); // Inst cache size
823     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
824     lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
825     lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
826     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
827     lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc
828     lp[8] = htonl(0x00800002); // TLB total size/TLB assoc
829     break;
830     case 9: // 604e
831     case 10: // 604ev5
832     lp[0] = htonl(0x1000); // Page size
833     lp[1] = htonl(0x8000); // Data cache size
834     lp[2] = htonl(0x8000); // Inst cache size
835     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
836     lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
837     lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
838     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
839     lp[7] = htonl(0x00040004); // Inst cache assoc/Data cache assoc
840     lp[8] = htonl(0x00800002); // TLB total size/TLB assoc
841     break;
842     // case 11: // X704?
843     case 12: // ???
844     lp[0] = htonl(0x1000); // Page size
845     lp[1] = htonl(0x8000); // Data cache size
846     lp[2] = htonl(0x8000); // Inst cache size
847     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
848     lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
849     lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
850     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
851     lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc
852     lp[8] = htonl(0x00800002); // TLB total size/TLB assoc
853     break;
854     case 13: // ???
855     lp[0] = htonl(0x1000); // Page size
856     lp[1] = htonl(0x8000); // Data cache size
857     lp[2] = htonl(0x8000); // Inst cache size
858     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
859     lp[4] = htonl(0x00000020); // Unified caches/Inst cache line size
860     lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
861     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
862     lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc
863     lp[8] = htonl(0x01000004); // TLB total size/TLB assoc
864     break;
865     // case 50: // 821
866     // case 80: // 860
867     case 96: // ???
868     lp[0] = htonl(0x1000); // Page size
869     lp[1] = htonl(0x8000); // Data cache size
870     lp[2] = htonl(0x8000); // Inst cache size
871     lp[3] = htonl(0x00200020); // Coherency block size/Reservation granule size
872     lp[4] = htonl(0x00010020); // Unified caches/Inst cache line size
873     lp[5] = htonl(0x00200020); // Data cache line size/Data cache block size touch
874     lp[6] = htonl(0x00200020); // Inst cache block size/Data cache block size
875     lp[7] = htonl(0x00080008); // Inst cache assoc/Data cache assoc
876     lp[8] = htonl(0x00800004); // TLB total size/TLB assoc
877     break;
878     default:
879     printf("WARNING: Unknown CPU type\n");
880     break;
881     }
882    
883     // Don't set SPRG3, don't test MQ
884     lp = (uint32 *)(ROM_BASE + loc + 0x20);
885     *lp++ = htonl(POWERPC_NOP);
886     lp++;
887     *lp++ = htonl(POWERPC_NOP);
888     lp++;
889     *lp = htonl(POWERPC_NOP);
890    
891     // Don't read MSR
892     lp = (uint32 *)(ROM_BASE + loc + 0x40);
893     *lp = htonl(0x39c00000); // li r14,0
894    
895     // Don't write to DEC
896     lp = (uint32 *)(ROM_BASE + loc + 0x70);
897     *lp++ = htonl(POWERPC_NOP);
898     loc = (ntohl(lp[0]) & 0xffff) + (uint32)lp - ROM_BASE;
899     D(bug("loc %08lx\n", loc));
900    
901     // Don't set SPRG3
902     lp = (uint32 *)(ROM_BASE + loc + 0x2c);
903     *lp = htonl(POWERPC_NOP);
904    
905     // Don't read PVR
906     static const uint32 pvr_ofs[] = {0x138, 0x138, 0x138, 0x140, 0x148};
907     lp = (uint32 *)(ROM_BASE + loc + pvr_ofs[ROMType]);
908     *lp = htonl(0x82e00000 + XLM_PVR); // lwz r23,(theoretical PVR)
909     lp = (uint32 *)(ROM_BASE + loc + 0x170);
910     if (ntohl(*lp) == 0x7eff42a6) // NewWorld ROM
911     *lp = htonl(0x82e00000 + XLM_PVR); // lwz r23,(theoretical PVR)
912     lp = (uint32 *)(ROM_BASE + 0x313134);
913     if (ntohl(*lp) == 0x7e5f42a6)
914     *lp = htonl(0x82400000 + XLM_PVR); // lwz r18,(theoretical PVR)
915     lp = (uint32 *)(ROM_BASE + 0x3131f4);
916     if (ntohl(*lp) == 0x7e5f42a6) // NewWorld ROM
917     *lp = htonl(0x82400000 + XLM_PVR); // lwz r18,(theoretical PVR)
918 gbeauche 1.4 lp = (uint32 *)(ROM_BASE + 0x314600);
919     if (ntohl(*lp) == 0x7d3f42a6)
920     *lp = htonl(0x81200000 + XLM_PVR); // lzw r9,(theoritical PVR)
921 cebix 1.1
922     // Don't read SDR1
923     static const uint32 sdr1_ofs[] = {0x174, 0x174, 0x174, 0x17c, 0x19c};
924     lp = (uint32 *)(ROM_BASE + loc + sdr1_ofs[ROMType]);
925     *lp++ = htonl(0x3d00dead); // lis r8,0xdead (pointer to page table)
926     *lp++ = htonl(0x3ec0001f); // lis r22,0x001f (size of page table)
927     *lp = htonl(POWERPC_NOP);
928    
929     // Don't clear page table
930     static const uint32 pgtb_ofs[] = {0x198, 0x198, 0x198, 0x1a0, 0x1c4};
931     lp = (uint32 *)(ROM_BASE + loc + pgtb_ofs[ROMType]);
932     *lp = htonl(POWERPC_NOP);
933    
934     // Don't invalidate TLB
935     static const uint32 tlb_ofs[] = {0x1a0, 0x1a0, 0x1a0, 0x1a8, 0x1cc};
936     lp = (uint32 *)(ROM_BASE + loc + tlb_ofs[ROMType]);
937     *lp = htonl(POWERPC_NOP);
938    
939     // Don't create RAM descriptor table
940     static const uint32 desc_ofs[] = {0x350, 0x350, 0x350, 0x358, 0x37c};
941     lp = (uint32 *)(ROM_BASE + loc + desc_ofs[ROMType]);
942     *lp = htonl(POWERPC_NOP);
943    
944     // Don't load SRs and BATs
945     static const uint32 sr_ofs[] = {0x3d8, 0x3d8, 0x3d8, 0x3e0, 0x404};
946     lp = (uint32 *)(ROM_BASE + loc + sr_ofs[ROMType]);
947     *lp = htonl(POWERPC_NOP);
948    
949     // Don't mess with SRs
950     static const uint32 sr2_ofs[] = {0x312118, 0x312118, 0x312118, 0x312118, 0x3121b4};
951     lp = (uint32 *)(ROM_BASE + sr2_ofs[ROMType]);
952     *lp = htonl(POWERPC_BLR);
953    
954     // Don't check performance monitor
955     static const uint32 pm_ofs[] = {0x313148, 0x313148, 0x313148, 0x313148, 0x313218};
956     lp = (uint32 *)(ROM_BASE + pm_ofs[ROMType]);
957     while (ntohl(*lp) != 0x7e58eba6) lp++;
958     *lp++ = htonl(POWERPC_NOP);
959     while (ntohl(*lp) != 0x7e78eaa6) lp++;
960     *lp++ = htonl(POWERPC_NOP);
961     while (ntohl(*lp) != 0x7e59eba6) lp++;
962     *lp++ = htonl(POWERPC_NOP);
963     while (ntohl(*lp) != 0x7e79eaa6) lp++;
964     *lp++ = htonl(POWERPC_NOP);
965     while (ntohl(*lp) != 0x7e5aeba6) lp++;
966     *lp++ = htonl(POWERPC_NOP);
967     while (ntohl(*lp) != 0x7e7aeaa6) lp++;
968     *lp++ = htonl(POWERPC_NOP);
969     while (ntohl(*lp) != 0x7e5beba6) lp++;
970     *lp++ = htonl(POWERPC_NOP);
971     while (ntohl(*lp) != 0x7e7beaa6) lp++;
972     *lp++ = htonl(POWERPC_NOP);
973     while (ntohl(*lp) != 0x7e5feba6) lp++;
974     *lp++ = htonl(POWERPC_NOP);
975     while (ntohl(*lp) != 0x7e7feaa6) lp++;
976     *lp++ = htonl(POWERPC_NOP);
977     while (ntohl(*lp) != 0x7e5ceba6) lp++;
978     *lp++ = htonl(POWERPC_NOP);
979     while (ntohl(*lp) != 0x7e7ceaa6) lp++;
980     *lp++ = htonl(POWERPC_NOP);
981     while (ntohl(*lp) != 0x7e5deba6) lp++;
982     *lp++ = htonl(POWERPC_NOP);
983     while (ntohl(*lp) != 0x7e7deaa6) lp++;
984     *lp++ = htonl(POWERPC_NOP);
985     while (ntohl(*lp) != 0x7e5eeba6) lp++;
986     *lp++ = htonl(POWERPC_NOP);
987     while (ntohl(*lp) != 0x7e7eeaa6) lp++;
988     *lp++ = htonl(POWERPC_NOP);
989    
990     // Jump to 68k emulator
991     static const uint32 jump68k_ofs[] = {0x40c, 0x40c, 0x40c, 0x414, 0x438};
992     lp = (uint32 *)(ROM_BASE + loc + jump68k_ofs[ROMType]);
993     *lp++ = htonl(0x80610634); // lwz r3,0x0634(r1) (pointer to Emulator Data)
994     *lp++ = htonl(0x8081119c); // lwz r4,0x119c(r1) (pointer to opcode table)
995     *lp++ = htonl(0x80011184); // lwz r0,0x1184(r1) (pointer to emulator init routine)
996     *lp++ = htonl(0x7c0903a6); // mtctr r0
997     *lp = htonl(POWERPC_BCTR);
998     return true;
999     }
1000    
1001    
1002     /*
1003     * 68k emulator patches
1004     */
1005    
1006     static bool patch_68k_emul(void)
1007     {
1008     uint32 *lp;
1009     uint32 base;
1010    
1011     // Overwrite twi instructions
1012     static const uint32 twi_loc[] = {0x36e680, 0x36e6c0, 0x36e6c0, 0x36e6c0, 0x36e740};
1013     base = twi_loc[ROMType];
1014     lp = (uint32 *)(ROM_BASE + base);
1015     *lp++ = htonl(0x48000000 + 0x36f900 - base); // b 0x36f900 (Emulator start)
1016     *lp++ = htonl(0x48000000 + 0x36fa00 - base - 4); // b 0x36fa00 (Mixed mode)
1017     *lp++ = htonl(0x48000000 + 0x36fb00 - base - 8); // b 0x36fb00 (Reset/FC1E opcode)
1018     *lp++ = htonl(0x48000000 + 0x36fc00 - base - 12); // FE0A opcode
1019     *lp++ = htonl(POWERPC_ILLEGAL); // Interrupt
1020     *lp++ = htonl(POWERPC_ILLEGAL); // ?
1021     *lp++ = htonl(POWERPC_ILLEGAL);
1022     *lp++ = htonl(POWERPC_ILLEGAL);
1023     *lp++ = htonl(POWERPC_ILLEGAL);
1024     *lp++ = htonl(POWERPC_ILLEGAL);
1025     *lp++ = htonl(POWERPC_ILLEGAL);
1026     *lp++ = htonl(POWERPC_ILLEGAL);
1027     *lp++ = htonl(POWERPC_ILLEGAL);
1028     *lp++ = htonl(POWERPC_ILLEGAL);
1029     *lp++ = htonl(POWERPC_ILLEGAL);
1030     *lp = htonl(POWERPC_ILLEGAL);
1031    
1032     #if EMULATED_PPC
1033     // Install EMUL_RETURN, EXEC_RETURN and EMUL_OP opcodes
1034     lp = (uint32 *)(ROM_BASE + 0x380000 + (M68K_EMUL_RETURN << 3));
1035     *lp++ = htonl(POWERPC_EMUL_OP);
1036     *lp++ = htonl(0x4bf66e80); // b 0x366084
1037     *lp++ = htonl(POWERPC_EMUL_OP | 1);
1038     *lp++ = htonl(0x4bf66e78); // b 0x366084
1039     for (int i=0; i<OP_MAX; i++) {
1040     *lp++ = htonl(POWERPC_EMUL_OP | (i + 2));
1041     *lp++ = htonl(0x4bf66e70 - i*8); // b 0x366084
1042     }
1043     #else
1044     // Install EMUL_RETURN, EXEC_RETURN and EMUL_OP opcodes
1045     lp = (uint32 *)(ROM_BASE + 0x380000 + (M68K_EMUL_RETURN << 3));
1046     *lp++ = htonl(0x80000000 + XLM_EMUL_RETURN_PROC); // lwz r0,XLM_EMUL_RETURN_PROC
1047     *lp++ = htonl(0x4bf705fc); // b 0x36f800
1048     *lp++ = htonl(0x80000000 + XLM_EXEC_RETURN_PROC); // lwz r0,XLM_EXEC_RETURN_PROC
1049     *lp++ = htonl(0x4bf705f4); // b 0x36f800
1050     for (int i=0; i<OP_MAX; i++) {
1051     *lp++ = htonl(0x38a00000 + i); // li r5,OP_*
1052     *lp++ = htonl(0x4bf705f4 - i*8); // b 0x36f808
1053     }
1054    
1055     // Extra routines for EMUL_RETURN/EXEC_RETURN/EMUL_OP
1056     lp = (uint32 *)(ROM_BASE + 0x36f800);
1057     *lp++ = htonl(0x7c0803a6); // mtlr r0
1058     *lp++ = htonl(0x4e800020); // blr
1059    
1060     *lp++ = htonl(0x80000000 + XLM_EMUL_OP_PROC); // lwz r0,XLM_EMUL_OP_PROC
1061     *lp++ = htonl(0x7c0803a6); // mtlr r0
1062     *lp = htonl(0x4e800020); // blr
1063     #endif
1064    
1065     // Extra routine for 68k emulator start
1066     lp = (uint32 *)(ROM_BASE + 0x36f900);
1067     *lp++ = htonl(0x7c2903a6); // mtctr r1
1068     *lp++ = htonl(0x80200000 + XLM_IRQ_NEST); // lwz r1,XLM_IRQ_NEST
1069     *lp++ = htonl(0x38210001); // addi r1,r1,1
1070     *lp++ = htonl(0x90200000 + XLM_IRQ_NEST); // stw r1,XLM_IRQ_NEST
1071     *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz r1,XLM_KERNEL_DATA
1072     *lp++ = htonl(0x90c10018); // stw r6,0x18(r1)
1073     *lp++ = htonl(0x7cc902a6); // mfctr r6
1074     *lp++ = htonl(0x90c10004); // stw r6,$0004(r1)
1075     *lp++ = htonl(0x80c1065c); // lwz r6,$065c(r1)
1076     *lp++ = htonl(0x90e6013c); // stw r7,$013c(r6)
1077     *lp++ = htonl(0x91060144); // stw r8,$0144(r6)
1078     *lp++ = htonl(0x9126014c); // stw r9,$014c(r6)
1079     *lp++ = htonl(0x91460154); // stw r10,$0154(r6)
1080     *lp++ = htonl(0x9166015c); // stw r11,$015c(r6)
1081     *lp++ = htonl(0x91860164); // stw r12,$0164(r6)
1082     *lp++ = htonl(0x91a6016c); // stw r13,$016c(r6)
1083     *lp++ = htonl(0x7da00026); // mfcr r13
1084     *lp++ = htonl(0x80e10660); // lwz r7,$0660(r1)
1085     *lp++ = htonl(0x7d8802a6); // mflr r12
1086     *lp++ = htonl(0x50e74001); // rlwimi. r7,r7,8,$80000000
1087     *lp++ = htonl(0x814105f0); // lwz r10,0x05f0(r1)
1088     *lp++ = htonl(0x7d4803a6); // mtlr r10
1089     *lp++ = htonl(0x7d8a6378); // mr r10,r12
1090     *lp++ = htonl(0x3d600002); // lis r11,0x0002
1091     *lp++ = htonl(0x616bf072); // ori r11,r11,0xf072 (MSR)
1092     *lp++ = htonl(0x50e7deb4); // rlwimi r7,r7,27,$00000020
1093     *lp = htonl(0x4e800020); // blr
1094    
1095     // Extra routine for Mixed Mode
1096     lp = (uint32 *)(ROM_BASE + 0x36fa00);
1097     *lp++ = htonl(0x7c2903a6); // mtctr r1
1098     *lp++ = htonl(0x80200000 + XLM_IRQ_NEST); // lwz r1,XLM_IRQ_NEST
1099     *lp++ = htonl(0x38210001); // addi r1,r1,1
1100     *lp++ = htonl(0x90200000 + XLM_IRQ_NEST); // stw r1,XLM_IRQ_NEST
1101     *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz r1,XLM_KERNEL_DATA
1102     *lp++ = htonl(0x90c10018); // stw r6,0x18(r1)
1103     *lp++ = htonl(0x7cc902a6); // mfctr r6
1104     *lp++ = htonl(0x90c10004); // stw r6,$0004(r1)
1105     *lp++ = htonl(0x80c1065c); // lwz r6,$065c(r1)
1106     *lp++ = htonl(0x90e6013c); // stw r7,$013c(r6)
1107     *lp++ = htonl(0x91060144); // stw r8,$0144(r6)
1108     *lp++ = htonl(0x9126014c); // stw r9,$014c(r6)
1109     *lp++ = htonl(0x91460154); // stw r10,$0154(r6)
1110     *lp++ = htonl(0x9166015c); // stw r11,$015c(r6)
1111     *lp++ = htonl(0x91860164); // stw r12,$0164(r6)
1112     *lp++ = htonl(0x91a6016c); // stw r13,$016c(r6)
1113     *lp++ = htonl(0x7da00026); // mfcr r13
1114     *lp++ = htonl(0x80e10660); // lwz r7,$0660(r1)
1115     *lp++ = htonl(0x7d8802a6); // mflr r12
1116     *lp++ = htonl(0x50e74001); // rlwimi. r7,r7,8,$80000000
1117     *lp++ = htonl(0x814105f4); // lwz r10,0x05f4(r1)
1118     *lp++ = htonl(0x7d4803a6); // mtlr r10
1119     *lp++ = htonl(0x7d8a6378); // mr r10,r12
1120     *lp++ = htonl(0x3d600002); // lis r11,0x0002
1121     *lp++ = htonl(0x616bf072); // ori r11,r11,0xf072 (MSR)
1122     *lp++ = htonl(0x50e7deb4); // rlwimi r7,r7,27,$00000020
1123     *lp = htonl(0x4e800020); // blr
1124    
1125     // Extra routine for Reset/FC1E opcode
1126 gbeauche 1.4 lp = (uint32 *)(ROM_BASE + 0x36fb00);
1127 cebix 1.1 *lp++ = htonl(0x7c2903a6); // mtctr r1
1128     *lp++ = htonl(0x80200000 + XLM_IRQ_NEST); // lwz r1,XLM_IRQ_NEST
1129     *lp++ = htonl(0x38210001); // addi r1,r1,1
1130     *lp++ = htonl(0x90200000 + XLM_IRQ_NEST); // stw r1,XLM_IRQ_NEST
1131     *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz r1,XLM_KERNEL_DATA
1132     *lp++ = htonl(0x90c10018); // stw r6,0x18(r1)
1133     *lp++ = htonl(0x7cc902a6); // mfctr r6
1134     *lp++ = htonl(0x90c10004); // stw r6,$0004(r1)
1135     *lp++ = htonl(0x80c1065c); // lwz r6,$065c(r1)
1136     *lp++ = htonl(0x90e6013c); // stw r7,$013c(r6)
1137     *lp++ = htonl(0x91060144); // stw r8,$0144(r6)
1138     *lp++ = htonl(0x9126014c); // stw r9,$014c(r6)
1139     *lp++ = htonl(0x91460154); // stw r10,$0154(r6)
1140     *lp++ = htonl(0x9166015c); // stw r11,$015c(r6)
1141     *lp++ = htonl(0x91860164); // stw r12,$0164(r6)
1142     *lp++ = htonl(0x91a6016c); // stw r13,$016c(r6)
1143     *lp++ = htonl(0x7da00026); // mfcr r13
1144     *lp++ = htonl(0x80e10660); // lwz r7,$0660(r1)
1145     *lp++ = htonl(0x7d8802a6); // mflr r12
1146     *lp++ = htonl(0x50e74001); // rlwimi. r7,r7,8,$80000000
1147 gbeauche 1.4 *lp++ = htonl(0x814105f8); // lwz r10,0x05f8(r1)
1148 cebix 1.1 *lp++ = htonl(0x7d4803a6); // mtlr r10
1149     *lp++ = htonl(0x7d8a6378); // mr r10,r12
1150     *lp++ = htonl(0x3d600002); // lis r11,0x0002
1151     *lp++ = htonl(0x616bf072); // ori r11,r11,0xf072 (MSR)
1152     *lp++ = htonl(0x50e7deb4); // rlwimi r7,r7,27,$00000020
1153     *lp = htonl(0x4e800020); // blr
1154    
1155     // Extra routine for FE0A opcode (QuickDraw 3D needs this)
1156     lp = (uint32 *)(ROM_BASE + 0x36fc00);
1157     *lp++ = htonl(0x7c2903a6); // mtctr r1
1158     *lp++ = htonl(0x80200000 + XLM_IRQ_NEST); // lwz r1,XLM_IRQ_NEST
1159     *lp++ = htonl(0x38210001); // addi r1,r1,1
1160     *lp++ = htonl(0x90200000 + XLM_IRQ_NEST); // stw r1,XLM_IRQ_NEST
1161     *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz r1,XLM_KERNEL_DATA
1162     *lp++ = htonl(0x90c10018); // stw r6,0x18(r1)
1163     *lp++ = htonl(0x7cc902a6); // mfctr r6
1164     *lp++ = htonl(0x90c10004); // stw r6,$0004(r1)
1165     *lp++ = htonl(0x80c1065c); // lwz r6,$065c(r1)
1166     *lp++ = htonl(0x90e6013c); // stw r7,$013c(r6)
1167     *lp++ = htonl(0x91060144); // stw r8,$0144(r6)
1168     *lp++ = htonl(0x9126014c); // stw r9,$014c(r6)
1169     *lp++ = htonl(0x91460154); // stw r10,$0154(r6)
1170     *lp++ = htonl(0x9166015c); // stw r11,$015c(r6)
1171     *lp++ = htonl(0x91860164); // stw r12,$0164(r6)
1172     *lp++ = htonl(0x91a6016c); // stw r13,$016c(r6)
1173     *lp++ = htonl(0x7da00026); // mfcr r13
1174     *lp++ = htonl(0x80e10660); // lwz r7,$0660(r1)
1175     *lp++ = htonl(0x7d8802a6); // mflr r12
1176     *lp++ = htonl(0x50e74001); // rlwimi. r7,r7,8,$80000000
1177 gbeauche 1.4 *lp++ = htonl(0x814105fc); // lwz r10,0x05fc(r1)
1178 cebix 1.1 *lp++ = htonl(0x7d4803a6); // mtlr r10
1179     *lp++ = htonl(0x7d8a6378); // mr r10,r12
1180     *lp++ = htonl(0x3d600002); // lis r11,0x0002
1181     *lp++ = htonl(0x616bf072); // ori r11,r11,0xf072 (MSR)
1182     *lp++ = htonl(0x50e7deb4); // rlwimi r7,r7,27,$00000020
1183     *lp = htonl(0x4e800020); // blr
1184    
1185     // Patch DR emulator to jump to right address when an interrupt occurs
1186     lp = (uint32 *)(ROM_BASE + 0x370000);
1187     while (lp < (uint32 *)(ROM_BASE + 0x380000)) {
1188     if (ntohl(*lp) == 0x4ca80020) // bclr 5,8
1189     goto dr_found;
1190     lp++;
1191     }
1192     D(bug("DR emulator patch location not found\n"));
1193     return false;
1194     dr_found:
1195     lp++;
1196     *lp = htonl(0x48000000 + 0xf000 - (((uint32)lp - ROM_BASE) & 0xffff)); // b DR_CACHE_BASE+0x1f000
1197     lp = (uint32 *)(ROM_BASE + 0x37f000);
1198     *lp++ = htonl(0x3c000000 + ((ROM_BASE + 0x46d0a4) >> 16)); // lis r0,xxx
1199     *lp++ = htonl(0x60000000 + ((ROM_BASE + 0x46d0a4) & 0xffff)); // ori r0,r0,xxx
1200     *lp++ = htonl(0x7c0903a6); // mtctr r0
1201     *lp = htonl(POWERPC_BCTR); // bctr
1202     return true;
1203     }
1204    
1205    
1206     /*
1207     * Nanokernel patches
1208     */
1209    
1210     static bool patch_nanokernel(void)
1211     {
1212     uint32 *lp;
1213    
1214     // Patch Mixed Mode trap
1215     lp = (uint32 *)(ROM_BASE + 0x313c90); // Don't translate virtual->physical
1216     while (ntohl(*lp) != 0x3ba10320) lp++;
1217     lp++;
1218     *lp++ = htonl(0x7f7fdb78); // mr r31,r27
1219     lp++;
1220     *lp = htonl(POWERPC_NOP);
1221    
1222     lp = (uint32 *)(ROM_BASE + 0x313c3c); // Don't activate PPC exception table
1223     while (ntohl(*lp) != 0x39010420) lp++;
1224     *lp++ = htonl(0x39000000 + MODE_NATIVE); // li r8,MODE_NATIVE
1225     *lp = htonl(0x91000000 + XLM_RUN_MODE); // stw r8,XLM_RUN_MODE
1226    
1227     lp = (uint32 *)(ROM_BASE + 0x312e88); // Don't modify MSR to turn on FPU
1228     while (ntohl(*lp) != 0x556b04e2) lp++;
1229     lp -= 4;
1230     *lp++ = htonl(POWERPC_NOP);
1231     lp++;
1232     *lp++ = htonl(POWERPC_NOP);
1233     lp++;
1234     *lp = htonl(POWERPC_NOP);
1235    
1236     lp = (uint32 *)(ROM_BASE + 0x312b3c); // Always save FPU state
1237     while (ntohl(*lp) != 0x81010668) lp++;
1238     lp--;
1239     *lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff)); // bl 0x00312e88
1240    
1241     lp = (uint32 *)(ROM_BASE + 0x312b44); // Don't read DEC
1242     while (ntohl(*lp) != 0x7ff602a6) lp++;
1243     *lp = htonl(0x3be00000); // li r31,0
1244    
1245     lp = (uint32 *)(ROM_BASE + 0x312b50); // Don't write DEC
1246     while (ntohl(*lp) != 0x7d1603a6) lp++;
1247     #if 1
1248     *lp++ = htonl(POWERPC_NOP);
1249     *lp = htonl(POWERPC_NOP);
1250     #else
1251     *lp++ = htonl(0x39000040); // li r8,0x40
1252     *lp = htonl(0x990600e4); // stb r8,0xe4(r6)
1253     #endif
1254    
1255     lp = (uint32 *)(ROM_BASE + 0x312b9c); // Always restore FPU state
1256     while (ntohl(*lp) != 0x7c00092d) lp++;
1257     lp--;
1258     *lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff)); // bl 0x00312ddc
1259    
1260     lp = (uint32 *)(ROM_BASE + 0x312a68); // Don't activate 68k exception table
1261     while (ntohl(*lp) != 0x39010360) lp++;
1262     *lp++ = htonl(0x39000000 + MODE_68K); // li r8,MODE_68K
1263     *lp = htonl(0x91000000 + XLM_RUN_MODE); // stw r8,XLM_RUN_MODE
1264    
1265     // Patch 68k emulator trap routine
1266     lp = (uint32 *)(ROM_BASE + 0x312994); // Always restore FPU state
1267     while (ntohl(*lp) != 0x39260040) lp++;
1268     lp--;
1269     *lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff)); // bl 0x00312dd4
1270    
1271     lp = (uint32 *)(ROM_BASE + 0x312dd8); // Don't modify MSR to turn on FPU
1272     while (ntohl(*lp) != 0x810600e4) lp++;
1273     lp--;
1274     *lp++ = htonl(POWERPC_NOP);
1275     lp += 2;
1276     *lp++ = htonl(POWERPC_NOP);
1277     lp++;
1278     *lp++ = htonl(POWERPC_NOP);
1279     *lp++ = htonl(POWERPC_NOP);
1280     *lp = htonl(POWERPC_NOP);
1281    
1282     // Patch trap return routine
1283     lp = (uint32 *)(ROM_BASE + 0x312c20);
1284     while (ntohl(*lp) != 0x7d5a03a6) lp++;
1285     *lp++ = htonl(0x7d4903a6); // mtctr r10
1286     *lp++ = htonl(0x7daff120); // mtcr r13
1287     *lp = htonl(0x48000000 + 0x8000 - (((uint32)lp - ROM_BASE) & 0xffff)); // b ROM_BASE+0x318000
1288     uint32 xlp = ((uint32)(lp+1) - ROM_BASE) & 0xffff;
1289    
1290     lp = (uint32 *)(ROM_BASE + 0x312c50); // Replace rfi
1291     while (ntohl(*lp) != 0x4c000064) lp++;
1292     *lp = htonl(POWERPC_BCTR);
1293    
1294     lp = (uint32 *)(ROM_BASE + 0x318000);
1295     *lp++ = htonl(0x81400000 + XLM_IRQ_NEST); // lwz r10,XLM_IRQ_NEST
1296     *lp++ = htonl(0x394affff); // subi r10,r10,1
1297     *lp++ = htonl(0x91400000 + XLM_IRQ_NEST); // stw r10,XLM_IRQ_NEST
1298     *lp = htonl(0x48000000 + ((xlp - 0x800c) & 0x03fffffc)); // b ROM_BASE+0x312c2c
1299     /*
1300     // Disable FE0A/FE06 opcodes
1301     lp = (uint32 *)(ROM_BASE + 0x3144ac);
1302     *lp++ = htonl(POWERPC_NOP);
1303     *lp += 8;
1304     */
1305     return true;
1306     }
1307    
1308    
1309     /*
1310     * 68k boot routine patches
1311     */
1312    
1313     static bool patch_68k(void)
1314     {
1315     uint32 *lp;
1316     uint16 *wp;
1317     uint8 *bp;
1318     uint32 base;
1319    
1320     // Remove 68k RESET instruction
1321     static const uint8 reset_dat[] = {0x4e, 0x70};
1322     if ((base = find_rom_data(0xc8, 0x120, reset_dat, sizeof(reset_dat))) == 0) return false;
1323     D(bug("reset %08lx\n", base));
1324     wp = (uint16 *)(ROM_BASE + base);
1325     *wp = htons(M68K_NOP);
1326    
1327     // Fake reading PowerMac ID (via Universal)
1328     static const uint8 powermac_id_dat[] = {0x45, 0xf9, 0x5f, 0xff, 0xff, 0xfc, 0x20, 0x12, 0x72, 0x00};
1329     if ((base = find_rom_data(0xe000, 0x15000, powermac_id_dat, sizeof(powermac_id_dat))) == 0) return false;
1330     D(bug("powermac_id %08lx\n", base));
1331     wp = (uint16 *)(ROM_BASE + base);
1332     *wp++ = htons(0x203c); // move.l #id,d0
1333     *wp++ = htons(0);
1334     // if (ROMType == ROMTYPE_NEWWORLD)
1335     // *wp++ = htons(0x3035); // (PowerMac 9500 ID)
1336     // else
1337     *wp++ = htons(0x3020); // (PowerMac 9500 ID)
1338     *wp++ = htons(0xb040); // cmp.w d0,d0
1339     *wp = htons(0x4ed6); // jmp (a6)
1340    
1341     // Patch UniversalInfo
1342     if (ROMType == ROMTYPE_NEWWORLD) {
1343     static const uint8 univ_info_dat[] = {0x3f, 0xff, 0x04, 0x00};
1344 gbeauche 1.4 if ((base = find_rom_data(0x14000, 0x18000, univ_info_dat, sizeof(univ_info_dat))) == 0) return false;
1345 cebix 1.1 D(bug("universal_info %08lx\n", base));
1346     lp = (uint32 *)(ROM_BASE + base - 0x14);
1347     lp[0x00 >> 2] = htonl(ADDR_MAP_PATCH_SPACE - (base - 0x14));
1348     lp[0x10 >> 2] = htonl(0xcc003d11); // Make it like the PowerMac 9500 UniversalInfo
1349     lp[0x14 >> 2] = htonl(0x3fff0401);
1350     lp[0x18 >> 2] = htonl(0x0300001c);
1351     lp[0x1c >> 2] = htonl(0x000108c4);
1352     lp[0x24 >> 2] = htonl(0xc301bf26);
1353     lp[0x28 >> 2] = htonl(0x00000861);
1354     lp[0x58 >> 2] = htonl(0x30200000);
1355     lp[0x60 >> 2] = htonl(0x0000003d);
1356     } else if (ROMType == ROMTYPE_ZANZIBAR) {
1357     base = 0x12b70;
1358     lp = (uint32 *)(ROM_BASE + base - 0x14);
1359     lp[0x00 >> 2] = htonl(ADDR_MAP_PATCH_SPACE - (base - 0x14));
1360     lp[0x10 >> 2] = htonl(0xcc003d11); // Make it like the PowerMac 9500 UniversalInfo
1361     lp[0x14 >> 2] = htonl(0x3fff0401);
1362     lp[0x18 >> 2] = htonl(0x0300001c);
1363     lp[0x1c >> 2] = htonl(0x000108c4);
1364     lp[0x24 >> 2] = htonl(0xc301bf26);
1365     lp[0x28 >> 2] = htonl(0x00000861);
1366     lp[0x58 >> 2] = htonl(0x30200000);
1367     lp[0x60 >> 2] = htonl(0x0000003d);
1368     }
1369    
1370     // Construct AddrMap for NewWorld ROM
1371     if (ROMType == ROMTYPE_NEWWORLD || ROMType == ROMTYPE_ZANZIBAR) {
1372     lp = (uint32 *)(ROM_BASE + ADDR_MAP_PATCH_SPACE);
1373     memset(lp - 10, 0, 0x128);
1374     lp[-10] = htonl(0x0300001c);
1375     lp[-9] = htonl(0x000108c4);
1376     lp[-4] = htonl(0x00300000);
1377     lp[-2] = htonl(0x11010000);
1378     lp[-1] = htonl(0xf8000000);
1379     lp[0] = htonl(0xffc00000);
1380     lp[2] = htonl(0xf3016000);
1381     lp[3] = htonl(0xf3012000);
1382     lp[4] = htonl(0xf3012000);
1383     lp[24] = htonl(0xf3018000);
1384     lp[25] = htonl(0xf3010000);
1385     lp[34] = htonl(0xf3011000);
1386     lp[38] = htonl(0xf3015000);
1387     lp[39] = htonl(0xf3014000);
1388     lp[43] = htonl(0xf3000000);
1389     lp[48] = htonl(0xf8000000);
1390     }
1391    
1392     // Don't initialize VIA (via Universal)
1393     static const uint8 via_init_dat[] = {0x08, 0x00, 0x00, 0x02, 0x67, 0x00, 0x00, 0x2c, 0x24, 0x68, 0x00, 0x08};
1394     if ((base = find_rom_data(0xe000, 0x15000, via_init_dat, sizeof(via_init_dat))) == 0) return false;
1395     D(bug("via_init %08lx\n", base));
1396     wp = (uint16 *)(ROM_BASE + base + 4);
1397     *wp = htons(0x6000); // bra
1398    
1399     static const uint8 via_init2_dat[] = {0x24, 0x68, 0x00, 0x08, 0x00, 0x12, 0x00, 0x30, 0x4e, 0x71};
1400     if ((base = find_rom_data(0xa000, 0x10000, via_init2_dat, sizeof(via_init2_dat))) == 0) return false;
1401     D(bug("via_init2 %08lx\n", base));
1402     wp = (uint16 *)(ROM_BASE + base);
1403     *wp = htons(0x4ed6); // jmp (a6)
1404    
1405     static const uint8 via_init3_dat[] = {0x22, 0x68, 0x00, 0x08, 0x28, 0x3c, 0x20, 0x00, 0x01, 0x00};
1406     if ((base = find_rom_data(0xa000, 0x10000, via_init3_dat, sizeof(via_init3_dat))) == 0) return false;
1407     D(bug("via_init3 %08lx\n", base));
1408     wp = (uint16 *)(ROM_BASE + base);
1409     *wp = htons(0x4ed6); // jmp (a6)
1410    
1411     // Don't RunDiags, get BootGlobs pointer directly
1412     if (ROMType == ROMTYPE_NEWWORLD) {
1413     static const uint8 run_diags_dat[] = {0x60, 0xff, 0x00, 0x0c};
1414     if ((base = find_rom_data(0x110, 0x128, run_diags_dat, sizeof(run_diags_dat))) == 0) return false;
1415     D(bug("run_diags %08lx\n", base));
1416     wp = (uint16 *)(ROM_BASE + base);
1417     *wp++ = htons(0x4df9); // lea xxx,a6
1418     *wp++ = htons((RAMBase + RAMSize - 0x1c) >> 16);
1419     *wp = htons((RAMBase + RAMSize - 0x1c) & 0xffff);
1420     } else {
1421     static const uint8 run_diags_dat[] = {0x74, 0x00, 0x2f, 0x0e};
1422     if ((base = find_rom_data(0xd0, 0xf0, run_diags_dat, sizeof(run_diags_dat))) == 0) return false;
1423     D(bug("run_diags %08lx\n", base));
1424     wp = (uint16 *)(ROM_BASE + base - 6);
1425     *wp++ = htons(0x4df9); // lea xxx,a6
1426     *wp++ = htons((RAMBase + RAMSize - 0x1c) >> 16);
1427     *wp = htons((RAMBase + RAMSize - 0x1c) & 0xffff);
1428     }
1429    
1430     // Replace NVRAM routines
1431     static const uint8 nvram1_dat[] = {0x48, 0xe7, 0x01, 0x0e, 0x24, 0x68, 0x00, 0x08, 0x08, 0x83, 0x00, 0x1f};
1432     if ((base = find_rom_data(0x7000, 0xc000, nvram1_dat, sizeof(nvram1_dat))) == 0) return false;
1433     D(bug("nvram1 %08lx\n", base));
1434     wp = (uint16 *)(ROM_BASE + base);
1435     *wp++ = htons(M68K_EMUL_OP_XPRAM1);
1436     *wp = htons(M68K_RTS);
1437    
1438     if (ROMType == ROMTYPE_NEWWORLD) {
1439     static const uint8 nvram2_dat[] = {0x48, 0xe7, 0x1c, 0xe0, 0x4f, 0xef, 0xff, 0xb4};
1440     if ((base = find_rom_data(0xa000, 0xd000, nvram2_dat, sizeof(nvram2_dat))) == 0) return false;
1441     D(bug("nvram2 %08lx\n", base));
1442     wp = (uint16 *)(ROM_BASE + base);
1443     *wp++ = htons(M68K_EMUL_OP_XPRAM2);
1444     *wp = htons(0x4ed3); // jmp (a3)
1445    
1446     static const uint8 nvram3_dat[] = {0x48, 0xe7, 0xdc, 0xe0, 0x4f, 0xef, 0xff, 0xb4};
1447     if ((base = find_rom_data(0xa000, 0xd000, nvram3_dat, sizeof(nvram3_dat))) == 0) return false;
1448     D(bug("nvram3 %08lx\n", base));
1449     wp = (uint16 *)(ROM_BASE + base);
1450     *wp++ = htons(M68K_EMUL_OP_XPRAM3);
1451     *wp = htons(0x4ed3); // jmp (a3)
1452    
1453     static const uint8 nvram4_dat[] = {0x4e, 0x56, 0xff, 0xa8, 0x48, 0xe7, 0x1f, 0x38, 0x16, 0x2e, 0x00, 0x13};
1454     if ((base = find_rom_data(0xa000, 0xd000, nvram4_dat, sizeof(nvram4_dat))) == 0) return false;
1455     D(bug("nvram4 %08lx\n", base));
1456     wp = (uint16 *)(ROM_BASE + base + 16);
1457     *wp++ = htons(0x1a2e); // move.b ($000f,a6),d5
1458     *wp++ = htons(0x000f);
1459     *wp++ = htons(M68K_EMUL_OP_NVRAM3);
1460     *wp++ = htons(0x4cee); // movem.l ($ff88,a6),d3-d7/a2-a4
1461     *wp++ = htons(0x1cf8);
1462     *wp++ = htons(0xff88);
1463     *wp++ = htons(0x4e5e); // unlk a6
1464     *wp = htons(M68K_RTS);
1465    
1466     static const uint8 nvram5_dat[] = {0x0c, 0x80, 0x03, 0x00, 0x00, 0x00, 0x66, 0x0a, 0x70, 0x00, 0x21, 0xf8, 0x02, 0x0c, 0x01, 0xe4};
1467     if ((base = find_rom_data(0xa000, 0xd000, nvram5_dat, sizeof(nvram5_dat))) == 0) return false;
1468     D(bug("nvram5 %08lx\n", base));
1469     wp = (uint16 *)(ROM_BASE + base + 6);
1470     *wp = htons(M68K_NOP);
1471    
1472     static const uint8 nvram6_dat[] = {0x2f, 0x0a, 0x24, 0x48, 0x4f, 0xef, 0xff, 0xa0, 0x20, 0x0f};
1473     if ((base = find_rom_data(0x9000, 0xb000, nvram6_dat, sizeof(nvram6_dat))) == 0) return false;
1474     D(bug("nvram6 %08lx\n", base));
1475     wp = (uint16 *)(ROM_BASE + base);
1476     *wp++ = htons(0x7000); // moveq #0,d0
1477     *wp++ = htons(0x2080); // move.l d0,(a0)
1478     *wp++ = htons(0x4228); // clr.b 4(a0)
1479     *wp++ = htons(0x0004);
1480     *wp = htons(M68K_RTS);
1481    
1482     static const uint8 nvram7_dat[] = {0x42, 0x2a, 0x00, 0x04, 0x4f, 0xef, 0x00, 0x60, 0x24, 0x5f, 0x4e, 0x75, 0x4f, 0xef, 0xff, 0xa0, 0x20, 0x0f};
1483     base = find_rom_data(0x9000, 0xb000, nvram7_dat, sizeof(nvram7_dat));
1484     if (base) {
1485     D(bug("nvram7 %08lx\n", base));
1486     wp = (uint16 *)(ROM_BASE + base + 12);
1487     *wp = htons(M68K_RTS);
1488     }
1489     } else {
1490     static const uint8 nvram2_dat[] = {0x4e, 0xd6, 0x06, 0x41, 0x13, 0x00};
1491     if ((base = find_rom_data(0x7000, 0xb000, nvram2_dat, sizeof(nvram2_dat))) == 0) return false;
1492     D(bug("nvram2 %08lx\n", base));
1493     wp = (uint16 *)(ROM_BASE + base + 2);
1494     *wp++ = htons(M68K_EMUL_OP_XPRAM2);
1495     *wp = htons(0x4ed3); // jmp (a3)
1496    
1497     static const uint32 nvram3_loc[] = {0x582f0, 0xa0a0, 0x7e50, 0xa1d0, 0};
1498     wp = (uint16 *)(ROM_BASE + nvram3_loc[ROMType]);
1499     *wp++ = htons(0x202f); // move.l 4(sp),d0
1500     *wp++ = htons(0x0004);
1501     *wp++ = htons(M68K_EMUL_OP_NVRAM1);
1502     if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_GAZELLE)
1503     *wp = htons(M68K_RTS);
1504     else {
1505     *wp++ = htons(0x1f40); // move.b d0,8(sp)
1506     *wp++ = htons(0x0008);
1507     *wp++ = htons(0x4e74); // rtd #4
1508     *wp = htons(0x0004);
1509     }
1510    
1511     static const uint32 nvram4_loc[] = {0x58460, 0xa0f0, 0x7f40, 0xa220, 0};
1512     wp = (uint16 *)(ROM_BASE + nvram4_loc[ROMType]);
1513     if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_GAZELLE) {
1514     *wp++ = htons(0x202f); // move.l 4(sp),d0
1515     *wp++ = htons(0x0004);
1516     *wp++ = htons(0x122f); // move.b 11(sp),d1
1517     *wp++ = htons(0x000b);
1518     *wp++ = htons(M68K_EMUL_OP_NVRAM2);
1519     *wp = htons(M68K_RTS);
1520     } else {
1521     *wp++ = htons(0x202f); // move.l 6(sp),d0
1522     *wp++ = htons(0x0006);
1523     *wp++ = htons(0x122f); // move.b 4(sp),d1
1524     *wp++ = htons(0x0004);
1525     *wp++ = htons(M68K_EMUL_OP_NVRAM2);
1526     *wp++ = htons(0x4e74); // rtd #6
1527     *wp = htons(0x0006);
1528     }
1529     }
1530    
1531     // Fix MemTop/BootGlobs during system startup
1532     static const uint8 mem_top_dat[] = {0x2c, 0x6c, 0xff, 0xec, 0x2a, 0x4c, 0xdb, 0xec, 0xff, 0xf4};
1533     if ((base = find_rom_data(0x120, 0x180, mem_top_dat, sizeof(mem_top_dat))) == 0) return false;
1534     D(bug("mem_top %08lx\n", base));
1535     wp = (uint16 *)(ROM_BASE + base);
1536     *wp++ = htons(M68K_EMUL_OP_FIX_MEMTOP);
1537     *wp = htons(M68K_NOP);
1538    
1539     // Don't initialize SCC (via 0x1ac)
1540     static const uint8 scc_init_dat[] = {0x48, 0xe7, 0x38, 0xfe};
1541     if ((base = find_rom_data(0x190, 0x1f0, scc_init_dat, sizeof(scc_init_dat))) == 0) return false;
1542     D(bug("scc_init %08lx\n", base));
1543     wp = (uint16 *)(ROM_BASE + base - 2);
1544     wp = (uint16 *)(ROM_BASE + ntohs(*wp) + base - 2);
1545     *wp++ = htons(M68K_EMUL_OP_RESET);
1546     *wp = htons(M68K_RTS);
1547    
1548     // Don't EnableExtCache (via 0x1f6) and don't DisableIntSources(via 0x1fc)
1549     static const uint8 ext_cache_dat[] = {0x4e, 0x7b, 0x00, 0x02};
1550     if ((base = find_rom_data(0x1d0, 0x230, ext_cache_dat, sizeof(ext_cache_dat))) == 0) return false;
1551     D(bug("ext_cache %08lx\n", base));
1552     lp = (uint32 *)(ROM_BASE + base + 6);
1553     wp = (uint16 *)(ROM_BASE + ntohl(*lp) + base + 6);
1554     *wp = htons(M68K_RTS);
1555     lp = (uint32 *)(ROM_BASE + base + 12);
1556     wp = (uint16 *)(ROM_BASE + ntohl(*lp) + base + 12);
1557     *wp = htons(M68K_RTS);
1558    
1559     // Fake CPU speed test (SetupTimeK)
1560     static const uint8 timek_dat[] = {0x0c, 0x38, 0x00, 0x04, 0x01, 0x2f, 0x6d, 0x3c};
1561     if ((base = find_rom_data(0x400, 0x500, timek_dat, sizeof(timek_dat))) == 0) return false;
1562     D(bug("timek %08lx\n", base));
1563     wp = (uint16 *)(ROM_BASE + base);
1564     *wp++ = htons(0x31fc); // move.w #xxx,TimeDBRA
1565     *wp++ = htons(100);
1566     *wp++ = htons(0x0d00);
1567     *wp++ = htons(0x31fc); // move.w #xxx,TimeSCCDBRA
1568     *wp++ = htons(100);
1569     *wp++ = htons(0x0d02);
1570     *wp++ = htons(0x31fc); // move.w #xxx,TimeSCSIDBRA
1571     *wp++ = htons(100);
1572     *wp++ = htons(0x0b24);
1573     *wp++ = htons(0x31fc); // move.w #xxx,TimeRAMDBRA
1574     *wp++ = htons(100);
1575     *wp++ = htons(0x0cea);
1576     *wp = htons(M68K_RTS);
1577    
1578     // Relocate jump tables ($2000..)
1579     static const uint8 jump_tab_dat[] = {0x41, 0xfa, 0x00, 0x0e, 0x21, 0xc8, 0x20, 0x10, 0x4e, 0x75};
1580     if ((base = find_rom_data(0x3000, 0x6000, jump_tab_dat, sizeof(jump_tab_dat))) == 0) return false;
1581     D(bug("jump_tab %08lx\n", base));
1582     lp = (uint32 *)(ROM_BASE + base + 16);
1583     for (;;) {
1584     D(bug(" %08lx\n", (uint32)lp - ROM_BASE));
1585     while ((ntohl(*lp) & 0xff000000) == 0xff000000) {
1586     *lp = htonl((ntohl(*lp) & (ROM_SIZE-1)) + ROM_BASE);
1587     lp++;
1588     }
1589     while (!ntohl(*lp)) lp++;
1590     if (ntohl(*lp) != 0x41fa000e)
1591     break;
1592     lp += 4;
1593     }
1594    
1595     // Create SysZone at start of Mac RAM (SetSysAppZone, via 0x22a)
1596     static const uint8 sys_zone_dat[] = {0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x40, 0x00};
1597     if ((base = find_rom_data(0x600, 0x900, sys_zone_dat, sizeof(sys_zone_dat))) == 0) return false;
1598     D(bug("sys_zone %08lx\n", base));
1599     lp = (uint32 *)(ROM_BASE + base);
1600     *lp++ = htonl(RAMBase ? RAMBase : 0x3000);
1601     *lp = htonl(RAMBase ? RAMBase + 0x1800 : 0x4800);
1602    
1603     // Set boot stack at RAMBase+4MB and fix logical/physical RAM size (CompBootStack)
1604     // The RAM size fix must be done after InitMemMgr!
1605     static const uint8 boot_stack_dat[] = {0x08, 0x38, 0x00, 0x06, 0x24, 0x0b};
1606     if ((base = find_rom_data(0x580, 0x800, boot_stack_dat, sizeof(boot_stack_dat))) == 0) return false;
1607     D(bug("boot_stack %08lx\n", base));
1608     wp = (uint16 *)(ROM_BASE + base);
1609     *wp++ = htons(0x207c); // move.l #RAMBase+0x3ffffe,a0
1610     *wp++ = htons((RAMBase + 0x3ffffe) >> 16);
1611     *wp++ = htons((RAMBase + 0x3ffffe) & 0xffff);
1612     *wp++ = htons(M68K_EMUL_OP_FIX_MEMSIZE);
1613     *wp = htons(M68K_RTS);
1614    
1615     // Get PowerPC page size (InitVMemMgr, via 0x240)
1616     static const uint8 page_size_dat[] = {0x20, 0x30, 0x81, 0xf2, 0x5f, 0xff, 0xef, 0xd8, 0x00, 0x10};
1617     if ((base = find_rom_data(0xb000, 0x12000, page_size_dat, sizeof(page_size_dat))) == 0) return false;
1618     D(bug("page_size %08lx\n", base));
1619     wp = (uint16 *)(ROM_BASE + base);
1620     *wp++ = htons(0x203c); // move.l #$1000,d0
1621     *wp++ = htons(0);
1622     *wp++ = htons(0x1000);
1623     *wp++ = htons(M68K_NOP);
1624     *wp = htons(M68K_NOP);
1625    
1626     // Gestalt PowerPC page size, RAM size (InitGestalt, via 0x25c)
1627     static const uint8 page_size2_dat[] = {0x26, 0x79, 0x5f, 0xff, 0xef, 0xd8, 0x25, 0x6b, 0x00, 0x10, 0x00, 0x1e};
1628     if ((base = find_rom_data(0x50000, 0x70000, page_size2_dat, sizeof(page_size2_dat))) == 0) return false;
1629     D(bug("page_size2 %08lx\n", base));
1630     wp = (uint16 *)(ROM_BASE + base);
1631     *wp++ = htons(0x257c); // move.l #$1000,$1e(a2)
1632     *wp++ = htons(0);
1633     *wp++ = htons(0x1000);
1634     *wp++ = htons(0x001e);
1635     *wp++ = htons(0x157c); // move.b #PVR,$1d(a2)
1636     *wp++ = htons(PVR >> 16);
1637     *wp++ = htons(0x001d);
1638     *wp++ = htons(0x263c); // move.l #RAMSize,d3
1639     *wp++ = htons(RAMSize >> 16);
1640     *wp++ = htons(RAMSize & 0xffff);
1641     *wp++ = htons(M68K_NOP);
1642     *wp++ = htons(M68K_NOP);
1643     *wp = htons(M68K_NOP);
1644     if (ROMType == ROMTYPE_NEWWORLD)
1645     wp = (uint16 *)(ROM_BASE + base + 0x4a);
1646     else
1647     wp = (uint16 *)(ROM_BASE + base + 0x28);
1648     *wp++ = htons(M68K_NOP);
1649     *wp = htons(M68K_NOP);
1650    
1651     // Gestalt CPU/bus clock speed (InitGestalt, via 0x25c)
1652     if (ROMType == ROMTYPE_ZANZIBAR) {
1653     wp = (uint16 *)(ROM_BASE + 0x5d87a);
1654     *wp++ = htons(0x203c); // move.l #Hz,d0
1655     *wp++ = htons(BusClockSpeed >> 16);
1656     *wp++ = htons(BusClockSpeed & 0xffff);
1657     *wp++ = htons(M68K_NOP);
1658     *wp = htons(M68K_NOP);
1659     wp = (uint16 *)(ROM_BASE + 0x5d888);
1660     *wp++ = htons(0x203c); // move.l #Hz,d0
1661     *wp++ = htons(CPUClockSpeed >> 16);
1662     *wp++ = htons(CPUClockSpeed & 0xffff);
1663     *wp++ = htons(M68K_NOP);
1664     *wp = htons(M68K_NOP);
1665     }
1666    
1667     // Don't write to GC interrupt mask register (via 0x262)
1668     if (ROMType != ROMTYPE_NEWWORLD) {
1669     static const uint8 gc_mask_dat[] = {0x83, 0xa8, 0x00, 0x24, 0x4e, 0x71};
1670     if ((base = find_rom_data(0x13000, 0x20000, gc_mask_dat, sizeof(gc_mask_dat))) == 0) return false;
1671     D(bug("gc_mask %08lx\n", base));
1672     wp = (uint16 *)(ROM_BASE + base);
1673     *wp++ = htons(M68K_NOP);
1674     *wp = htons(M68K_NOP);
1675     wp = (uint16 *)(ROM_BASE + base + 0x40);
1676     *wp++ = htons(M68K_NOP);
1677     *wp = htons(M68K_NOP);
1678     wp = (uint16 *)(ROM_BASE + base + 0x78);
1679     *wp++ = htons(M68K_NOP);
1680     *wp = htons(M68K_NOP);
1681     wp = (uint16 *)(ROM_BASE + base + 0x96);
1682     *wp++ = htons(M68K_NOP);
1683     *wp = htons(M68K_NOP);
1684    
1685     static const uint8 gc_mask2_dat[] = {0x02, 0xa8, 0x00, 0x00, 0x00, 0x80, 0x00, 0x24};
1686     if ((base = find_rom_data(0x13000, 0x20000, gc_mask2_dat, sizeof(gc_mask2_dat))) == 0) return false;
1687     D(bug("gc_mask2 %08lx\n", base));
1688     wp = (uint16 *)(ROM_BASE + base);
1689     for (int i=0; i<5; i++) {
1690     *wp++ = htons(M68K_NOP);
1691     *wp++ = htons(M68K_NOP);
1692     *wp++ = htons(M68K_NOP);
1693     *wp++ = htons(M68K_NOP);
1694     wp += 2;
1695     }
1696     if (ROMType == ROMTYPE_ZANZIBAR) {
1697     for (int i=0; i<6; i++) {
1698     *wp++ = htons(M68K_NOP);
1699     *wp++ = htons(M68K_NOP);
1700     *wp++ = htons(M68K_NOP);
1701     *wp++ = htons(M68K_NOP);
1702     wp += 2;
1703     }
1704     }
1705     }
1706    
1707     // Don't initialize Cuda (via 0x274)
1708     static const uint8 cuda_init_dat[] = {0x08, 0xa9, 0x00, 0x04, 0x16, 0x00, 0x4e, 0x71, 0x13, 0x7c, 0x00, 0x84, 0x1c, 0x00, 0x4e, 0x71};
1709     if ((base = find_rom_data(0xa000, 0x12000, cuda_init_dat, sizeof(cuda_init_dat))) == 0) return false;
1710     D(bug("cuda_init %08lx\n", base));
1711     wp = (uint16 *)(ROM_BASE + base);
1712     *wp++ = htons(M68K_NOP);
1713     *wp++ = htons(M68K_NOP);
1714     *wp++ = htons(M68K_NOP);
1715     *wp++ = htons(M68K_NOP);
1716     *wp++ = htons(M68K_NOP);
1717     *wp++ = htons(M68K_NOP);
1718     *wp = htons(M68K_NOP);
1719    
1720     // Patch GetCPUSpeed (via 0x27a) (some ROMs have two of them)
1721     static const uint8 cpu_speed_dat[] = {0x20, 0x30, 0x81, 0xf2, 0x5f, 0xff, 0xef, 0xd8, 0x00, 0x04, 0x4c, 0x7c};
1722 gbeauche 1.4 if ((base = find_rom_data(0x6000, 0xa000, cpu_speed_dat, sizeof(cpu_speed_dat))) == 0) return false;
1723 cebix 1.1 D(bug("cpu_speed %08lx\n", base));
1724     wp = (uint16 *)(ROM_BASE + base);
1725     *wp++ = htons(0x203c); // move.l #(MHz<<16)|MHz,d0
1726     *wp++ = htons(CPUClockSpeed / 1000000);
1727     *wp++ = htons(CPUClockSpeed / 1000000);
1728     *wp = htons(M68K_RTS);
1729 gbeauche 1.4 if ((base = find_rom_data(base, 0xa000, cpu_speed_dat, sizeof(cpu_speed_dat))) != 0) {
1730 cebix 1.1 D(bug("cpu_speed2 %08lx\n", base));
1731     wp = (uint16 *)(ROM_BASE + base);
1732     *wp++ = htons(0x203c); // move.l #(MHz<<16)|MHz,d0
1733     *wp++ = htons(CPUClockSpeed / 1000000);
1734     *wp++ = htons(CPUClockSpeed / 1000000);
1735     *wp = htons(M68K_RTS);
1736     }
1737    
1738     // Don't poke VIA in InitTimeMgr (via 0x298)
1739     static const uint8 time_via_dat[] = {0x40, 0xe7, 0x00, 0x7c, 0x07, 0x00, 0x28, 0x78, 0x01, 0xd4, 0x43, 0xec, 0x10, 0x00};
1740     if ((base = find_rom_data(0x30000, 0x40000, time_via_dat, sizeof(time_via_dat))) == 0) return false;
1741     D(bug("time_via %08lx\n", base));
1742     wp = (uint16 *)(ROM_BASE + base);
1743     *wp++ = htons(0x4cdf); // movem.l (sp)+,d0-d5/a0-a4
1744     *wp++ = htons(0x1f3f);
1745     *wp = htons(M68K_RTS);
1746    
1747     // Don't read from 0xff800000 (Name Registry, Open Firmware?) (via 0x2a2)
1748     // Remove this if FE03 works!!
1749     static const uint8 open_firmware_dat[] = {0x2f, 0x79, 0xff, 0x80, 0x00, 0x00, 0x00, 0xfc};
1750     if ((base = find_rom_data(0x48000, 0x58000, open_firmware_dat, sizeof(open_firmware_dat))) == 0) return false;
1751     D(bug("open_firmware %08lx\n", base));
1752     wp = (uint16 *)(ROM_BASE + base);
1753     *wp++ = htons(0x2f7c); // move.l #deadbeef,0xfc(a7)
1754     *wp++ = htons(0xdead);
1755     *wp++ = htons(0xbeef);
1756     *wp = htons(0x00fc);
1757     wp = (uint16 *)(ROM_BASE + base + 0x1a);
1758     *wp++ = htons(M68K_NOP); // (FE03 opcode, tries to jump to 0xdeadbeef)
1759     *wp = htons(M68K_NOP);
1760    
1761     // Don't EnableExtCache (via 0x2b2)
1762     static const uint8 ext_cache2_dat[] = {0x4f, 0xef, 0xff, 0xec, 0x20, 0x4f, 0x10, 0xbc, 0x00, 0x01, 0x11, 0x7c, 0x00, 0x1b};
1763     if ((base = find_rom_data(0x13000, 0x20000, ext_cache2_dat, sizeof(ext_cache2_dat))) == 0) return false;
1764     D(bug("ext_cache2 %08lx\n", base));
1765     wp = (uint16 *)(ROM_BASE + base);
1766     *wp = htons(M68K_RTS);
1767    
1768     // Don't install Time Manager task for 60Hz interrupt (Enable60HzInts, via 0x2b8)
1769     if (ROMType == ROMTYPE_NEWWORLD) {
1770     static const uint8 tm_task_dat[] = {0x30, 0x3c, 0x4e, 0x2b, 0xa9, 0xc9};
1771     if ((base = find_rom_data(0x2e0, 0x320, tm_task_dat, sizeof(tm_task_dat))) == 0) return false;
1772     D(bug("tm_task %08lx\n", base));
1773     wp = (uint16 *)(ROM_BASE + base + 28);
1774     *wp++ = htons(M68K_NOP);
1775     *wp++ = htons(M68K_NOP);
1776     *wp++ = htons(M68K_NOP);
1777     *wp++ = htons(M68K_NOP);
1778     *wp++ = htons(M68K_NOP);
1779     *wp = htons(M68K_NOP);
1780     } else {
1781     static const uint8 tm_task_dat[] = {0x20, 0x3c, 0x73, 0x79, 0x73, 0x61};
1782     if ((base = find_rom_data(0x280, 0x300, tm_task_dat, sizeof(tm_task_dat))) == 0) return false;
1783     D(bug("tm_task %08lx\n", base));
1784     wp = (uint16 *)(ROM_BASE + base - 6);
1785     *wp++ = htons(M68K_NOP);
1786     *wp++ = htons(M68K_NOP);
1787     *wp = htons(M68K_NOP);
1788     }
1789    
1790     // Don't read PVR from 0x5fffef80 in DriverServicesLib (via 0x316)
1791     if (ROMType != ROMTYPE_NEWWORLD) {
1792     uint32 dsl_offset = find_rom_resource(FOURCC('n','l','i','b'), -16401);
1793     if (ROMType == ROMTYPE_ZANZIBAR) {
1794     static const uint8 dsl_pvr_dat[] = {0x40, 0x82, 0x00, 0x40, 0x38, 0x60, 0xef, 0x80, 0x3c, 0x63, 0x60, 0x00, 0x80, 0x83, 0x00, 0x00, 0x54, 0x84, 0x84, 0x3e};
1795     if ((base = find_rom_data(dsl_offset, dsl_offset + 0x6000, dsl_pvr_dat, sizeof(dsl_pvr_dat))) == 0) return false;
1796     } else {
1797     static const uint8 dsl_pvr_dat[] = {0x3b, 0xc3, 0x00, 0x00, 0x30, 0x84, 0xff, 0xa0, 0x40, 0x82, 0x00, 0x44, 0x80, 0x84, 0xef, 0xe0, 0x54, 0x84, 0x84, 0x3e};
1798     if ((base = find_rom_data(dsl_offset, dsl_offset + 0x6000, dsl_pvr_dat, sizeof(dsl_pvr_dat))) == 0) return false;
1799     }
1800     D(bug("dsl_pvr %08lx\n", base));
1801     lp = (uint32 *)(ROM_BASE + base + 12);
1802     *lp = htonl(0x3c800000 | (PVR >> 16)); // lis r4,PVR
1803    
1804     // Don't read bus clock from 0x5fffef88 in DriverServicesLib (via 0x316)
1805     if (ROMType == ROMTYPE_ZANZIBAR) {
1806     static const uint8 dsl_bus_dat[] = {0x81, 0x07, 0x00, 0x00, 0x39, 0x20, 0x42, 0x40, 0x81, 0x62, 0xff, 0x20};
1807     if ((base = find_rom_data(dsl_offset, dsl_offset + 0x6000, dsl_bus_dat, sizeof(dsl_bus_dat))) == 0) return false;
1808     D(bug("dsl_bus %08lx\n", base));
1809     lp = (uint32 *)(ROM_BASE + base);
1810     *lp = htonl(0x81000000 + XLM_BUS_CLOCK); // lwz r8,(bus clock speed)
1811     } else {
1812     static const uint8 dsl_bus_dat[] = {0x80, 0x83, 0xef, 0xe8, 0x80, 0x62, 0x00, 0x10, 0x7c, 0x04, 0x03, 0x96};
1813     if ((base = find_rom_data(dsl_offset, dsl_offset + 0x6000, dsl_bus_dat, sizeof(dsl_bus_dat))) == 0) return false;
1814     D(bug("dsl_bus %08lx\n", base));
1815     lp = (uint32 *)(ROM_BASE + base);
1816     *lp = htonl(0x80800000 + XLM_BUS_CLOCK); // lwz r4,(bus clock speed)
1817     }
1818     }
1819    
1820     // Don't open InterruptTreeTNT in MotherBoardHAL init in DriverServicesLib init
1821     if (ROMType == ROMTYPE_ZANZIBAR) {
1822     lp = (uint32 *)(ROM_BASE + find_rom_resource(FOURCC('n','l','i','b'), -16408) + 0x16c);
1823     *lp = htonl(0x38600000); // li r3,0
1824     }
1825    
1826     // Patch Name Registry
1827     static const uint8 name_reg_dat[] = {0x70, 0xff, 0xab, 0xeb};
1828     if ((base = find_rom_data(0x300, 0x380, name_reg_dat, sizeof(name_reg_dat))) == 0) return false;
1829     D(bug("name_reg %08lx\n", base));
1830     wp = (uint16 *)(ROM_BASE + base);
1831     *wp = htons(M68K_EMUL_OP_NAME_REGISTRY);
1832    
1833     #if DISABLE_SCSI
1834     // Fake SCSI Manager
1835     // Remove this if SCSI Manager works!!
1836     static const uint8 scsi_mgr_a_dat[] = {0x4e, 0x56, 0x00, 0x00, 0x20, 0x3c, 0x00, 0x00, 0x04, 0x0c, 0xa7, 0x1e};
1837     static const uint8 scsi_mgr_b_dat[] = {0x4e, 0x56, 0x00, 0x00, 0x2f, 0x0c, 0x20, 0x3c, 0x00, 0x00, 0x04, 0x0c, 0xa7, 0x1e};
1838     if ((base = find_rom_data(0x1c000, 0x28000, scsi_mgr_a_dat, sizeof(scsi_mgr_a_dat))) == 0) {
1839     if ((base = find_rom_data(0x1c000, 0x28000, scsi_mgr_b_dat, sizeof(scsi_mgr_b_dat))) == 0) return false;
1840     }
1841     D(bug("scsi_mgr %08lx\n", base));
1842     wp = (uint16 *)(ROM_BASE + base);
1843     *wp++ = htons(0x21fc); // move.l #xxx,0x624 (SCSIAtomic)
1844     *wp++ = htons((ROM_BASE + base + 18) >> 16);
1845     *wp++ = htons((ROM_BASE + base + 18) & 0xffff);
1846     *wp++ = htons(0x0624);
1847     *wp++ = htons(0x21fc); // move.l #xxx,0xe54 (SCSIDispatch)
1848     *wp++ = htons((ROM_BASE + base + 22) >> 16);
1849     *wp++ = htons((ROM_BASE + base + 22) & 0xffff);
1850     *wp++ = htons(0x0e54);
1851     *wp++ = htons(M68K_RTS);
1852     *wp++ = htons(M68K_EMUL_OP_SCSI_ATOMIC);
1853     *wp++ = htons(M68K_RTS);
1854     *wp++ = htons(M68K_EMUL_OP_SCSI_DISPATCH);
1855     *wp = htons(0x4ed0); // jmp (a0)
1856     wp = (uint16 *)(ROM_BASE + base + 0x20);
1857     *wp++ = htons(0x7000); // moveq #0,d0
1858     *wp = htons(M68K_RTS);
1859     #endif
1860    
1861     #if DISABLE_SCSI
1862     // Don't access SCSI variables
1863     // Remove this if SCSI Manager works!!
1864     if (ROMType == ROMTYPE_NEWWORLD) {
1865     static const uint8 scsi_var_dat[] = {0x70, 0x01, 0xa0, 0x89, 0x4a, 0x6e, 0xfe, 0xac, 0x4f, 0xef, 0x00, 0x10, 0x66, 0x00};
1866     if ((base = find_rom_data(0x1f500, 0x1f600, scsi_var_dat, sizeof(scsi_var_dat))) != 0) {
1867     D(bug("scsi_var %08lx\n", base));
1868     wp = (uint16 *)(ROM_BASE + base + 12);
1869     *wp = htons(0x6000); // bra
1870     }
1871    
1872     static const uint8 scsi_var2_dat[] = {0x4e, 0x56, 0xfc, 0x58, 0x48, 0xe7, 0x1f, 0x38};
1873     if ((base = find_rom_data(0x1f700, 0x1f800, scsi_var2_dat, sizeof(scsi_var2_dat))) != 0) {
1874     D(bug("scsi_var2 %08lx\n", base));
1875     wp = (uint16 *)(ROM_BASE + base);
1876     *wp++ = htons(0x7000); // moveq #0,d0
1877     *wp = htons(M68K_RTS); // bra
1878     }
1879     }
1880     #endif
1881    
1882     // Don't wait in ADBInit (via 0x36c)
1883     static const uint8 adb_init_dat[] = {0x08, 0x2b, 0x00, 0x05, 0x01, 0x5d, 0x66, 0xf8};
1884     if ((base = find_rom_data(0x31000, 0x3d000, adb_init_dat, sizeof(adb_init_dat))) == 0) return false;
1885     D(bug("adb_init %08lx\n", base));
1886     wp = (uint16 *)(ROM_BASE + base + 6);
1887     *wp = htons(M68K_NOP);
1888    
1889     // Modify check in InitResources() so that addresses >0x80000000 work
1890     static const uint8 init_res_dat[] = {0x4a, 0xb8, 0x0a, 0x50, 0x6e, 0x20};
1891     if ((base = find_rom_data(0x78000, 0x8c000, init_res_dat, sizeof(init_res_dat))) == 0) return false;
1892     D(bug("init_res %08lx\n", base));
1893     bp = (uint8 *)(ROM_BASE + base + 4);
1894     *bp = 0x66;
1895    
1896     // Modify vCheckLoad() so that we can patch resources (68k Resource Manager)
1897     static const uint8 check_load_dat[] = {0x20, 0x78, 0x07, 0xf0, 0x4e, 0xd0};
1898     if ((base = find_rom_data(0x78000, 0x8c000, check_load_dat, sizeof(check_load_dat))) == 0) return false;
1899     D(bug("check_load %08lx\n", base));
1900     wp = (uint16 *)(ROM_BASE + base);
1901     *wp++ = htons(M68K_JMP);
1902     *wp++ = htons((ROM_BASE + CHECK_LOAD_PATCH_SPACE) >> 16);
1903     *wp = htons((ROM_BASE + CHECK_LOAD_PATCH_SPACE) & 0xffff);
1904     wp = (uint16 *)(ROM_BASE + CHECK_LOAD_PATCH_SPACE);
1905     *wp++ = htons(0x2f03); // move.l d3,-(a7)
1906     *wp++ = htons(0x2078); // move.l $07f0,a0
1907     *wp++ = htons(0x07f0);
1908     *wp++ = htons(M68K_JSR_A0);
1909     *wp++ = htons(M68K_EMUL_OP_CHECKLOAD);
1910     *wp = htons(M68K_RTS);
1911    
1912     // Replace .Sony driver
1913     sony_offset = find_rom_resource(FOURCC('D','R','V','R'), 4);
1914     if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_NEWWORLD)
1915     sony_offset = find_rom_resource(FOURCC('D','R','V','R'), 4, true); // First DRVR 4 is .MFMFloppy
1916     if (sony_offset == 0) {
1917     sony_offset = find_rom_resource(FOURCC('n','d','r','v'), -20196); // NewWorld 1.6 has "PCFloppy" ndrv
1918     if (sony_offset == 0)
1919     return false;
1920     lp = (uint32 *)(ROM_BASE + rsrc_ptr + 8);
1921     *lp = htonl(FOURCC('D','R','V','R'));
1922     wp = (uint16 *)(ROM_BASE + rsrc_ptr + 12);
1923     *wp = htons(4);
1924     }
1925     D(bug("sony_offset %08lx\n", sony_offset));
1926     memcpy((void *)(ROM_BASE + sony_offset), sony_driver, sizeof(sony_driver));
1927    
1928     // Install .Disk and .AppleCD drivers
1929     memcpy((void *)(ROM_BASE + sony_offset + 0x100), disk_driver, sizeof(disk_driver));
1930     memcpy((void *)(ROM_BASE + sony_offset + 0x200), cdrom_driver, sizeof(cdrom_driver));
1931    
1932     // Install serial drivers
1933     memcpy((void *)(ROM_BASE + sony_offset + 0x300), ain_driver, sizeof(ain_driver));
1934     memcpy((void *)(ROM_BASE + sony_offset + 0x400), aout_driver, sizeof(aout_driver));
1935     memcpy((void *)(ROM_BASE + sony_offset + 0x500), bin_driver, sizeof(bin_driver));
1936     memcpy((void *)(ROM_BASE + sony_offset + 0x600), bout_driver, sizeof(bout_driver));
1937    
1938     // Copy icons to ROM
1939     SonyDiskIconAddr = ROM_BASE + sony_offset + 0x800;
1940     memcpy((void *)(ROM_BASE + sony_offset + 0x800), SonyDiskIcon, sizeof(SonyDiskIcon));
1941     SonyDriveIconAddr = ROM_BASE + sony_offset + 0xa00;
1942     memcpy((void *)(ROM_BASE + sony_offset + 0xa00), SonyDriveIcon, sizeof(SonyDriveIcon));
1943     DiskIconAddr = ROM_BASE + sony_offset + 0xc00;
1944     memcpy((void *)(ROM_BASE + sony_offset + 0xc00), DiskIcon, sizeof(DiskIcon));
1945     CDROMIconAddr = ROM_BASE + sony_offset + 0xe00;
1946     memcpy((void *)(ROM_BASE + sony_offset + 0xe00), CDROMIcon, sizeof(CDROMIcon));
1947    
1948     // Patch driver install routine
1949     static const uint8 drvr_install_dat[] = {0xa7, 0x1e, 0x21, 0xc8, 0x01, 0x1c, 0x4e, 0x75};
1950     if ((base = find_rom_data(0xb00, 0xd00, drvr_install_dat, sizeof(drvr_install_dat))) == 0) return false;
1951     D(bug("drvr_install %08lx\n", base));
1952     wp = (uint16 *)(ROM_BASE + base + 8);
1953     *wp++ = htons(M68K_EMUL_OP_INSTALL_DRIVERS);
1954     *wp = htons(M68K_RTS);
1955    
1956     // Don't install serial drivers from ROM
1957     if (ROMType == ROMTYPE_ZANZIBAR || ROMType == ROMTYPE_NEWWORLD) {
1958     wp = (uint16 *)(ROM_BASE + find_rom_resource(FOURCC('S','E','R','D'), 0));
1959     *wp = htons(M68K_RTS);
1960     } else {
1961     wp = (uint16 *)(ROM_BASE + find_rom_resource(FOURCC('s','l','0','5'), 2) + 0xc4);
1962     *wp++ = htons(M68K_NOP);
1963     *wp++ = htons(M68K_NOP);
1964     *wp++ = htons(M68K_NOP);
1965     *wp++ = htons(M68K_NOP);
1966     *wp = htons(0x7000); // moveq #0,d0
1967     wp = (uint16 *)(ROM_BASE + find_rom_resource(FOURCC('s','l','0','5'), 2) + 0x8ee);
1968     *wp = htons(M68K_NOP);
1969     }
1970     uint32 nsrd_offset = find_rom_resource(FOURCC('n','s','r','d'), 1);
1971     if (nsrd_offset) {
1972     lp = (uint32 *)(ROM_BASE + rsrc_ptr + 8);
1973     *lp = htonl(FOURCC('x','s','r','d'));
1974     }
1975    
1976     // Replace ADBOp()
1977     memcpy((void *)(ROM_BASE + find_rom_trap(0xa07c)), adbop_patch, sizeof(adbop_patch));
1978    
1979     // Replace Time Manager
1980     wp = (uint16 *)(ROM_BASE + find_rom_trap(0xa058));
1981     *wp++ = htons(M68K_EMUL_OP_INSTIME);
1982     *wp = htons(M68K_RTS);
1983     wp = (uint16 *)(ROM_BASE + find_rom_trap(0xa059));
1984     *wp++ = htons(0x40e7); // move sr,-(sp)
1985     *wp++ = htons(0x007c); // ori #$0700,sr
1986     *wp++ = htons(0x0700);
1987     *wp++ = htons(M68K_EMUL_OP_RMVTIME);
1988     *wp++ = htons(0x46df); // move (sp)+,sr
1989     *wp = htons(M68K_RTS);
1990     wp = (uint16 *)(ROM_BASE + find_rom_trap(0xa05a));
1991     *wp++ = htons(0x40e7); // move sr,-(sp)
1992     *wp++ = htons(0x007c); // ori #$0700,sr
1993     *wp++ = htons(0x0700);
1994     *wp++ = htons(M68K_EMUL_OP_PRIMETIME);
1995     *wp++ = htons(0x46df); // move (sp)+,sr
1996     *wp = htons(M68K_RTS);
1997     wp = (uint16 *)(ROM_BASE + find_rom_trap(0xa093));
1998     *wp++ = htons(M68K_EMUL_OP_MICROSECONDS);
1999     *wp = htons(M68K_RTS);
2000    
2001     // Disable Egret Manager
2002     static const uint8 egret_dat[] = {0x2f, 0x30, 0x81, 0xe2, 0x20, 0x10, 0x00, 0x18};
2003     if ((base = find_rom_data(0xa000, 0x10000, egret_dat, sizeof(egret_dat))) == 0) return false;
2004     D(bug("egret %08lx\n", base));
2005     wp = (uint16 *)(ROM_BASE + base);
2006     *wp++ = htons(0x7000);
2007     *wp = htons(M68K_RTS);
2008    
2009     // Don't call FE0A opcode in Shutdown Manager
2010     static const uint8 shutdown_dat[] = {0x40, 0xe7, 0x00, 0x7c, 0x07, 0x00, 0x48, 0xe7, 0x3f, 0x00, 0x2c, 0x00, 0x2e, 0x01};
2011     if ((base = find_rom_data(0x30000, 0x40000, shutdown_dat, sizeof(shutdown_dat))) == 0) return false;
2012     D(bug("shutdown %08lx\n", base));
2013     wp = (uint16 *)(ROM_BASE + base);
2014     if (ROMType == ROMTYPE_ZANZIBAR)
2015     *wp = htons(M68K_RTS);
2016     else
2017     wp[-2] = htons(0x6000); // bra
2018    
2019     // Patch PowerOff()
2020     wp = (uint16 *)(ROM_BASE + find_rom_trap(0xa05b)); // PowerOff()
2021     *wp = htons(M68K_EMUL_RETURN);
2022    
2023     // Patch VIA interrupt handler
2024     static const uint8 via_int_dat[] = {0x70, 0x7f, 0xc0, 0x29, 0x1a, 0x00, 0xc0, 0x29, 0x1c, 0x00};
2025     if ((base = find_rom_data(0x13000, 0x1c000, via_int_dat, sizeof(via_int_dat))) == 0) return false;
2026     D(bug("via_int %08lx\n", base));
2027     uint32 level1_int = ROM_BASE + base;
2028     wp = (uint16 *)level1_int; // Level 1 handler
2029     *wp++ = htons(0x7002); // moveq #2,d0 (60Hz interrupt)
2030     *wp++ = htons(M68K_NOP);
2031     *wp++ = htons(M68K_NOP);
2032     *wp++ = htons(M68K_NOP);
2033     *wp = htons(M68K_NOP);
2034    
2035     static const uint8 via_int2_dat[] = {0x13, 0x7c, 0x00, 0x02, 0x1a, 0x00, 0x4e, 0x71, 0x52, 0xb8, 0x01, 0x6a};
2036     if ((base = find_rom_data(0x10000, 0x18000, via_int2_dat, sizeof(via_int2_dat))) == 0) return false;
2037     D(bug("via_int2 %08lx\n", base));
2038     wp = (uint16 *)(ROM_BASE + base); // 60Hz handler
2039     *wp++ = htons(M68K_EMUL_OP_IRQ);
2040     *wp++ = htons(0x4a80); // tst.l d0
2041     *wp++ = htons(0x6700); // beq xxx
2042     *wp = htons(0xffe8);
2043    
2044     if (ROMType == ROMTYPE_NEWWORLD) {
2045     static const uint8 via_int3_dat[] = {0x48, 0xe7, 0xf0, 0xf0, 0x76, 0x01, 0x60, 0x26};
2046 gbeauche 1.4 if ((base = find_rom_data(0x15000, 0x19000, via_int3_dat, sizeof(via_int3_dat))) == 0) return false;
2047 cebix 1.1 D(bug("via_int3 %08lx\n", base));
2048     wp = (uint16 *)(ROM_BASE + base); // CHRP level 1 handler
2049     *wp++ = htons(M68K_JMP);
2050     *wp++ = htons((level1_int - 12) >> 16);
2051     *wp = htons((level1_int - 12) & 0xffff);
2052     }
2053    
2054     // Patch PutScrap() for clipboard exchange with host OS
2055     uint32 put_scrap = find_rom_trap(0xa9fe); // PutScrap()
2056     wp = (uint16 *)(ROM_BASE + PUT_SCRAP_PATCH_SPACE);
2057     *wp++ = htons(M68K_EMUL_OP_PUT_SCRAP);
2058     *wp++ = htons(M68K_JMP);
2059     *wp++ = htons((ROM_BASE + put_scrap) >> 16);
2060     *wp++ = htons((ROM_BASE + put_scrap) & 0xffff);
2061     lp = (uint32 *)(ROM_BASE + 0x22);
2062     lp = (uint32 *)(ROM_BASE + ntohl(*lp));
2063     lp[0xa9fe & 0x3ff] = htonl(PUT_SCRAP_PATCH_SPACE);
2064    
2065     // Patch GetScrap() for clipboard exchange with host OS
2066     uint32 get_scrap = find_rom_trap(0xa9fd); // GetScrap()
2067     wp = (uint16 *)(ROM_BASE + GET_SCRAP_PATCH_SPACE);
2068     *wp++ = htons(M68K_EMUL_OP_GET_SCRAP);
2069     *wp++ = htons(M68K_JMP);
2070     *wp++ = htons((ROM_BASE + get_scrap) >> 16);
2071     *wp++ = htons((ROM_BASE + get_scrap) & 0xffff);
2072     lp = (uint32 *)(ROM_BASE + 0x22);
2073     lp = (uint32 *)(ROM_BASE + ntohl(*lp));
2074     lp[0xa9fd & 0x3ff] = htonl(GET_SCRAP_PATCH_SPACE);
2075    
2076     #if __BEOS__
2077     // Patch SynchIdleTime()
2078     if (PrefsFindBool("idlewait")) {
2079     wp = (uint16 *)(ROM_BASE + find_rom_trap(0xabf7) + 4); // SynchIdleTime()
2080     D(bug("SynchIdleTime at %08lx\n", wp));
2081     if (ntohs(*wp) == 0x2078) {
2082     *wp++ = htons(M68K_EMUL_OP_IDLE_TIME);
2083     *wp = htons(M68K_NOP);
2084     } else {
2085     D(bug("SynchIdleTime patch not installed\n"));
2086     }
2087     }
2088     #endif
2089    
2090     // Construct list of all sifters used by sound components in ROM
2091     D(bug("Searching for sound components with type sdev in ROM\n"));
2092     uint32 thing = find_rom_resource(FOURCC('t','h','n','g'));
2093     while (thing) {
2094     thing += ROM_BASE;
2095     D(bug(" found %c%c%c%c %c%c%c%c\n", ReadMacInt8(thing), ReadMacInt8(thing + 1), ReadMacInt8(thing + 2), ReadMacInt8(thing + 3), ReadMacInt8(thing + 4), ReadMacInt8(thing + 5), ReadMacInt8(thing + 6), ReadMacInt8(thing + 7)));
2096     if (ReadMacInt32(thing) == FOURCC('s','d','e','v') && ReadMacInt32(thing + 4) == FOURCC('s','i','n','g')) {
2097     WriteMacInt32(thing + 4, FOURCC('a','w','g','c'));
2098     D(bug(" found sdev component at offset %08x in ROM\n", thing));
2099     AddSifter(ReadMacInt32(thing + componentResType), ReadMacInt16(thing + componentResID));
2100     if (ReadMacInt32(thing + componentPFCount))
2101     AddSifter(ReadMacInt32(thing + componentPFResType), ReadMacInt16(thing + componentPFResID));
2102     }
2103     thing = find_rom_resource(FOURCC('t','h','n','g'), 4711, true);
2104     }
2105    
2106     // Patch component code
2107     D(bug("Patching sifters in ROM\n"));
2108     for (int i=0; i<num_sifters; i++) {
2109     if ((thing = find_rom_resource(sifter_list[i].type, sifter_list[i].id)) != 0) {
2110     D(bug(" patching type %08x, id %d\n", sifter_list[i].type, sifter_list[i].id));
2111     // Install 68k glue code
2112     uint16 *wp = (uint16 *)(ROM_BASE + thing);
2113     *wp++ = htons(0x4e56); *wp++ = htons(0x0000); // link a6,#0
2114     *wp++ = htons(0x48e7); *wp++ = htons(0x8018); // movem.l d0/a3-a4,-(a7)
2115     *wp++ = htons(0x266e); *wp++ = htons(0x000c); // movea.l $c(a6),a3
2116     *wp++ = htons(0x286e); *wp++ = htons(0x0008); // movea.l $8(a6),a4
2117     *wp++ = htons(M68K_EMUL_OP_AUDIO_DISPATCH);
2118     *wp++ = htons(0x2d40); *wp++ = htons(0x0010); // move.l d0,$10(a6)
2119     *wp++ = htons(0x4cdf); *wp++ = htons(0x1801); // movem.l (a7)+,d0/a3-a4
2120     *wp++ = htons(0x4e5e); // unlk a6
2121     *wp++ = htons(0x4e74); *wp++ = htons(0x0008); // rtd #8
2122     }
2123     }
2124     return true;
2125     }
2126    
2127    
2128     /*
2129     * Install .Sony, disk and CD-ROM drivers
2130     */
2131    
2132     void InstallDrivers(void)
2133     {
2134     D(bug("Installing drivers...\n"));
2135     M68kRegisters r;
2136     uint8 pb[SIZEOF_IOParam];
2137    
2138     // Open .Sony driver
2139     WriteMacInt8((uint32)pb + ioPermssn, 0);
2140     WriteMacInt32((uint32)pb + ioNamePtr, (uint32)"\005.Sony");
2141     r.a[0] = (uint32)pb;
2142     Execute68kTrap(0xa000, &r); // Open()
2143    
2144     // Install disk driver
2145     r.a[0] = ROM_BASE + sony_offset + 0x100;
2146     r.d[0] = (uint32)DiskRefNum;
2147     Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem()
2148     r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~DiskRefNum * 4); // Get driver handle from Unit Table
2149     Execute68kTrap(0xa029, &r); // HLock()
2150     uint32 dce = ReadMacInt32(r.a[0]);
2151     WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x100);
2152     WriteMacInt16(dce + dCtlFlags, DiskDriverFlags);
2153    
2154     // Open disk driver
2155     WriteMacInt32((uint32)pb + ioNamePtr, (uint32)"\005.Disk");
2156     r.a[0] = (uint32)pb;
2157     Execute68kTrap(0xa000, &r); // Open()
2158    
2159     // Install CD-ROM driver unless nocdrom option given
2160     if (!PrefsFindBool("nocdrom")) {
2161    
2162     // Install CD-ROM driver
2163     r.a[0] = ROM_BASE + sony_offset + 0x200;
2164     r.d[0] = (uint32)CDROMRefNum;
2165     Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem()
2166     r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~CDROMRefNum * 4); // Get driver handle from Unit Table
2167     Execute68kTrap(0xa029, &r); // HLock()
2168     dce = ReadMacInt32(r.a[0]);
2169     WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x200);
2170     WriteMacInt16(dce + dCtlFlags, CDROMDriverFlags);
2171    
2172     // Open CD-ROM driver
2173     WriteMacInt32((uint32)pb + ioNamePtr, (uint32)"\010.AppleCD");
2174     r.a[0] = (uint32)pb;
2175     Execute68kTrap(0xa000, &r); // Open()
2176     }
2177    
2178     // Install serial drivers
2179     r.a[0] = ROM_BASE + sony_offset + 0x300;
2180     r.d[0] = (uint32)-6;
2181     Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem()
2182     r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~(-6) * 4); // Get driver handle from Unit Table
2183     Execute68kTrap(0xa029, &r); // HLock()
2184     dce = ReadMacInt32(r.a[0]);
2185     WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x300);
2186     WriteMacInt16(dce + dCtlFlags, 0x4d00);
2187    
2188     r.a[0] = ROM_BASE + sony_offset + 0x400;
2189     r.d[0] = (uint32)-7;
2190     Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem()
2191     r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~(-7) * 4); // Get driver handle from Unit Table
2192     Execute68kTrap(0xa029, &r); // HLock()
2193     dce = ReadMacInt32(r.a[0]);
2194     WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x400);
2195     WriteMacInt16(dce + dCtlFlags, 0x4e00);
2196    
2197     r.a[0] = ROM_BASE + sony_offset + 0x500;
2198     r.d[0] = (uint32)-8;
2199     Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem()
2200     r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~(-8) * 4); // Get driver handle from Unit Table
2201     Execute68kTrap(0xa029, &r); // HLock()
2202     dce = ReadMacInt32(r.a[0]);
2203     WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x500);
2204     WriteMacInt16(dce + dCtlFlags, 0x4d00);
2205    
2206     r.a[0] = ROM_BASE + sony_offset + 0x600;
2207     r.d[0] = (uint32)-9;
2208     Execute68kTrap(0xa43d, &r); // DrvrInstallRsrvMem()
2209     r.a[0] = ReadMacInt32(ReadMacInt32(0x11c) + ~(-9) * 4); // Get driver handle from Unit Table
2210     Execute68kTrap(0xa029, &r); // HLock()
2211     dce = ReadMacInt32(r.a[0]);
2212     WriteMacInt32(dce + dCtlDriver, ROM_BASE + sony_offset + 0x600);
2213     WriteMacInt16(dce + dCtlFlags, 0x4e00);
2214     }