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root/cebix/SheepShaver/src/rom_patches.cpp

Comparing SheepShaver/src/rom_patches.cpp (file contents):
Revision 1.25 by gbeauche, 2004-01-31T11:10:48Z vs.
Revision 1.26 by gbeauche, 2004-02-15T17:20:36Z

#	Line 871 | Line 871 | static bool patch_nanokernel_boot(void)
871		lp[8] = htonl(0x00800002);      // TLB total size/TLB assoc
872		break;
873		//              case 11:        // X704?
874	<	case 12:        // ???
874	>	case 12:        // 7400, 7410
875	>	case 0x800c:
876		lp[0] = htonl(0x1000);          // Page size
877		lp[1] = htonl(0x8000);          // Data cache size
878		lp[2] = htonl(0x8000);          // Inst cache size
#	Line 906 | Line 907 | static bool patch_nanokernel_boot(void)
907		lp[7] = htonl(0x00080008);      // Inst cache assoc/Data cache assoc
908		lp[8] = htonl(0x00800004);      // TLB total size/TLB assoc
909		break;
909	–	case 0x8000:    // 7400
910	–	case 0x800c:    // 7410
911	–	lp[0] = htonl(0x1000);          // Page size
912	–	lp[1] = htonl(0x8000);          // Data cache size
913	–	lp[2] = htonl(0x8000);          // Inst cache size
914	–	lp[3] = htonl(0x00200020);      // Coherency block size/Reservation granule size
915	–	lp[4] = htonl(0x00000020);      // Unified caches/Inst cache line size
916	–	lp[5] = htonl(0x00200020);      // Data cache line size/Data cache block size touch
917	–	lp[6] = htonl(0x00200020);      // Inst cache block size/Data cache block size
918	–	lp[7] = htonl(0x00080008);      // Inst cache assoc/Data cache assoc
919	–	lp[8] = htonl(0x00800002);      // TLB total size/TLB assoc
920	–	break;
910		default:
911		printf("WARNING: Unknown CPU type\n");
912		break;

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