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root/cebix/SheepShaver/src/rom_patches.cpp
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Comparing SheepShaver/src/rom_patches.cpp (file contents):
Revision 1.18 by gbeauche, 2003-12-04T17:26:35Z vs.
Revision 1.21 by gbeauche, 2003-12-15T15:23:59Z

# Line 62 | Line 62
62   const uint32 CHECK_LOAD_PATCH_SPACE = 0x2fcf00;
63   const uint32 PUT_SCRAP_PATCH_SPACE = 0x2fcf80;
64   const uint32 GET_SCRAP_PATCH_SPACE = 0x2fcfc0;
65 < const uint32 ADDR_MAP_PATCH_SPACE = 0x2fd000;
65 > const uint32 ADDR_MAP_PATCH_SPACE = 0x2fd100;
66  
67   // Global variables
68   int ROMType;                            // ROM type
# Line 270 | Line 270 | static uint32 find_rom_trap(uint16 trap)
270  
271  
272   /*
273 + *  Return target of branch instruction specified at ADDR, or 0 if
274 + *  there is no such instruction
275 + */
276 +
277 + static uint32 powerpc_branch_target(uintptr addr)
278 + {
279 +        uint32 opcode = ntohl(*(uint32 *)addr);
280 +        uint32 primop = opcode >> 26;
281 +        uint32 target = 0;
282 +
283 +        if (primop == 18) {                     // Branch
284 +                target = opcode & 0x3fffffc;
285 +                if (target & 0x2000000)
286 +                        target |= 0xfc000000;
287 +                if ((opcode & 2) == 0)
288 +                        target += addr;
289 +        }
290 +        else if (primop == 16) {        // Branch Conditional
291 +                target = (int32)(int16)(opcode & 0xfffc);
292 +                if ((opcode & 2) == 0)
293 +                        target += addr;
294 +        }
295 +        return target;
296 + }
297 +
298 +
299 + /*
300 + *  Search ROM for instruction branching to target address, return 0 if none found
301 + */
302 +
303 + static uint32 find_rom_powerpc_branch(uint32 start, uint32 end, uint32 target)
304 + {
305 +        for (uint32 addr = start; addr < end; addr += 4) {
306 +                if (powerpc_branch_target(ROM_BASE + addr) == ROM_BASE + target)
307 +                        return addr;
308 +        }
309 +        return 0;
310 + }
311 +
312 +
313 + /*
314 + *  Check that requested ROM patch space is really available
315 + */
316 +
317 + static bool check_rom_patch_space(uint32 base, uint32 size)
318 + {
319 +        size = (size + 3) & -4;
320 +        for (int i = 0; i < size; i += 4) {
321 +                uint32 x = ntohl(*(uint32 *)(ROM_BASE + base + i));
322 +                printf("%08x\n", x);
323 +                if (x != 0x6b636b63 && x != 0)
324 +                        return false;
325 +        }
326 +        return true;
327 + }
328 +
329 +
330 + /*
331   *  List of audio sifters installed in ROM and System file
332   */
333  
# Line 656 | Line 714 | bool PatchROM(void)
714                  return false;
715  
716          // Check that other ROM addresses point to really free regions
717 <        if (ntohl(*(uint32 *)(ROM_BASE + CHECK_LOAD_PATCH_SPACE)) != 0x6b636b63)
717 >        if (!check_rom_patch_space(CHECK_LOAD_PATCH_SPACE, 0x40))
718                  return false;
719 <        if (ntohl(*(uint32 *)(ROM_BASE + PUT_SCRAP_PATCH_SPACE)) != 0x6b636b63)
719 >        if (!check_rom_patch_space(PUT_SCRAP_PATCH_SPACE, 0x40))
720                  return false;
721 <        if (ntohl(*(uint32 *)(ROM_BASE + GET_SCRAP_PATCH_SPACE)) != 0x6b636b63)
721 >        if (!check_rom_patch_space(GET_SCRAP_PATCH_SPACE, 0x40))
722                  return false;
723 <        if (ntohl(*(uint32 *)(ROM_BASE + ADDR_MAP_PATCH_SPACE)) != 0x6b636b63)
723 >        if (!check_rom_patch_space(ADDR_MAP_PATCH_SPACE - 10 * 4, 0x100))
724                  return false;
725  
726          // Apply patches
# Line 697 | Line 755 | bool PatchROM(void)
755   static bool patch_nanokernel_boot(void)
756   {
757          uint32 *lp;
758 +        uint32 base, loc;
759  
760          // ROM boot structure patches
761          lp = (uint32 *)(ROM_BASE + 0x30d000);
# Line 709 | Line 768 | static bool patch_nanokernel_boot(void)
768          lp[0xfd8 >> 2] = htonl(ROM_BASE + 0x2a);                // 68k reset vector
769  
770          // Skip SR/BAT/SDR init
771 +        loc = 0x310000;
772          if (ROMType == ROMTYPE_GAZELLE || ROMType == ROMTYPE_GOSSAMER || ROMType == ROMTYPE_NEWWORLD) {
773 <                lp = (uint32 *)(ROM_BASE + 0x310000);
773 >                lp = (uint32 *)(ROM_BASE + loc);
774                  *lp++ = htonl(POWERPC_NOP);
775                  *lp = htonl(0x38000000);
776          }
777 <        static const uint32 sr_init_loc[] = {0x3101b0, 0x3101b0, 0x3101b0, 0x3101ec, 0x3101fc, 0x310200};
778 <        lp = (uint32 *)(ROM_BASE + 0x310008);
779 <        *lp = htonl(0x48000000 | (sr_init_loc[ROMType] - 8) & 0xffff);  // b            ROM_BASE+0x3101b0
780 <        lp = (uint32 *)(ROM_BASE + sr_init_loc[ROMType]);
777 >        static const uint8 sr_init_dat[] = {0x35, 0x4a, 0xff, 0xfc, 0x7d, 0x86, 0x50, 0x2e};
778 >        if ((base = find_rom_data(0x3101b0, 0x3105b0, sr_init_dat, sizeof(sr_init_dat))) == 0) return false;
779 >        D(bug("sr_init %08lx\n", base));
780 >        lp = (uint32 *)(ROM_BASE + loc + 8);
781 >        *lp = htonl(0x48000000 | ((base - loc - 8) & 0x3fffffc));       // b            ROM_BASE+0x3101b0
782 >        lp = (uint32 *)(ROM_BASE + base);
783          *lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);            // lwz  r1,(pointer to Kernel Data)
784          *lp++ = htonl(0x3da0dead);              // lis  r13,0xdead      (start of kernel memory)
785          *lp++ = htonl(0x3dc00010);              // lis  r14,0x0010      (size of page table)
786          *lp = htonl(0x3de00010);                // lis  r15,0x0010      (size of kernel memory)
787  
788          // Don't read PVR
789 <        static const uint32 pvr_loc[] = {0x3103b0, 0x3103b4, 0x3103b4, 0x310400, 0x310430, 0x310438};
790 <        lp = (uint32 *)(ROM_BASE + pvr_loc[ROMType]);
789 >        static const uint8 pvr_read_dat[] = {0x7d, 0x9f, 0x42, 0xa6};
790 >        if ((base = find_rom_data(0x3103b0, 0x3108b0, pvr_read_dat, sizeof(pvr_read_dat))) == 0) return false;
791 >        D(bug("pvr_read %08lx\n", base));
792 >        lp = (uint32 *)(ROM_BASE + base);
793          *lp = htonl(0x81800000 + XLM_PVR);      // lwz  r12,(theoretical PVR)
794  
795          // Set CPU specific data (even if ROM doesn't have support for that CPU)
732        lp = (uint32 *)(ROM_BASE + pvr_loc[ROMType]);
796          if (ntohl(lp[6]) != 0x2c0c0001)
797                  return false;
798          uint32 ofs = ntohl(lp[7]) & 0xffff;
799          D(bug("ofs %08lx\n", ofs));
800          lp[8] = htonl((ntohl(lp[8]) & 0xffff) | 0x48000000);    // beq -> b
801 <        uint32 loc = (ntohl(lp[8]) & 0xffff) + (uint32)(lp+8) - ROM_BASE;
801 >        loc = (ntohl(lp[8]) & 0xffff) + (uint32)(lp+8) - ROM_BASE;
802          D(bug("loc %08lx\n", loc));
803          lp = (uint32 *)(ROM_BASE + ofs + 0x310000);
804          switch (PVR >> 16) {
# Line 850 | Line 913 | static bool patch_nanokernel_boot(void)
913          }
914  
915          // Don't set SPRG3, don't test MQ
916 <        lp = (uint32 *)(ROM_BASE + loc + 0x20);
917 <        *lp++ = htonl(POWERPC_NOP);
918 <        lp++;
919 <        *lp++ = htonl(POWERPC_NOP);
920 <        lp++;
921 <        *lp = htonl(POWERPC_NOP);
916 >        static const uint8 sprg3_mq_dat[] = {0x7d, 0x13, 0x43, 0xa6, 0x3d, 0x00, 0x00, 0x04, 0x7d, 0x00, 0x03, 0xa6, 0x39, 0x00, 0x00, 0x00, 0x7d, 0x00, 0x02, 0xa6};
917 >        if ((base = find_rom_data(loc + 0x20, loc + 0x60, sprg3_mq_dat, sizeof(sprg3_mq_dat))) == 0) return false;
918 >        D(bug("sprg3/mq %08lx\n", base));
919 >        lp = (uint32 *)(ROM_BASE + base);
920 >        lp[0] = htonl(POWERPC_NOP);
921 >        lp[2] = htonl(POWERPC_NOP);
922 >        lp[4] = htonl(POWERPC_NOP);
923  
924          // Don't read MSR
925 <        lp = (uint32 *)(ROM_BASE + loc + 0x40);
925 >        static const uint8 msr_dat[] = {0x7d, 0xc0, 0x00, 0xa6};
926 >        if ((base = find_rom_data(loc + 0x40, loc + 0x80, msr_dat, sizeof(msr_dat))) == 0) return false;
927 >        D(bug("msr %08lx\n", base));
928 >        lp = (uint32 *)(ROM_BASE + base);
929          *lp = htonl(0x39c00000);                // li   r14,0
930  
931          // Don't write to DEC
# Line 868 | Line 935 | static bool patch_nanokernel_boot(void)
935          D(bug("loc %08lx\n", loc));
936  
937          // Don't set SPRG3
938 <        lp = (uint32 *)(ROM_BASE + loc + 0x2c);
938 >        static const uint8 sprg3_dat[] = {0x39, 0x21, 0x03, 0x60, 0x7d, 0x33, 0x43, 0xa6, 0x39, 0x01, 0x04, 0x20};
939 >        if ((base = find_rom_data(0x310000, 0x314000, sprg3_dat, sizeof(sprg3_dat))) == 0) return false;
940 >        D(bug("sprg3 %08lx\n", base + 4));
941 >        lp = (uint32 *)(ROM_BASE + base + 4);
942          *lp = htonl(POWERPC_NOP);
943  
944          // Don't read PVR
945 <        static const uint32 pvr_ofs[] = {0x138, 0x138, 0x138, 0x140, 0x148, 0x148};
946 <        lp = (uint32 *)(ROM_BASE + loc + pvr_ofs[ROMType]);
945 >        static const uint8 pvr_read2_dat[] = {0x7e, 0xff, 0x42, 0xa6, 0x56, 0xf7, 0x84, 0x3e};
946 >        if ((base = find_rom_data(0x310000, 0x320000, pvr_read2_dat, sizeof(pvr_read2_dat))) == 0) return false;
947 >        D(bug("pvr_read2 %08lx\n", base));
948 >        lp = (uint32 *)(ROM_BASE + base);
949          *lp = htonl(0x82e00000 + XLM_PVR);              // lwz  r23,(theoretical PVR)
950 <        lp = (uint32 *)(ROM_BASE + loc + 0x170);
951 <        if (ntohl(*lp) == 0x7eff42a6)   // NewWorld or Gossamer ROM
950 >        if ((base = find_rom_data(base + 4, 0x320000, pvr_read2_dat, sizeof(pvr_read2_dat))) != 0) {
951 >                D(bug("pvr_read2 %08lx\n", base));
952 >                lp = (uint32 *)(ROM_BASE + base);
953                  *lp = htonl(0x82e00000 + XLM_PVR);      // lwz  r23,(theoretical PVR)
954 <        lp = (uint32 *)(ROM_BASE + 0x313134);
955 <        if (ntohl(*lp) == 0x7e5f42a6)
956 <                *lp = htonl(0x82400000 + XLM_PVR);      // lwz  r18,(theoretical PVR)
957 <        lp = (uint32 *)(ROM_BASE + 0x3131f4);
958 <        if (ntohl(*lp) == 0x7e5f42a6)   // NewWorld ROM
954 >        }
955 >        static const uint8 pvr_read3_dat[] = {0x7e, 0x5f, 0x42, 0xa6, 0x56, 0x52, 0x84, 0x3e};
956 >        if ((base = find_rom_data(0x310000, 0x320000, pvr_read3_dat, sizeof(pvr_read3_dat))) != 0) {
957 >                D(bug("pvr_read3 %08lx\n", base));
958 >                lp = (uint32 *)(ROM_BASE + base);
959                  *lp = htonl(0x82400000 + XLM_PVR);      // lwz  r18,(theoretical PVR)
960 <        lp = (uint32 *)(ROM_BASE + 0x314600);
961 <        if (ntohl(*lp) == 0x7d3f42a6)
960 >        }
961 >        static const uint8 pvr_read4_dat[] = {0x7d, 0x3f, 0x42, 0xa6, 0x55, 0x29, 0x84, 0x3e};
962 >        if ((base = find_rom_data(0x310000, 0x320000, pvr_read4_dat, sizeof(pvr_read4_dat))) != 0) {
963 >                D(bug("pvr_read4 %08lx\n", base));
964 >                lp = (uint32 *)(ROM_BASE + base);
965                  *lp = htonl(0x81200000 + XLM_PVR);      // lzw  r9,(theoritical PVR)
966 +        }
967  
968          // Don't read SDR1
969 <        static const uint32 sdr1_ofs[] = {0x174, 0x174, 0x174, 0x17c, 0x19c, 0x19c};
970 <        lp = (uint32 *)(ROM_BASE + loc + sdr1_ofs[ROMType]);
969 >        static const uint8 sdr1_read_dat[] = {0x7d, 0x19, 0x02, 0xa6, 0x55, 0x16, 0x81, 0xde};
970 >        if ((base = find_rom_data(0x310000, 0x320000, sdr1_read_dat, sizeof(sdr1_read_dat))) == 0) return false;
971 >        D(bug("sdr1_read %08lx\n", base));
972 >        lp = (uint32 *)(ROM_BASE + base);
973          *lp++ = htonl(0x3d00dead);              // lis  r8,0xdead               (pointer to page table)
974          *lp++ = htonl(0x3ec0001f);              // lis  r22,0x001f      (size of page table)
975          *lp = htonl(POWERPC_NOP);
976  
977 <        // Don't clear page table
978 <        static const uint32 pgtb_ofs[] = {0x198, 0x198, 0x198, 0x1a0, 0x1c0, 0x1c4};
979 <        lp = (uint32 *)(ROM_BASE + loc + pgtb_ofs[ROMType]);
977 >        // Don't clear page table, don't invalidate TLB
978 >        static const uint8 pgtb_clear_dat[] = {0x36, 0xd6, 0xff, 0xfc, 0x7e, 0xe8, 0xb1, 0x2e, 0x41, 0x81, 0xff, 0xf8};
979 >        if ((base = find_rom_data(0x310000, 0x320000, pgtb_clear_dat, sizeof(pgtb_clear_dat))) == 0) return false;
980 >        D(bug("pgtb_clear %08lx\n", base + 4));
981 >        lp = (uint32 *)(ROM_BASE + base + 4);
982          *lp = htonl(POWERPC_NOP);
983 <
984 <        // Don't invalidate TLB
904 <        static const uint32 tlb_ofs[] = {0x1a0, 0x1a0, 0x1a0, 0x1a8, 0x1c8, 0x1cc};
905 <        lp = (uint32 *)(ROM_BASE + loc + tlb_ofs[ROMType]);
983 >        D(bug("tblie %08lx\n", base + 12));
984 >        lp = (uint32 *)(ROM_BASE + base + 12);
985          *lp = htonl(POWERPC_NOP);
986  
987          // Don't create RAM descriptor table
988 <        static const uint32 desc_ofs[] = {0x350, 0x350, 0x350, 0x358, 0x378, 0x37c};
989 <        lp = (uint32 *)(ROM_BASE + loc + desc_ofs[ROMType]);
988 >        static const uint8 desc_create_dat[] = {0x97, 0xfd, 0x00, 0x04, 0x3b, 0xff, 0x10, 0x00, 0x4b, 0xff, 0xff, 0xdc};
989 >        if ((base = find_rom_data(0x310000, 0x320000, desc_create_dat, sizeof(desc_create_dat))) == 0) return false;
990 >        D(bug("desc_create %08lx\n", base))
991 >        lp = (uint32 *)(ROM_BASE + base);
992          *lp = htonl(POWERPC_NOP);
993  
994          // Don't load SRs and BATs
995 <        static const uint32 sr_ofs[] = {0x3d8, 0x3d8, 0x3d8, 0x3e0, 0x400, 0x404};
996 <        lp = (uint32 *)(ROM_BASE + loc + sr_ofs[ROMType]);
995 >        static const uint8 sr_load[] = {0x7c, 0x00, 0x04, 0xac, 0x83, 0x9d, 0x00, 0x00, 0x93, 0x81, 0x05, 0xe8};
996 >        if ((loc = find_rom_data(0x310000, 0x320000, sr_load, sizeof(sr_load))) == 0) return false;
997 >        static const uint8 sr_load_caller[] = {0x3e, 0xd6, 0xff, 0xff, 0x41, 0x81, 0xff, 0xdc, 0xb2, 0xc8, 0x00, 0x02};
998 >        if ((base = find_rom_data(0x310000, 0x320000, sr_load_caller, sizeof(sr_load_caller))) == 0) return false;
999 >        if ((base = find_rom_powerpc_branch(base + 12, 0x320000, loc)) == 0) return false;
1000 >        D(bug("sr_load %08lx, called from %08lx\n", loc, base));
1001 >        lp = (uint32 *)(ROM_BASE + base);
1002          *lp = htonl(POWERPC_NOP);
1003  
1004          // Don't mess with SRs
1005 <        static const uint32 sr2_ofs[] = {0x312118, 0x312118, 0x312118, 0x312118, 0x312118, 0x3121b4};
1006 <        lp = (uint32 *)(ROM_BASE + sr2_ofs[ROMType]);
1005 >        static const uint8 sr_load2_dat[] = {0x83, 0xa1, 0x05, 0xe8, 0x57, 0x7c, 0x3e, 0x78, 0x7f, 0xbd, 0xe0, 0x2e};
1006 >        if ((base = find_rom_data(0x310000, 0x320000, sr_load2_dat, sizeof(sr_load2_dat))) == 0) return false;
1007 >        D(bug("sr_load2 %08lx\n", base));
1008 >        lp = (uint32 *)(ROM_BASE + base);
1009          *lp = htonl(POWERPC_BLR);
1010  
1011          // Don't check performance monitor
1012 <        static const uint32 pm_ofs[] = {0x313148, 0x313148, 0x313148, 0x313148, 0x313158, 0x313218};
1013 <        lp = (uint32 *)(ROM_BASE + pm_ofs[ROMType]);
1014 <        while (ntohl(*lp) != 0x7e58eba6) lp++;
1015 <        *lp++ = htonl(POWERPC_NOP);
1016 <        while (ntohl(*lp) != 0x7e78eaa6) lp++;
1017 <        *lp++ = htonl(POWERPC_NOP);
1018 <        while (ntohl(*lp) != 0x7e59eba6) lp++;
1019 <        *lp++ = htonl(POWERPC_NOP);
1020 <        while (ntohl(*lp) != 0x7e79eaa6) lp++;
1021 <        *lp++ = htonl(POWERPC_NOP);
1022 <        while (ntohl(*lp) != 0x7e5aeba6) lp++;
1023 <        *lp++ = htonl(POWERPC_NOP);
1024 <        while (ntohl(*lp) != 0x7e7aeaa6) lp++;
1025 <        *lp++ = htonl(POWERPC_NOP);
1026 <        while (ntohl(*lp) != 0x7e5beba6) lp++;
1027 <        *lp++ = htonl(POWERPC_NOP);
1028 <        while (ntohl(*lp) != 0x7e7beaa6) lp++;
1029 <        *lp++ = htonl(POWERPC_NOP);
1030 <        while (ntohl(*lp) != 0x7e5feba6) lp++;
1031 <        *lp++ = htonl(POWERPC_NOP);
1032 <        while (ntohl(*lp) != 0x7e7feaa6) lp++;
1033 <        *lp++ = htonl(POWERPC_NOP);
1034 <        while (ntohl(*lp) != 0x7e5ceba6) lp++;
1035 <        *lp++ = htonl(POWERPC_NOP);
948 <        while (ntohl(*lp) != 0x7e7ceaa6) lp++;
949 <        *lp++ = htonl(POWERPC_NOP);
950 <        while (ntohl(*lp) != 0x7e5deba6) lp++;
951 <        *lp++ = htonl(POWERPC_NOP);
952 <        while (ntohl(*lp) != 0x7e7deaa6) lp++;
953 <        *lp++ = htonl(POWERPC_NOP);
954 <        while (ntohl(*lp) != 0x7e5eeba6) lp++;
955 <        *lp++ = htonl(POWERPC_NOP);
956 <        while (ntohl(*lp) != 0x7e7eeaa6) lp++;
957 <        *lp++ = htonl(POWERPC_NOP);
1012 >        static const uint8 pm_check_dat[] = {0x7e, 0x58, 0xeb, 0xa6, 0x7e, 0x53, 0x90, 0xf8, 0x7e, 0x78, 0xea, 0xa6};
1013 >        if ((base = find_rom_data(0x310000, 0x320000, pm_check_dat, sizeof(pm_check_dat))) == 0) return false;
1014 >        D(bug("pm_check %08lx\n", base));
1015 >        lp = (uint32 *)(ROM_BASE + base);
1016 >        
1017 >        static const int spr_check_list[] = {
1018 >                952 /* mmcr0 */, 953 /* pmc1 */, 954 /* pmc2 */, 955 /* sia */,
1019 >                956 /* mmcr1 */, 957 /* pmc3 */, 958 /* pmc4 */, 959 /* sda */
1020 >        };
1021 >
1022 >        for (int i = 0; i < sizeof(spr_check_list)/sizeof(spr_check_list[0]); i++) {
1023 >                int spr = spr_check_list[i];
1024 >                uint32 mtspr = 0x7e4003a6 | ((spr & 0x1f) << 16) | ((spr & 0x3e0) << 6);
1025 >                uint32 mfspr = 0x7e6002a6 | ((spr & 0x1f) << 16) | ((spr & 0x3e0) << 6);
1026 >                for (int ofs = 0; ofs < 64; ofs++) {
1027 >                        if (ntohl(lp[ofs]) == mtspr) {
1028 >                                if (ntohl(lp[ofs + 2]) != mfspr)
1029 >                                        return false;
1030 >                                D(bug("  SPR%d %08lx\n", spr, base + 4*ofs));
1031 >                                lp[ofs] = htonl(POWERPC_NOP);
1032 >                                lp[ofs + 2] = htonl(POWERPC_NOP);
1033 >                        }
1034 >                }
1035 >        }
1036  
1037          // Jump to 68k emulator
1038 <        static const uint32 jump68k_ofs[] = {0x40c, 0x40c, 0x40c, 0x414, 0x434, 0x438};
1039 <        lp = (uint32 *)(ROM_BASE + loc + jump68k_ofs[ROMType]);
1038 >        static const uint8 jump68k_dat[] = {0x7d, 0x92, 0x43, 0xa6, 0x7d, 0x5a, 0x03, 0xa6, 0x7d, 0x7b, 0x03, 0xa6};
1039 >        if ((loc = find_rom_data(0x310000, 0x320000, jump68k_dat, sizeof(jump68k_dat))) == 0) return false;
1040 >        static const uint8 jump68k_caller_dat[] = {0x85, 0x13, 0x00, 0x08, 0x56, 0xbf, 0x50, 0x3e, 0x63, 0xff, 0x0c, 0x00};
1041 >        if ((base = find_rom_data(0x310000, 0x320000, jump68k_caller_dat, sizeof(jump68k_caller_dat))) == 0) return false;
1042 >        if ((base = find_rom_powerpc_branch(base + 12, 0x320000, loc)) == 0) return false;
1043 >        D(bug("jump68k %08lx, called from %08lx\n", loc, base));
1044 >        lp = (uint32 *)(ROM_BASE + base);
1045          *lp++ = htonl(0x80610634);              // lwz  r3,0x0634(r1)   (pointer to Emulator Data)
1046          *lp++ = htonl(0x8081119c);              // lwz  r4,0x119c(r1)   (pointer to opcode table)
1047          *lp++ = htonl(0x80011184);              // lwz  r0,0x1184(r1)   (pointer to emulator init routine)
# Line 978 | Line 1061 | static bool patch_68k_emul(void)
1061          uint32 base;
1062  
1063          // Overwrite twi instructions
1064 <        static const uint32 twi_loc[] = {0x36e680, 0x36e6c0, 0x36e6c0, 0x36e6c0, 0x36e740, 0x36e740};
1065 <        base = twi_loc[ROMType];
1064 >        static const uint8 twi_dat[] = {0x0f, 0xff, 0x00, 0x00, 0x0f, 0xff, 0x00, 0x01, 0x0f, 0xff, 0x00, 0x02};
1065 >        if ((base = find_rom_data(0x36e600, 0x36ea00, twi_dat, sizeof(twi_dat))) == 0) return false;
1066 >        D(bug("twi %08lx\n", base));
1067          lp = (uint32 *)(ROM_BASE + base);
1068          *lp++ = htonl(0x48000000 + 0x36f900 - base);            // b 0x36f900 (Emulator start)
1069          *lp++ = htonl(0x48000000 + 0x36fa00 - base - 4);        // b 0x36fa00 (Mixed mode)
# Line 1199 | Line 1283 | dr_found:
1283   static bool patch_nanokernel(void)
1284   {
1285          uint32 *lp;
1286 +        uint32 base, loc;
1287  
1288          // Patch Mixed Mode trap
1289 <        lp = (uint32 *)(ROM_BASE + 0x313c90);   // Don't translate virtual->physical
1290 <        while (ntohl(*lp) != 0x3ba10320) lp++;
1291 <        lp++;
1292 <        *lp++ = htonl(0x7f7fdb78);                                      // mr           r31,r27
1293 <        lp++;
1294 <        *lp = htonl(POWERPC_NOP);
1295 <
1296 <        lp = (uint32 *)(ROM_BASE + 0x313c3c);   // Don't activate PPC exception table
1297 <        while (ntohl(*lp) != 0x39010420) lp++;
1289 >        static const uint8 virt2phys_dat[] = {0x7d, 0x1b, 0x43, 0x78, 0x3b, 0xa1, 0x03, 0x20};
1290 >        if ((base = find_rom_data(0x313000, 0x314000, virt2phys_dat, sizeof(virt2phys_dat))) == 0) return false;
1291 >        D(bug("virt2phys %08lx\n", base + 8));
1292 >        lp = (uint32 *)(ROM_BASE + base + 8);   // Don't translate virtual->physical
1293 >        lp[0] = htonl(0x7f7fdb78);                                      // mr           r31,r27
1294 >        lp[2] = htonl(POWERPC_NOP);
1295 >
1296 >        static const uint8 ppc_excp_tbl_dat[] = {0x39, 0x01, 0x04, 0x20, 0x7d, 0x13, 0x43, 0xa6};
1297 >        if ((base = find_rom_data(0x313000, 0x314000, ppc_excp_tbl_dat, sizeof(ppc_excp_tbl_dat))) == 0) return false;
1298 >        D(bug("ppc_excp_tbl %08lx\n", base));
1299 >        lp = (uint32 *)(ROM_BASE + base);               // Don't activate PPC exception table
1300          *lp++ = htonl(0x39000000 + MODE_NATIVE);        // li   r8,MODE_NATIVE
1301 <        *lp = htonl(0x91000000 + XLM_RUN_MODE); // stw  r8,XLM_RUN_MODE
1301 >        *lp = htonl(0x91000000 + XLM_RUN_MODE);         // stw  r8,XLM_RUN_MODE
1302  
1303 <        lp = (uint32 *)(ROM_BASE + 0x312e88);   // Don't modify MSR to turn on FPU
1304 <        while (ntohl(*lp) != 0x556b04e2) lp++;
1305 <        lp -= 4;
1303 >        static const uint8 save_fpu_dat[] = {0x7d, 0x00, 0x00, 0xa6, 0x61, 0x08, 0x20, 0x00, 0x7d, 0x00, 0x01, 0x24};
1304 >        if ((base = find_rom_data(0x310000, 0x314000, save_fpu_dat, sizeof(save_fpu_dat))) == 0) return false;
1305 >        D(bug("save_fpu %08lx\n", base));
1306 >        lp = (uint32 *)(ROM_BASE + base);               // Don't modify MSR to turn on FPU
1307 >        if (ntohl(lp[4]) != 0x556b04e2) return false;
1308 >        loc = ROM_BASE + base;
1309 > #if 1
1310 >        // FIXME: is that really intended?
1311          *lp++ = htonl(POWERPC_NOP);
1312          lp++;
1313          *lp++ = htonl(POWERPC_NOP);
1314          lp++;
1315          *lp = htonl(POWERPC_NOP);
1316 + #else
1317 +        lp[0] = htonl(POWERPC_NOP);
1318 +        lp[1] = htonl(POWERPC_NOP);
1319 +        lp[2] = htonl(POWERPC_NOP);
1320 +        lp[3] = htonl(POWERPC_NOP);
1321 + #endif
1322  
1323 <        lp = (uint32 *)(ROM_BASE + 0x312b3c);   // Always save FPU state
1324 <        while (ntohl(*lp) != 0x81010668) lp++;
1325 <        lp--;
1323 >        static const uint8 save_fpu_caller_dat[] = {0x93, 0xa6, 0x01, 0xec, 0x93, 0xc6, 0x01, 0xf4, 0x93, 0xe6, 0x01, 0xfc, 0x40};
1324 >        if ((base = find_rom_data(0x310000, 0x314000, save_fpu_caller_dat, sizeof(save_fpu_caller_dat))) == 0) return false;
1325 >        D(bug("save_fpu_caller %08lx\n", base + 12));
1326 >        if (powerpc_branch_target(ROM_BASE + base + 12) != loc) return false;
1327 >        lp = (uint32 *)(ROM_BASE + base + 12);  // Always save FPU state
1328          *lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff));        // bl   0x00312e88
1329  
1330 <        lp = (uint32 *)(ROM_BASE + 0x312b44);   // Don't read DEC
1331 <        while (ntohl(*lp) != 0x7ff602a6) lp++;
1332 <        *lp = htonl(0x3be00000);                                        // li   r31,0
1333 <
1334 <        lp = (uint32 *)(ROM_BASE + 0x312b50);   // Don't write DEC
1235 <        while (ntohl(*lp) != 0x7d1603a6) lp++;
1330 >        static const uint8 mdec_dat[] = {0x7f, 0xf6, 0x02, 0xa6, 0x2c, 0x08, 0x00, 0x00, 0x93, 0xe1, 0x06, 0x68, 0x7d, 0x16, 0x03, 0xa6};
1331 >        if ((base = find_rom_data(0x310000, 0x314000, mdec_dat, sizeof(mdec_dat))) == 0) return false;
1332 >        D(bug("mdec %08lx\n", base));
1333 >        lp = (uint32 *)(ROM_BASE + base);               // Don't modify DEC
1334 >        lp[0] = htonl(0x3be00000);                                      // li   r31,0
1335   #if 1
1336 <        *lp++ = htonl(POWERPC_NOP);
1337 <        *lp = htonl(POWERPC_NOP);
1336 >        lp[3] = htonl(POWERPC_NOP);
1337 >        lp[4] = htonl(POWERPC_NOP);
1338   #else
1339 <        *lp++ = htonl(0x39000040);                                      // li   r8,0x40
1340 <        *lp = htonl(0x990600e4);                                        // stb  r8,0xe4(r6)
1339 >        lp[3] = htonl(0x39000040);                                      // li   r8,0x40
1340 >        lp[4] = htonl(0x990600e4);                                      // stb  r8,0xe4(r6)
1341   #endif
1342  
1343 <        lp = (uint32 *)(ROM_BASE + 0x312b9c);   // Always restore FPU state
1344 <        while (ntohl(*lp) != 0x7c00092d) lp++;
1345 <        lp--;
1343 >        static const uint8 restore_fpu_caller_dat[] = {0x81, 0x06, 0x00, 0xf4, 0x81, 0x46, 0x00, 0xfc, 0x7d, 0x09, 0x03, 0xa6, 0x40};
1344 >        if ((base = find_rom_data(0x310000, 0x314000, restore_fpu_caller_dat, sizeof(restore_fpu_caller_dat))) == 0) return false;
1345 >        D(bug("restore_fpu_caller %08lx\n", base + 12));
1346 >        lp = (uint32 *)(ROM_BASE + base + 12);  // Always restore FPU state
1347          *lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff));        // bl   0x00312ddc
1348  
1349 <        lp = (uint32 *)(ROM_BASE + 0x312a68);   // Don't activate 68k exception table
1350 <        while (ntohl(*lp) != 0x39010360) lp++;
1349 >        static const uint8 m68k_excp_tbl_dat[] = {0x81, 0x21, 0x06, 0x58, 0x39, 0x01, 0x03, 0x60, 0x7d, 0x13, 0x43, 0xa6};
1350 >        if ((base = find_rom_data(0x310000, 0x314000, m68k_excp_tbl_dat, sizeof(m68k_excp_tbl_dat))) == 0) return false;
1351 >        D(bug("m68k_excp %08lx\n", base + 4));
1352 >        lp = (uint32 *)(ROM_BASE + base + 4);   // Don't activate 68k exception table
1353          *lp++ = htonl(0x39000000 + MODE_68K);           // li   r8,MODE_68K
1354          *lp = htonl(0x91000000 + XLM_RUN_MODE);         // stw  r8,XLM_RUN_MODE
1355  
1356          // Patch 68k emulator trap routine
1357 <        lp = (uint32 *)(ROM_BASE + 0x312994);   // Always restore FPU state
1358 <        while (ntohl(*lp) != 0x39260040) lp++;
1359 <        lp--;
1357 >        static const uint8 restore_fpu_caller2_dat[] = {0x81, 0x86, 0x00, 0x8c, 0x80, 0x66, 0x00, 0x94, 0x80, 0x86, 0x00, 0x9c, 0x40};
1358 >        if ((base = find_rom_data(0x310000, 0x314000, restore_fpu_caller2_dat, sizeof(restore_fpu_caller2_dat))) == 0) return false;
1359 >        D(bug("restore_fpu_caller2 %08lx\n", base + 12));
1360 >        loc = powerpc_branch_target(ROM_BASE + base + 12) - ROM_BASE;
1361 >        lp = (uint32 *)(ROM_BASE + base + 12);  // Always restore FPU state
1362          *lp = htonl(0x48000000 | (ntohl(*lp) & 0xffff));        // bl   0x00312dd4
1363  
1364 <        lp = (uint32 *)(ROM_BASE + 0x312dd8);   // Don't modify MSR to turn on FPU
1365 <        while (ntohl(*lp) != 0x810600e4) lp++;
1366 <        lp--;
1364 >        static const uint8 restore_fpu_dat[] = {0x55, 0x68, 0x04, 0xa5, 0x4c, 0x82, 0x00, 0x20, 0x81, 0x06, 0x00, 0xe4};
1365 >        if ((base = find_rom_data(0x310000, 0x314000, restore_fpu_dat, sizeof(restore_fpu_dat))) == 0) return false;
1366 >        D(bug("restore_fpu %08lx\n", base));
1367 >        if (base != loc) return false;
1368 >        lp = (uint32 *)(ROM_BASE + base + 4);   // Don't modify MSR to turn on FPU
1369          *lp++ = htonl(POWERPC_NOP);
1370          lp += 2;
1371          *lp++ = htonl(POWERPC_NOP);
# Line 1269 | Line 1375 | static bool patch_nanokernel(void)
1375          *lp = htonl(POWERPC_NOP);
1376  
1377          // Patch trap return routine
1378 <        lp = (uint32 *)(ROM_BASE + 0x312c20);
1379 <        while (ntohl(*lp) != 0x7d5a03a6) lp++;
1378 >        static const uint8 trap_return_dat[] = {0x80, 0xc1, 0x00, 0x18, 0x80, 0x21, 0x00, 0x04, 0x4c, 0x00, 0x00, 0x64};
1379 >        if ((base = find_rom_data(0x312000, 0x320000, trap_return_dat, sizeof(trap_return_dat))) == 0) return false;
1380 >        D(bug("trap_return %08lx\n", base + 8));
1381 >        lp = (uint32 *)(ROM_BASE + base + 8);   // Replace rfi
1382 >        *lp = htonl(POWERPC_BCTR);
1383 >
1384 >        while (ntohl(*lp) != 0x7d5a03a6) lp--;
1385          *lp++ = htonl(0x7d4903a6);                                      // mtctr        r10
1386          *lp++ = htonl(0x7daff120);                                      // mtcr r13
1387 <        *lp = htonl(0x48000000 + 0x8000 - (((uint32)lp - ROM_BASE) & 0xffff));  // b            ROM_BASE+0x318000
1388 <        uint32 xlp = ((uint32)(lp+1) - ROM_BASE) & 0xffff;
1278 <
1279 <        lp = (uint32 *)(ROM_BASE + 0x312c50);   // Replace rfi
1280 <        while (ntohl(*lp) != 0x4c000064) lp++;
1281 <        *lp = htonl(POWERPC_BCTR);
1387 >        *lp = htonl(0x48000000 + ((0x318000 - ((uint32)lp - ROM_BASE)) & 0x03fffffc));  // b            ROM_BASE+0x318000
1388 >        uint32 npc = (uint32)(lp + 1) - ROM_BASE;
1389  
1390          lp = (uint32 *)(ROM_BASE + 0x318000);
1391   #if EMULATED_PPC
1392          *lp++ = htonl(NativeOpcode(NATIVE_ENABLE_INTERRUPT));
1393 <        *lp = htonl(0x48000000 + ((xlp - 0x8004) & 0x03fffffc));        // b            ROM_BASE+0x312c2c
1393 >        *lp = htonl(0x48000000 + ((npc - 0x318004) & 0x03fffffc));      // b            ROM_BASE+0x312c2c
1394   #else
1395          *lp++ = htonl(0x81400000 + XLM_IRQ_NEST);       // lwz  r10,XLM_IRQ_NEST
1396          *lp++ = htonl(0x394affff);                                      // subi r10,r10,1
1397          *lp++ = htonl(0x91400000 + XLM_IRQ_NEST);       // stw  r10,XLM_IRQ_NEST
1398 <        *lp = htonl(0x48000000 + ((xlp - 0x800c) & 0x03fffffc));        // b            ROM_BASE+0x312c2c
1398 >        *lp = htonl(0x48000000 + ((npc - 0x31800c) & 0x03fffffc));      // b            ROM_BASE+0x312c2c
1399   #endif
1400  
1401   /*
# Line 1310 | Line 1417 | static bool patch_68k(void)
1417          uint32 *lp;
1418          uint16 *wp;
1419          uint8 *bp;
1420 <        uint32 base;
1420 >        uint32 base, loc;
1421  
1422          // Remove 68k RESET instruction
1423          static const uint8 reset_dat[] = {0x4e, 0x70};
# Line 1551 | Line 1658 | static bool patch_68k(void)
1658          *wp = htons(M68K_NOP);
1659  
1660          // Don't initialize SCC (via 0x1ac)
1661 <        static const uint8 scc_init_dat[] = {0x48, 0xe7, 0x38, 0xfe};
1662 <        if ((base = find_rom_data(0x190, 0x1f0, scc_init_dat, sizeof(scc_init_dat))) == 0) return false;
1661 >        static const uint8 scc_init_caller_dat[] = {0x21, 0xce, 0x01, 0x08, 0x22, 0x78, 0x0d, 0xd8};
1662 >        if ((base = find_rom_data(0x180, 0x1f0, scc_init_caller_dat, sizeof(scc_init_caller_dat))) == 0) return false;
1663 >        D(bug("scc_init_caller %08lx\n", base + 12));
1664 >        wp = (uint16 *)(ROM_BASE + base + 12);
1665 >        loc = ntohs(wp[1]) + ((uintptr)wp - ROM_BASE) + 2;
1666 >        static const uint8 scc_init_dat[] = {0x20, 0x78, 0x01, 0xdc, 0x22, 0x78, 0x01, 0xd8};
1667 >        if ((base = find_rom_data(loc, loc + 0x80, scc_init_dat, sizeof(scc_init_dat))) != loc) return false;
1668          D(bug("scc_init %08lx\n", base));
1669 <        wp = (uint16 *)(ROM_BASE + base - 2);
1558 <        wp = (uint16 *)(ROM_BASE + ntohs(*wp) + base - 2);
1669 >        wp = (uint16 *)(ROM_BASE + base);
1670          *wp++ = htons(M68K_EMUL_OP_RESET);
1671          *wp = htons(M68K_RTS);
1672  
# Line 1839 | Line 1950 | static bool patch_68k(void)
1950                  *lp = htonl(0x38600000);                // li   r3,0
1951          }
1952  
1953 +        // FIXME: Fake reading from [HpChk]+4 (the callchain reports some function from DriverServicesLib)
1954 +        if (1) {
1955 +                uint32 hpchk_offset = find_rom_resource(FOURCC('n','l','i','b'), 10);
1956 +                static const uint8 hpchk_dat[] = {0x80, 0x80, 0x03, 0x16, 0x94, 0x21, 0xff, 0xb0, 0x83, 0xc4, 0x00, 0x04};
1957 +                if ((base = find_rom_data(hpchk_offset, hpchk_offset + 0x3000, hpchk_dat, sizeof(hpchk_dat))) == 0) return false;
1958 +                D(bug("hpchk %08lx\n", base));
1959 +                lp = (uint32 *)(ROM_BASE + base);
1960 +                *lp = htonl(0x80800000 + XLM_ZERO_PAGE);                // lwz  r4,(zero page)
1961 +        }
1962 +
1963          // Patch Name Registry
1964          static const uint8 name_reg_dat[] = {0x70, 0xff, 0xab, 0xeb};
1965          if ((base = find_rom_data(0x300, 0x380, name_reg_dat, sizeof(name_reg_dat))) == 0) return false;
# Line 2186 | Line 2307 | void InstallDrivers(void)
2307  
2308   #if DISABLE_SCSI && 0
2309          // Fake SCSIGlobals
2310 <        static const uint8 fake_scsi_globals[32] = {0,};
2190 <        WriteMacInt32(0xc0c, (uint32)fake_scsi_globals);
2310 >        WriteMacInt32(0xc0c, SheepMem::ZeroPage());
2311   #endif
2312  
2313          // Open .Sony driver

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