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root/cebix/SheepShaver/src/rom_patches.cpp

Comparing SheepShaver/src/rom_patches.cpp (file contents):
Revision 1.29 by gbeauche, 2004-05-31T09:04:42Z vs.
Revision 1.32 by gbeauche, 2004-06-30T08:17:12Z

#	Line 847 | Line 847 | static bool patch_nanokernel_boot(void)
847		lp[7] = htonl(0x00040004);      // Inst cache assoc/Data cache assoc
848		lp[8] = htonl(0x00400002);      // TLB total size/TLB assoc
849		break;
850	<	case 8:         // 750
850	>	case 8:         // 750, 750FX
851	>	case 0x7000:
852		lp[0] = htonl(0x1000);          // Page size
853		lp[1] = htonl(0x8000);          // Data cache size
854		lp[2] = htonl(0x8000);          // Inst cache size
#	Line 871 | Line 872 | static bool patch_nanokernel_boot(void)
872		lp[8] = htonl(0x00800002);      // TLB total size/TLB assoc
873		break;
874		//              case 11:        // X704?
875	<	case 12:        // 7400, 7410
875	>	case 12:        // 7400, 7410, 7450, 7455, 7457
876		case 0x800c:
877	+	case 0x8000:
878	+	case 0x8001:
879	+	case 0x8002:
880		lp[0] = htonl(0x1000);          // Page size
881		lp[1] = htonl(0x8000);          // Data cache size
882		lp[2] = htonl(0x8000);          // Inst cache size
#	Line 1122 | Line 1126 | static bool patch_68k_emul(void)
1126		// Extra routine for 68k emulator start
1127		lp = (uint32 *)(ROM_BASE + 0x36f900);
1128		*lp++ = htonl(0x7c2903a6);                                      // mtctr        r1
1125	–	#if EMULATED_PPC
1126	–	*lp++ = htonl(NativeOpcode(NATIVE_DISABLE_INTERRUPT));
1127	–	#else
1129		*lp++ = htonl(0x80200000 + XLM_IRQ_NEST);       // lwz          r1,XLM_IRQ_NEST
1130		*lp++ = htonl(0x38210001);                                      // addi         r1,r1,1
1131		*lp++ = htonl(0x90200000 + XLM_IRQ_NEST);       // stw          r1,XLM_IRQ_NEST
1131	–	#endif
1132		*lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz              r1,XLM_KERNEL_DATA
1133		*lp++ = htonl(0x90c10018);                                      // stw          r6,0x18(r1)
1134		*lp++ = htonl(0x7cc902a6);                                      // mfctr        r6
#	Line 1156 | Line 1156 | static bool patch_68k_emul(void)
1156		// Extra routine for Mixed Mode
1157		lp = (uint32 *)(ROM_BASE + 0x36fa00);
1158		*lp++ = htonl(0x7c2903a6);                                      // mtctr        r1
1159	–	#if EMULATED_PPC
1160	–	*lp++ = htonl(NativeOpcode(NATIVE_DISABLE_INTERRUPT));
1161	–	#else
1159		*lp++ = htonl(0x80200000 + XLM_IRQ_NEST);       // lwz          r1,XLM_IRQ_NEST
1160		*lp++ = htonl(0x38210001);                                      // addi         r1,r1,1
1161		*lp++ = htonl(0x90200000 + XLM_IRQ_NEST);       // stw          r1,XLM_IRQ_NEST
1165	–	#endif
1162		*lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz              r1,XLM_KERNEL_DATA
1163		*lp++ = htonl(0x90c10018);                                      // stw          r6,0x18(r1)
1164		*lp++ = htonl(0x7cc902a6);                                      // mfctr        r6
#	Line 1190 | Line 1186 | static bool patch_68k_emul(void)
1186		// Extra routine for Reset/FC1E opcode
1187		lp = (uint32 *)(ROM_BASE + 0x36fb00);
1188		*lp++ = htonl(0x7c2903a6);                                      // mtctr        r1
1193	–	#if EMULATED_PPC
1194	–	*lp++ = htonl(NativeOpcode(NATIVE_DISABLE_INTERRUPT));
1195	–	#else
1189		*lp++ = htonl(0x80200000 + XLM_IRQ_NEST);       // lwz          r1,XLM_IRQ_NEST
1190		*lp++ = htonl(0x38210001);                                      // addi         r1,r1,1
1191		*lp++ = htonl(0x90200000 + XLM_IRQ_NEST);       // stw          r1,XLM_IRQ_NEST
1199	–	#endif
1192		*lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz              r1,XLM_KERNEL_DATA
1193		*lp++ = htonl(0x90c10018);                                      // stw          r6,0x18(r1)
1194		*lp++ = htonl(0x7cc902a6);                                      // mfctr        r6
#	Line 1224 | Line 1216 | static bool patch_68k_emul(void)
1216		// Extra routine for FE0A opcode (QuickDraw 3D needs this)
1217		lp = (uint32 *)(ROM_BASE + 0x36fc00);
1218		*lp++ = htonl(0x7c2903a6);                                      // mtctr        r1
1227	–	#if EMULATED_PPC
1228	–	*lp++ = htonl(NativeOpcode(NATIVE_DISABLE_INTERRUPT));
1229	–	#else
1219		*lp++ = htonl(0x80200000 + XLM_IRQ_NEST);       // lwz          r1,XLM_IRQ_NEST
1220		*lp++ = htonl(0x38210001);                                      // addi         r1,r1,1
1221		*lp++ = htonl(0x90200000 + XLM_IRQ_NEST);       // stw          r1,XLM_IRQ_NEST
1233	–	#endif
1222		*lp++ = htonl(0x80200000 + XLM_KERNEL_DATA);// lwz              r1,XLM_KERNEL_DATA
1223		*lp++ = htonl(0x90c10018);                                      // stw          r6,0x18(r1)
1224		*lp++ = htonl(0x7cc902a6);                                      // mfctr        r6
#	Line 1397 | Line 1385 | static bool patch_nanokernel(void)
1385		uint32 npc = (uint32)(lp + 1) - ROM_BASE;
1386
1387		lp = (uint32 *)(ROM_BASE + 0x318000);
1400	–	#if EMULATED_PPC
1401	–	*lp++ = htonl(NativeOpcode(NATIVE_ENABLE_INTERRUPT));
1402	–	*lp = htonl(0x48000000 + ((npc - 0x318004) & 0x03fffffc));      // b            ROM_BASE+0x312c2c
1403	–	#else
1388		*lp++ = htonl(0x81400000 + XLM_IRQ_NEST);       // lwz  r10,XLM_IRQ_NEST
1389		*lp++ = htonl(0x394affff);                                      // subi r10,r10,1
1390		*lp++ = htonl(0x91400000 + XLM_IRQ_NEST);       // stw  r10,XLM_IRQ_NEST
1391		*lp = htonl(0x48000000 + ((npc - 0x31800c) & 0x03fffffc));      // b            ROM_BASE+0x312c2c
1408	–	#endif
1392
1393		/*
1394		// Disable FE0A/FE06 opcodes
#	Line 1767 | Line 1750 | static bool patch_68k(void)
1750		*wp++ = htons(0x1000);
1751		*wp++ = htons(0x001e);
1752		*wp++ = htons(0x157c);                  // move.b       #PVR,$1d(a2)
1753	<	*wp++ = htons(PVR >> 16);
1753	>	*wp++ = htons(((PVR & 0x80000000) ? 0x10 : 0) | ((PVR >> 16) & 0xff));
1754		*wp++ = htons(0x001d);
1755		*wp++ = htons(0x263c);                  // move.l       #RAMSize,d3
1756		*wp++ = htons(RAMSize >> 16);

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