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root/cebix/mon/src/mon_z80.cpp
Revision: 1.3
Committed: 2002-01-18T16:03:33Z (22 years, 3 months ago) by cebix
Branch: MAIN
Changes since 1.2: +1 -1 lines
Log Message: 
- copyright year bumped to 2002
- in MacOS mode, mon pulls in the lowmem globals as predefined variables
- mon_lowmem.h split into .h/.cpp because it's now used in two places
- variable handling code rewritten to use map<> instead of manually maintained
  linked list

File Contents

# User Rev Content
1 cebix 1.1 /*
2     * mon_z80.cpp - Z80 disassembler
3     *
4 cebix 1.3 * cxmon (C) 1997-2002 Christian Bauer, Marc Hellwig
5 cebix 1.1 *
6     * This program is free software; you can redistribute it and/or modify
7     * it under the terms of the GNU General Public License as published by
8     * the Free Software Foundation; either version 2 of the License, or
9     * (at your option) any later version.
10     *
11     * This program is distributed in the hope that it will be useful,
12     * but WITHOUT ANY WARRANTY; without even the implied warranty of
13     * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14     * GNU General Public License for more details.
15     *
16     * You should have received a copy of the GNU General Public License
17     * along with this program; if not, write to the Free Software
18     * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19     */
20    
21     #include "sysdeps.h"
22    
23     #include <stdarg.h>
24    
25     #include "mon.h"
26     #include "mon_disass.h"
27    
28    
29     // Addressing modes
30     enum {
31     A_IMPL,
32     A_IMM8, // xx
33     A_IMM16, // xxxx
34     A_ABS8, // (xx)
35     A_ABS16, // (xxxx)
36     A_REL, // relative
37     A_A, // a
38     A_HL, // hl or ix or iy
39     A_SP, // sp
40     A_REG1, // 8-bit register (bits 0..2 of opcode) or (hl)/(ix+d)/(iy+d)
41     A_REG1X, // 8-bit register (bits 0..2 of opcode) or (hl)/(ix+d)/(iy+d), don't substitute h or l on prefixes
42     A_REG2, // 8-bit register (bits 3..5 of opcode) or (hl)/(ix+d)/(iy+d)
43     A_REG2X, // 8-bit register (bits 3..5 of opcode) or (hl)/(ix+d)/(iy+d), don't substitute h or l on prefixes
44     A_REG3, // 16-bit register (bits 4..5 of opcode) bc/de/hl/sp
45     A_REG4, // 16-bit register (bits 4..5 of opcode) bc/de/hl/af
46     A_COND, // condition code (bits 3..5 of opcode)
47     A_COND2, // condition code (bits 3..4 of opcode)
48     A_BIT, // bit number (bits 3..5 of opcode)
49     A_RST, // restart
50     A_BC_IND, // (bc)
51     A_DE_IND, // (de)
52     A_HL_IND, // (hl) or (ix) or (iy)
53     A_SP_IND, // (sp)
54     A_DE_HL, // de,hl
55     A_AF_AF, // af,af'
56     };
57    
58     // Mnemonics
59     enum {
60     M_ADC, M_ADD, M_AND, M_BIT, M_CALL, M_CCF, M_CP, M_CPD, M_CPDR, M_CPI,
61     M_CPIR, M_CPL, M_DAA, M_DEC, M_DI, M_DJNZ, M_EI, M_EX, M_EXX, M_HALT,
62     M_IM0, M_IM1, M_IM2, M_IN, M_INC, M_IND, M_INDR, M_INI, M_INIR, M_JP,
63     M_JR, M_LD, M_LDD, M_LDDR, M_LDI, M_LDIR, M_NEG, M_NOP, M_OR, M_OTDR,
64     M_OTIR, M_OUT, M_OUTD, M_OUTI, M_POP, M_PUSH, M_RES, M_RET, M_RETI,
65     M_RETN, M_RL, M_RLA, M_RLC, M_RLCA, M_RLD, M_RR, M_RRA, M_RRC, M_RRCA,
66     M_RRD, M_RST, M_SBC, M_SCF, M_SET, M_SL1, M_SLA, M_SRA, M_SRL, M_SUB,
67     M_XOR,
68     M_ILLEGAL,
69    
70     M_MAXIMUM
71     };
72    
73     // Chars for each mnemonic
74     static const char mnem_1[] = "aaabccccccccddddeeehiiiiiiiiijjlllllnnoooooopprrrrrrrrrrrrrrrssssssssx?";
75     static const char mnem_2[] = "ddniacppppppaeijixxammmnnnnnnprdddddeorttuuuoueeeelllllrrrrrsbcellrruo ";
76     static const char mnem_3[] = "cddtlf ddiilac n xl cddii ddiigp ditttpssttt accd accdtcft1aalbr ";
77     static const char mnem_4[] = " l r r z t012 r r r r rr di h in a a ";
78    
79     // Mnemonic for each opcode
80     static const char mnemonic[256] = {
81     M_NOP , M_LD , M_LD , M_INC , M_INC , M_DEC , M_LD , M_RLCA, // 00
82     M_EX , M_ADD, M_LD , M_DEC , M_INC , M_DEC , M_LD , M_RRCA,
83     M_DJNZ, M_LD , M_LD , M_INC , M_INC , M_DEC , M_LD , M_RLA , // 10
84     M_JR , M_ADD, M_LD , M_DEC , M_INC , M_DEC , M_LD , M_RRA ,
85     M_JR , M_LD , M_LD , M_INC , M_INC , M_DEC , M_LD , M_DAA , // 20
86     M_JR , M_ADD, M_LD , M_DEC , M_INC , M_DEC , M_LD , M_CPL ,
87     M_JR , M_LD , M_LD , M_INC , M_INC , M_DEC , M_LD , M_SCF , // 30
88     M_JR , M_ADD, M_LD , M_DEC , M_INC , M_DEC , M_LD , M_CCF ,
89     M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , // 40
90     M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , M_LD ,
91     M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , // 50
92     M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , M_LD ,
93     M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , // 60
94     M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , M_LD ,
95     M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , M_HALT, M_LD , // 70
96     M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , M_LD , M_LD ,
97     M_ADD , M_ADD, M_ADD, M_ADD , M_ADD , M_ADD , M_ADD , M_ADD , // 80
98     M_ADC , M_ADC, M_ADC, M_ADC , M_ADC , M_ADC , M_ADC , M_ADC ,
99     M_SUB , M_SUB, M_SUB, M_SUB , M_SUB , M_SUB , M_SUB , M_SUB , // 90
100     M_SBC , M_SBC, M_SBC, M_SBC , M_SBC , M_SBC , M_SBC , M_SBC ,
101     M_AND , M_AND, M_AND, M_AND , M_AND , M_AND , M_AND , M_AND , // a0
102     M_XOR , M_XOR, M_XOR, M_XOR , M_XOR , M_XOR , M_XOR , M_XOR ,
103     M_OR , M_OR , M_OR , M_OR , M_OR , M_OR , M_OR , M_OR , // b0
104     M_CP , M_CP , M_CP , M_CP , M_CP , M_CP , M_CP , M_CP ,
105     M_RET , M_POP, M_JP , M_JP , M_CALL, M_PUSH , M_ADD , M_RST , // c0
106     M_RET , M_RET, M_JP , M_ILLEGAL, M_CALL, M_CALL , M_ADC , M_RST ,
107     M_RET , M_POP, M_JP , M_OUT , M_CALL, M_PUSH , M_SUB , M_RST , // d0
108     M_RET , M_EXX, M_JP , M_IN , M_CALL, M_ILLEGAL, M_SBC , M_RST ,
109     M_RET , M_POP, M_JP , M_EX , M_CALL, M_PUSH , M_AND , M_RST , // e0
110     M_RET , M_JP , M_JP , M_EX , M_CALL, M_ILLEGAL, M_XOR , M_RST ,
111     M_RET , M_POP, M_JP , M_DI , M_CALL, M_PUSH , M_OR , M_RST , // f0
112     M_RET , M_LD , M_JP , M_EI , M_CALL, M_ILLEGAL, M_CP , M_RST
113     };
114    
115     // Source/destination addressing modes for each opcode
116     #define A(d,s) (((A_ ## d) << 8) | (A_ ## s))
117    
118     static const short adr_mode[256] = {
119     A(IMPL,IMPL) , A(REG3,IMM16) , A(BC_IND,A) , A(REG3,IMPL) , A(REG2,IMPL) , A(REG2,IMPL) , A(REG2,IMM8) , A(IMPL,IMPL) , // 00
120     A(AF_AF,IMPL) , A(HL,REG3) , A(A,BC_IND) , A(REG3,IMPL) , A(REG2,IMPL) , A(REG2,IMPL) , A(REG2,IMM8) , A(IMPL,IMPL) ,
121     A(REL,IMPL) , A(REG3,IMM16) , A(DE_IND,A) , A(REG3,IMPL) , A(REG2,IMPL) , A(REG2,IMPL) , A(REG2,IMM8) , A(IMPL,IMPL) , // 10
122     A(REL,IMPL) , A(HL,REG3) , A(A,DE_IND) , A(REG3,IMPL) , A(REG2,IMPL) , A(REG2,IMPL) , A(REG2,IMM8) , A(IMPL,IMPL) ,
123     A(COND2,REL) , A(REG3,IMM16) , A(ABS16,HL) , A(REG3,IMPL) , A(REG2,IMPL) , A(REG2,IMPL) , A(REG2,IMM8) , A(IMPL,IMPL) , // 20
124     A(COND2,REL) , A(HL,REG3) , A(HL,ABS16) , A(REG3,IMPL) , A(REG2,IMPL) , A(REG2,IMPL) , A(REG2,IMM8) , A(IMPL,IMPL) ,
125     A(COND2,REL) , A(REG3,IMM16) , A(ABS16,A) , A(REG3,IMPL) , A(REG2,IMPL) , A(REG2,IMPL) , A(REG2,IMM8) , A(IMPL,IMPL) , // 30
126     A(COND2,REL) , A(HL,REG3) , A(A,ABS16) , A(REG3,IMPL) , A(REG2,IMPL) , A(REG2,IMPL) , A(REG2,IMM8) , A(IMPL,IMPL) ,
127     A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2X,REG1), A(REG2,REG1) , // 40
128     A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2X,REG1), A(REG2,REG1) ,
129     A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2X,REG1), A(REG2,REG1) , // 50
130     A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2X,REG1), A(REG2,REG1) ,
131     A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2X,REG1), A(REG2,REG1) , // 60
132     A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2X,REG1), A(REG2,REG1) ,
133     A(REG2,REG1X) , A(REG2,REG1X) , A(REG2,REG1X), A(REG2,REG1X), A(REG2,REG1X), A(REG2,REG1X), A(IMPL,IMPL) , A(REG2,REG1X), // 70
134     A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2,REG1) , A(REG2X,REG1), A(REG2,REG1) ,
135     A(A,REG1) , A(A,REG1) , A(A,REG1) , A(A,REG1) , A(A,REG1) , A(A,REG1) , A(A,REG1) , A(A,REG1) , // 80
136     A(A,REG1) , A(A,REG1) , A(A,REG1) , A(A,REG1) , A(A,REG1) , A(A,REG1) , A(A,REG1) , A(A,REG1) ,
137     A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , // 90
138     A(A,REG1) , A(A,REG1) , A(A,REG1) , A(A,REG1) , A(A,REG1) , A(A,REG1) , A(A,REG1) , A(A,REG1) ,
139     A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , // a0
140     A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) ,
141     A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , // b0
142     A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) , A(REG1,IMPL) ,
143     A(COND,IMPL) , A(REG4,IMPL) , A(COND,IMM16), A(IMM16,IMPL), A(COND,IMM16), A(REG4,IMPL) , A(A,IMM8) , A(RST,IMPL) , // c0
144     A(COND,IMPL) , A(IMPL,IMPL) , A(COND,IMM16), A(IMPL,IMPL) , A(COND,IMM16), A(IMM16,IMPL), A(A,IMM8) , A(RST,IMPL) ,
145     A(COND,IMPL) , A(REG4,IMPL) , A(COND,IMM16), A(ABS8,A) , A(COND,IMM16), A(REG4,IMPL) , A(IMM8,IMPL) , A(RST,IMPL) , // d0
146     A(COND,IMPL) , A(IMPL,IMPL) , A(COND,IMM16), A(A,ABS8) , A(COND,IMM16), A(IMPL,IMPL) , A(A,IMM8) , A(RST,IMPL) ,
147     A(COND,IMPL) , A(REG4,IMPL) , A(COND,IMM16), A(SP_IND,HL) , A(COND,IMM16), A(REG4,IMPL) , A(IMM8,IMPL) , A(RST,IMPL) , // e0
148     A(COND,IMPL) , A(HL_IND,IMPL), A(COND,IMM16), A(DE_HL,IMPL), A(COND,IMM16), A(IMPL,IMPL) , A(IMM8,IMPL) , A(RST,IMPL) ,
149     A(COND,IMPL) , A(REG4,IMPL) , A(COND,IMM16), A(IMPL,IMPL) , A(COND,IMM16), A(REG4,IMPL) , A(IMM8,IMPL) , A(RST,IMPL) , // f0
150     A(COND,IMPL) , A(SP,HL) , A(COND,IMM16), A(IMPL,IMPL) , A(COND,IMM16), A(IMPL,IMPL) , A(IMM8,IMPL) , A(RST,IMPL)
151     };
152    
153    
154     /*
155     * sprintf into a "stream"
156     */
157    
158     struct SFILE {
159     char *buffer;
160     char *current;
161     };
162    
163     static int mon_sprintf(SFILE *f, const char *format, ...)
164     {
165     int n;
166     va_list args;
167     va_start(args, format);
168     vsprintf(f->current, format, args);
169     f->current += n = strlen(f->current);
170     va_end(args);
171     return n;
172     }
173    
174    
175     /*
176     * Disassemble one instruction, return number of bytes
177     */
178    
179     static const char *reg_name[] = {"b", "c", "d", "e", "h", "l", "*", "a"};
180     static const char *reg_name_ix[] = {"b", "c", "d", "e", "hx", "lx", "*", "a"}; // undoc
181     static const char *reg_name_iy[] = {"b", "c", "d", "e", "hy", "ly", "*", "a"}; // undoc
182     static const char *reg_name_16[] = {"bc", "de", "hl", "sp"};
183     static const char *reg_name_16_2[] = {"bc", "de", "hl", "af"};
184     static const char *cond_name[] = {"nz", "z", "nc", "c", "po", "pe", "p", "m"};
185    
186     static void operand(SFILE *f, char mode, uint32 &adr, uint8 op, bool ix, bool iy)
187     {
188     switch (mode) {
189     case A_IMPL:
190     break;
191    
192     case A_IMM8:
193     mon_sprintf(f, "$%02x", mon_read_byte(adr)); adr++;
194     break;
195    
196     case A_IMM16:
197     mon_sprintf(f, "$%04x", (mon_read_byte(adr + 1) << 8) | mon_read_byte(adr)); adr += 2;
198     break;
199    
200     case A_ABS8:
201     mon_sprintf(f, "($%02x)", mon_read_byte(adr)); adr++;
202     break;
203    
204     case A_ABS16:
205     mon_sprintf(f, "($%04x)", (mon_read_byte(adr + 1) << 8) | mon_read_byte(adr)); adr += 2;
206     break;
207    
208     case A_REL:
209     mon_sprintf(f, "$%04x", (adr + 2 + (int8)mon_read_byte(adr)) & 0xffff); adr++;
210     break;
211    
212     case A_A:
213     mon_sprintf(f, "a");
214     break;
215    
216     case A_HL:
217     mon_sprintf(f, ix ? "ix" : (iy ? "iy" : "hl"));
218     break;
219    
220     case A_SP:
221     mon_sprintf(f, "sp");
222     break;
223    
224     case A_REG1:
225     case A_REG1X: {
226     int reg = op & 7;
227     if (reg == 6) {
228     if (ix || iy) {
229     mon_sprintf(f, "(%s+$%02x)", ix ? "ix" : "iy", mon_read_byte(adr)); adr++;
230     } else
231     mon_sprintf(f, "(hl)");
232     } else if (mode == A_REG1)
233     mon_sprintf(f, "%s", ix ? reg_name_ix[reg] : (iy ? reg_name_iy[reg] : reg_name[reg]));
234     else
235     mon_sprintf(f, "%s", reg_name[reg]);
236     break;
237     }
238    
239     case A_REG2:
240     case A_REG2X: {
241     int reg = (op >> 3) & 7;
242     if (reg == 6) {
243     if (ix || iy) {
244     mon_sprintf(f, "(%s+$%02x)", ix ? "ix" : "iy", mon_read_byte(adr)); adr++;
245     } else
246     mon_sprintf(f, "(hl)");
247     } else if (mode == A_REG2)
248     mon_sprintf(f, "%s", ix ? reg_name_ix[reg] : (iy ? reg_name_iy[reg] : reg_name[reg]));
249     else
250     mon_sprintf(f, "%s", reg_name[reg]);
251     break;
252     }
253    
254     case A_REG3:
255     mon_sprintf(f, reg_name_16[(op >> 4) & 3]);
256     break;
257    
258     case A_REG4:
259     mon_sprintf(f, reg_name_16_2[(op >> 4) & 3]);
260     break;
261    
262     case A_COND:
263     mon_sprintf(f, cond_name[(op >> 3) & 7]);
264     break;
265    
266     case A_COND2:
267     mon_sprintf(f, cond_name[(op >> 3) & 3]);
268     break;
269    
270     case A_BIT:
271     mon_sprintf(f, "%d", (op >> 3) & 7);
272     break;
273    
274     case A_RST:
275     mon_sprintf(f, "$%02x", op & 0x38);
276     break;
277    
278     case A_BC_IND:
279     mon_sprintf(f, "(bc)");
280     break;
281    
282     case A_DE_IND:
283     mon_sprintf(f, "(de)");
284     break;
285    
286     case A_HL_IND:
287     mon_sprintf(f, ix ? "(ix)" : (iy ? "(iy)" : "(hl)"));
288     break;
289    
290     case A_SP_IND:
291     mon_sprintf(f, "(sp)");
292     break;
293    
294     case A_DE_HL:
295     mon_sprintf(f, "de,hl");
296     break;
297    
298     case A_AF_AF:
299     mon_sprintf(f, "af,af'");
300     break;
301     }
302     }
303    
304     static int print_instr(SFILE *f, char mnem, char dst_mode, char src_mode, uint32 adr, uint8 op, bool ix, bool iy)
305     {
306     uint32 orig_adr = adr;
307    
308     // Print mnemonic
309     mon_sprintf(f, "%c%c%c%c ", mnem_1[mnem], mnem_2[mnem], mnem_3[mnem], mnem_4[mnem]);
310    
311     // Print destination operand
312     operand(f, dst_mode, adr, op, ix, iy);
313    
314     // Print source operand
315     if (src_mode != A_IMPL)
316     mon_sprintf(f, ",");
317     operand(f, src_mode, adr, op, ix, iy);
318    
319     return adr - orig_adr;
320     }
321    
322     static int disass_cb(SFILE *f, uint32 adr, bool ix, bool iy)
323     {
324     int num;
325    
326     // Fetch opcode
327     uint8 op;
328     if (ix || iy) {
329     op = mon_read_byte(adr + 1);
330     num = 2;
331     } else {
332     op = mon_read_byte(adr);
333     num = 1;
334     }
335    
336     // Decode mnemonic and addressing modes
337 cebix 1.2 char mnem = M_ILLEGAL, dst_mode = A_IMPL, src_mode = A_IMPL;
338 cebix 1.1 switch (op & 0xc0) {
339     case 0x00:
340     dst_mode = A_REG1;
341     switch ((op >> 3) & 7) {
342     case 0: mnem = M_RLC; break;
343     case 1: mnem = M_RRC; break;
344     case 2: mnem = M_RL; break;
345     case 3: mnem = M_RR; break;
346     case 4: mnem = M_SLA; break;
347     case 5: mnem = M_SRA; break;
348     case 6: mnem = M_SL1; break;
349     case 7: mnem = M_SRL; break;
350     }
351     break;
352     case 0x40:
353     mnem = M_BIT; dst_mode = A_BIT; src_mode = A_REG1;
354     break;
355     case 0x80:
356     mnem = M_RES; dst_mode = A_BIT; src_mode = A_REG1;
357     break;
358     case 0xc0:
359     mnem = M_SET; dst_mode = A_BIT; src_mode = A_REG1;
360     break;
361     }
362    
363     // Print instruction
364     print_instr(f, mnem, dst_mode, src_mode, adr, op, ix, iy);
365     return num;
366     }
367    
368     static int disass_ed(SFILE *f, uint32 adr)
369     {
370     // Fetch opcode
371     uint8 op = mon_read_byte(adr);
372    
373     // Decode mnemonic and addressing modes
374     char mnem, dst_mode = A_IMPL, src_mode = A_IMPL;
375     switch (op) {
376     case 0x40:
377     case 0x48:
378     case 0x50:
379     case 0x58:
380     case 0x60:
381     case 0x68:
382     case 0x78:
383     mon_sprintf(f, "in\t%s,(c)", reg_name[(op >> 3) & 7]);
384     return 1;
385     case 0x70:
386     mon_sprintf(f, "in\t(c)");
387     return 1;
388    
389     case 0x41:
390     case 0x49:
391     case 0x51:
392     case 0x59:
393     case 0x61:
394     case 0x69:
395     case 0x79:
396     mon_sprintf(f, "out\t(c),%s", reg_name[(op >> 3) & 7]);
397     return 1;
398     case 0x71: // undoc
399     mon_sprintf(f, "out\t(c),0");
400     return 1;
401    
402     case 0x42:
403     case 0x52:
404     case 0x62:
405     case 0x72:
406     mnem = M_SBC; dst_mode = A_HL; src_mode = A_REG3;
407     break;
408    
409     case 0x43:
410     case 0x53:
411     case 0x63:
412     case 0x73:
413     mnem = M_LD; dst_mode = A_ABS16; src_mode = A_REG3;
414     break;
415    
416     case 0x4a:
417     case 0x5a:
418     case 0x6a:
419     case 0x7a:
420     mnem = M_ADC; dst_mode = A_HL; src_mode = A_REG3;
421     break;
422    
423     case 0x4b:
424     case 0x5b:
425     case 0x6b:
426     case 0x7b:
427     mnem = M_LD; dst_mode = A_REG3; src_mode = A_ABS16;
428     break;
429    
430     case 0x44:
431     case 0x4c: // undoc
432     case 0x54: // undoc
433     case 0x5c: // undoc
434     case 0x64: // undoc
435     case 0x6c: // undoc
436     case 0x74: // undoc
437     case 0x7c: // undoc
438     mnem = M_NEG;
439     break;
440    
441     case 0x45:
442     case 0x55: // undoc
443     case 0x5d: // undoc
444     case 0x65: // undoc
445     case 0x6d: // undoc
446     case 0x75: // undoc
447     case 0x7d: // undoc
448     mnem = M_RETN;
449     break;
450     case 0x4d: mnem = M_RETI; break;
451    
452     case 0x46:
453     case 0x4e: // undoc
454     case 0x66: // undoc
455     case 0x6e: // undoc
456     mnem = M_IM0;
457     break;
458     case 0x56:
459     case 0x76: // undoc
460     mnem = M_IM1;
461     break;
462     case 0x5e:
463     case 0x7e: // undoc
464     mnem = M_IM2;
465     break;
466    
467     case 0x47:
468     mon_sprintf(f, "ld\ti,a");
469     return 1;
470     case 0x4f:
471     mon_sprintf(f, "ld\tr,a");
472     return 1;
473     case 0x57:
474     mon_sprintf(f, "ld\ta,i");
475     return 1;
476     case 0x5f:
477     mon_sprintf(f, "ld\ta,r");
478     return 1;
479    
480     case 0x67: mnem = M_RRD; break;
481     case 0x6f: mnem = M_RLD; break;
482    
483     case 0xa0: mnem = M_LDI; break;
484     case 0xa1: mnem = M_CPI; break;
485     case 0xa2: mnem = M_INI; break;
486     case 0xa3: mnem = M_OUTI; break;
487     case 0xa8: mnem = M_LDD; break;
488     case 0xa9: mnem = M_CPD; break;
489     case 0xaa: mnem = M_IND; break;
490     case 0xab: mnem = M_OUTD; break;
491     case 0xb0: mnem = M_LDIR; break;
492     case 0xb1: mnem = M_CPIR; break;
493     case 0xb2: mnem = M_INIR; break;
494     case 0xb3: mnem = M_OTIR; break;
495     case 0xb8: mnem = M_LDDR; break;
496     case 0xb9: mnem = M_CPDR; break;
497     case 0xba: mnem = M_INDR; break;
498     case 0xbb: mnem = M_OTDR; break;
499    
500     default:
501     mnem = M_ILLEGAL;
502     break;
503     }
504    
505     // Print instruction
506     return print_instr(f, mnem, dst_mode, src_mode, adr + 1, op, false, false) + 1;
507     }
508    
509     static int disass(SFILE *f, uint32 adr, bool ix, bool iy)
510     {
511     uint8 op = mon_read_byte(adr);
512     if (op == 0xcb)
513     return disass_cb(f, adr + 1, ix, iy) + 1;
514     else
515     return print_instr(f, mnemonic[op], adr_mode[op] >> 8, adr_mode[op] & 0xff, adr + 1, op, ix, iy) + 1;
516     }
517    
518     int disass_z80(FILE *f, uint32 adr)
519     {
520     int num;
521     char buf[64];
522     SFILE sfile = {buf, buf};
523    
524     switch (mon_read_byte(adr)) {
525     case 0xdd: // ix prefix
526     num = disass(&sfile, adr + 1, true, false) + 1;
527     break;
528     case 0xed:
529     num = disass_ed(&sfile, adr + 1) + 1;
530     break;
531     case 0xfd: // iy prefix
532     num = disass(&sfile, adr + 1, false, true) + 1;
533     break;
534     default:
535     num = disass(&sfile, adr, false, false);
536     break;
537     }
538    
539     for (int i=0; i<4; i++) {
540     if (num > i)
541     fprintf(f, "%02x ", mon_read_byte(adr + i));
542     else
543     fprintf(f, " ");
544     }
545    
546     fprintf(f, "\t%s\n", buf);
547     return num;
548     }