src/uae_cpu/newcpu.h

 /*
  * UAE - The Un*x Amiga Emulator
  *
  * MC68000 emulation
  *
  * Copyright 1995 Bernd Schmidt
  */

#ifndef NEWCPU_H
#define NEWCPU_H

#include "m68k.h"
#include "readcpu.h"
#include "spcflags.h"
 
extern int areg_byteinc[];
extern int imm8_table[];

extern int movem_index1[256];
extern int movem_index2[256];
extern int movem_next[256];

extern int fpp_movem_index1[256];
extern int fpp_movem_index2[256];
extern int fpp_movem_next[256];

extern int broken_in;

/* Control flow information */
#define CFLOW_NORMAL            0
#define CFLOW_BRANCH            1
#define CFLOW_JUMP                      2
#define CFLOW_TRAP                      CFLOW_JUMP
#define CFLOW_RETURN            3
#define CFLOW_SPCFLAGS          32      /* some spcflags are set */
#define CFLOW_EXEC_RETURN       64      /* must exit from the execution loop */

#define cpuop_rettype           void
#define cpuop_return(v)         do { (v); return; } while (0)

#ifdef X86_ASSEMBLY
/* This hack seems to force all register saves (pushl %reg) to be moved to the
   begining of the function, thus making it possible to cpuopti to remove them
   since m68k_run_1 will save those registers before calling the instruction
   handler */
# define cpuop_tag(tag)         __asm__ __volatile__ ( "#cpuop_" tag )
#else
# define cpuop_tag(tag)         ;
#endif

#define cpuop_begin()           do { cpuop_tag("begin"); } while (0)
#define cpuop_end(cflow)        do { cpuop_tag("end"); cpuop_return(cflow); } while (0)

typedef cpuop_rettype REGPARAM2 cpuop_func (uae_u32) REGPARAM;
 
struct cputbl {
    cpuop_func *handler;
    uae_u16 specific;
    uae_u16 opcode;
};

extern cpuop_rettype REGPARAM2 op_illg (uae_u32) REGPARAM;

typedef char flagtype;

struct regstruct {
    uae_u32             regs[16];

    uae_u32             pc;
    uae_u8 *    pc_p;
    uae_u8 *    pc_oldp;

        spcflags_t      spcflags;
    int                 intmask;

    uae_u32             vbr, sfc, dfc;
    uaecptr             usp, isp, msp;
    uae_u16             sr;
    flagtype    t1;
    flagtype    t0;
    flagtype    s;
    flagtype    m;
    flagtype    x;
    flagtype    stopped;

    double              fp[8];
    uae_u32             fpcr,fpsr,fpiar;

#if USE_PREFETCH_BUFFER
    /* Fellow sources say this is 4 longwords. That's impossible. It needs
     * to be at least a longword. The HRM has some cryptic comment about two
     * instructions being on the same longword boundary.
     * The way this is implemented now seems like a good compromise.
     */
    uae_u32 prefetch;
#endif
};

extern regstruct regs, lastint_regs;

#define m68k_dreg(r,num) ((r).regs[(num)])
#define m68k_areg(r,num) (((r).regs + 8)[(num)])

#define get_ibyte(o) do_get_mem_byte((uae_u8 *)(regs.pc_p + (o) + 1))
#define get_iword(o) do_get_mem_word((uae_u16 *)(regs.pc_p + (o)))
#define get_ilong(o) do_get_mem_long((uae_u32 *)(regs.pc_p + (o)))

#ifdef HAVE_GET_WORD_UNSWAPPED
#define GET_OPCODE (do_get_mem_word_unswapped (regs.pc_p))
#else
#define GET_OPCODE (get_iword (0))
#endif

#if USE_PREFETCH_BUFFER
static __inline__ uae_u32 get_ibyte_prefetch (uae_s32 o)
{
    if (o > 3 || o < 0)
        return do_get_mem_byte((uae_u8 *)(regs.pc_p + o + 1));

    return do_get_mem_byte((uae_u8 *)(((uae_u8 *)&regs.prefetch) + o + 1));
}
static __inline__ uae_u32 get_iword_prefetch (uae_s32 o)
{
    if (o > 3 || o < 0)
        return do_get_mem_word((uae_u16 *)(regs.pc_p + o));

    return do_get_mem_word((uae_u16 *)(((uae_u8 *)&regs.prefetch) + o));
}
static __inline__ uae_u32 get_ilong_prefetch (uae_s32 o)
{
    if (o > 3 || o < 0)
        return do_get_mem_long((uae_u32 *)(regs.pc_p + o));
    if (o == 0)
        return do_get_mem_long(&regs.prefetch);
    return (do_get_mem_word (((uae_u16 *)&regs.prefetch) + 1) << 16) | do_get_mem_word ((uae_u16 *)(regs.pc_p + 4));
}
#endif

#define m68k_incpc(o) (regs.pc_p += (o))

static __inline__ void fill_prefetch_0 (void)
{
#if USE_PREFETCH_BUFFER
    uae_u32 r;
#ifdef UNALIGNED_PROFITABLE
    r = *(uae_u32 *)regs.pc_p;
    regs.prefetch = r;
#else
    r = do_get_mem_long ((uae_u32 *)regs.pc_p);
    do_put_mem_long (&regs.prefetch, r);
#endif
#endif
}

#if 0
static __inline__ void fill_prefetch_2 (void)
{
    uae_u32 r = do_get_mem_long (&regs.prefetch) << 16;
    uae_u32 r2 = do_get_mem_word (((uae_u16 *)regs.pc_p) + 1);
    r |= r2;
    do_put_mem_long (&regs.prefetch, r);
}
#else
#define fill_prefetch_2 fill_prefetch_0
#endif

/* These are only used by the 68020/68881 code, and therefore don't
 * need to handle prefetch.  */
static __inline__ uae_u32 next_ibyte (void)
{
    uae_u32 r = get_ibyte (0);
    m68k_incpc (2);
    return r;
}

static __inline__ uae_u32 next_iword (void)
{
    uae_u32 r = get_iword (0);
    m68k_incpc (2);
    return r;
}

static __inline__ uae_u32 next_ilong (void)
{
    uae_u32 r = get_ilong (0);
    m68k_incpc (4);
    return r;
}

static __inline__ void m68k_setpc (uaecptr newpc)
{
#if REAL_ADDRESSING || DIRECT_ADDRESSING
        regs.pc_p = get_real_address(newpc);
#else
    regs.pc_p = regs.pc_oldp = get_real_address(newpc);
    regs.pc = newpc;
#endif
}

static __inline__ uaecptr m68k_getpc (void)
{
#if REAL_ADDRESSING || DIRECT_ADDRESSING
        return get_virtual_address(regs.pc_p);
#else
    return regs.pc + ((char *)regs.pc_p - (char *)regs.pc_oldp);
#endif
}

#define m68k_setpc_fast m68k_setpc
#define m68k_setpc_bcc  m68k_setpc
#define m68k_setpc_rte  m68k_setpc

static __inline__ void m68k_do_rts(void)
{
            m68k_setpc(get_long(m68k_areg(regs, 7)));
                m68k_areg(regs, 7) += 4;
}
 
static __inline__ void m68k_do_bsr(uaecptr oldpc, uae_s32 offset)
{
            m68k_areg(regs, 7) -= 4;
                put_long(m68k_areg(regs, 7), oldpc);
                    m68k_incpc(offset);
}
 
static __inline__ void m68k_do_jsr(uaecptr oldpc, uaecptr dest)
{
            m68k_areg(regs, 7) -= 4;
                put_long(m68k_areg(regs, 7), oldpc);
                    m68k_setpc(dest);
}

static __inline__ void m68k_setstopped (int stop)
{
    regs.stopped = stop;
    /* A traced STOP instruction drops through immediately without
       actually stopping.  */
    if (stop && (regs.spcflags & SPCFLAG_DOTRACE) == 0)
    SPCFLAGS_SET( SPCFLAG_STOP );
}

extern uae_u32 get_disp_ea_020 (uae_u32 base, uae_u32 dp);
extern uae_u32 get_disp_ea_000 (uae_u32 base, uae_u32 dp);

extern uae_s32 ShowEA (int reg, amodes mode, wordsizes size, char *buf);

extern void MakeSR (void);
extern void MakeFromSR (void);
extern void Exception (int, uaecptr);
extern void dump_counts (void);
extern int m68k_move2c (int, uae_u32 *);
extern int m68k_movec2 (int, uae_u32 *);
extern void m68k_divl (uae_u32, uae_u32, uae_u16, uaecptr);
extern void m68k_mull (uae_u32, uae_u32, uae_u16);
extern void m68k_emulop (uae_u32);
extern void m68k_emulop_return (void);
extern void init_m68k (void);
extern void exit_m68k (void);
extern void m68k_dumpstate (uaecptr *);
extern void m68k_disasm (uaecptr, uaecptr *, int);
extern void m68k_reset (void);
extern void m68k_enter_debugger(void);
extern int m68k_do_specialties(void);

extern void mmu_op (uae_u32, uae_u16);

extern void fpp_opp (uae_u32, uae_u16);
extern void fdbcc_opp (uae_u32, uae_u16);
extern void fscc_opp (uae_u32, uae_u16);
extern void ftrapcc_opp (uae_u32,uaecptr);
extern void fbcc_opp (uae_u32, uaecptr, uae_u32);
extern void fsave_opp (uae_u32);
extern void frestore_opp (uae_u32);

extern void fpu_set_integral_fpu (bool is_integral);
extern void fpu_init (void);
extern void fpu_exit (void);
extern void fpu_reset (void);

/* Opcode of faulting instruction */
extern uae_u16 last_op_for_exception_3;
/* PC at fault time */
extern uaecptr last_addr_for_exception_3;
/* Address that generated the exception */
extern uaecptr last_fault_for_exception_3;

#define CPU_OP_NAME(a) op ## a

/* 68020 + 68881 */
extern struct cputbl op_smalltbl_0_ff[];
/* 68020 */
extern struct cputbl op_smalltbl_1_ff[];
/* 68010 */
extern struct cputbl op_smalltbl_2_ff[];
/* 68000 */
extern struct cputbl op_smalltbl_3_ff[];
/* 68000 slow but compatible.  */
extern struct cputbl op_smalltbl_4_ff[];

extern void m68k_do_execute(void);
extern void m68k_execute(void);
 
#endif /* NEWCPU_H */
Revision:	1.8
Committed:	2002-09-01T15:17:13Z (21 years, 9 months ago) by gbeauche
Content type:	text/plain
Branch:	MAIN
Changes since 1.7:	+71 -57 lines
Log Message:	- Merge with Basilisk II/JIT cpu core, interpretive part for now - Clean use of USE_PREFETCH_BUFFER macro and dependent bits
#	User	Rev	Content
1	cebix	1.1	/*
2			* UAE - The Un*x Amiga Emulator
3			*
4			* MC68000 emulation
5			*
6			* Copyright 1995 Bernd Schmidt
7			*/
8
9	gbeauche	1.4	#ifndef NEWCPU_H
10			#define NEWCPU_H
11
12	gbeauche	1.8	#include "m68k.h"
13			#include "readcpu.h"
14			#include "spcflags.h"
15
16	cebix	1.1	extern int areg_byteinc[];
17			extern int imm8_table[];
18
19			extern int movem_index1[256];
20			extern int movem_index2[256];
21			extern int movem_next[256];
22
23			extern int fpp_movem_index1[256];
24			extern int fpp_movem_index2[256];
25			extern int fpp_movem_next[256];
26
27			extern int broken_in;
28
29	gbeauche	1.8	/* Control flow information */
30			#define CFLOW_NORMAL 0
31			#define CFLOW_BRANCH 1
32			#define CFLOW_JUMP 2
33			#define CFLOW_TRAP CFLOW_JUMP
34			#define CFLOW_RETURN 3
35			#define CFLOW_SPCFLAGS 32 /* some spcflags are set */
36			#define CFLOW_EXEC_RETURN 64 /* must exit from the execution loop */
37
38			#define cpuop_rettype void
39			#define cpuop_return(v) do { (v); return; } while (0)
40
41			#ifdef X86_ASSEMBLY
42			/* This hack seems to force all register saves (pushl %reg) to be moved to the
43			begining of the function, thus making it possible to cpuopti to remove them
44			since m68k_run_1 will save those registers before calling the instruction
45			handler */
46			# define cpuop_tag(tag) __asm__ __volatile__ ( "#cpuop_" tag )
47			#else
48			# define cpuop_tag(tag) ;
49			#endif
50
51			#define cpuop_begin() do { cpuop_tag("begin"); } while (0)
52			#define cpuop_end(cflow) do { cpuop_tag("end"); cpuop_return(cflow); } while (0)
53	cebix	1.1
54	gbeauche	1.8	typedef cpuop_rettype REGPARAM2 cpuop_func (uae_u32) REGPARAM;
55
56	cebix	1.1	struct cputbl {
57			cpuop_func *handler;
58	gbeauche	1.8	uae_u16 specific;
59	cebix	1.1	uae_u16 opcode;
60			};
61
62	gbeauche	1.8	extern cpuop_rettype REGPARAM2 op_illg (uae_u32) REGPARAM;
63	cebix	1.1
64			typedef char flagtype;
65
66	gbeauche	1.8	struct regstruct {
67			uae_u32 regs[16];
68	cebix	1.1
69	gbeauche	1.8	uae_u32 pc;
70			uae_u8 * pc_p;
71			uae_u8 * pc_oldp;
72
73			spcflags_t spcflags;
74			int intmask;
75
76			uae_u32 vbr, sfc, dfc;
77			uaecptr usp, isp, msp;
78			uae_u16 sr;
79			flagtype t1;
80			flagtype t0;
81			flagtype s;
82			flagtype m;
83			flagtype x;
84			flagtype stopped;
85	cebix	1.1
86	gbeauche	1.8	double fp[8];
87			uae_u32 fpcr,fpsr,fpiar;
88	cebix	1.1
89	gbeauche	1.8	#if USE_PREFETCH_BUFFER
90	cebix	1.1	/* Fellow sources say this is 4 longwords. That's impossible. It needs
91			* to be at least a longword. The HRM has some cryptic comment about two
92			* instructions being on the same longword boundary.
93			* The way this is implemented now seems like a good compromise.
94			*/
95			uae_u32 prefetch;
96	gbeauche	1.8	#endif
97			};
98
99			extern regstruct regs, lastint_regs;
100	cebix	1.1
101			#define m68k_dreg(r,num) ((r).regs[(num)])
102			#define m68k_areg(r,num) (((r).regs + 8)[(num)])
103
104			#define get_ibyte(o) do_get_mem_byte((uae_u8 *)(regs.pc_p + (o) + 1))
105			#define get_iword(o) do_get_mem_word((uae_u16 *)(regs.pc_p + (o)))
106			#define get_ilong(o) do_get_mem_long((uae_u32 *)(regs.pc_p + (o)))
107
108			#ifdef HAVE_GET_WORD_UNSWAPPED
109			#define GET_OPCODE (do_get_mem_word_unswapped (regs.pc_p))
110			#else
111			#define GET_OPCODE (get_iword (0))
112			#endif
113
114	gbeauche	1.8	#if USE_PREFETCH_BUFFER
115	cebix	1.1	static __inline__ uae_u32 get_ibyte_prefetch (uae_s32 o)
116			{
117			if (o > 3 \|\| o < 0)
118			return do_get_mem_byte((uae_u8 *)(regs.pc_p + o + 1));
119
120			return do_get_mem_byte((uae_u8 )(((uae_u8 )&regs.prefetch) + o + 1));
121			}
122			static __inline__ uae_u32 get_iword_prefetch (uae_s32 o)
123			{
124			if (o > 3 \|\| o < 0)
125			return do_get_mem_word((uae_u16 *)(regs.pc_p + o));
126
127			return do_get_mem_word((uae_u16 )(((uae_u8 )&regs.prefetch) + o));
128			}
129			static __inline__ uae_u32 get_ilong_prefetch (uae_s32 o)
130			{
131			if (o > 3 \|\| o < 0)
132			return do_get_mem_long((uae_u32 *)(regs.pc_p + o));
133			if (o == 0)
134			return do_get_mem_long(&regs.prefetch);
135			return (do_get_mem_word (((uae_u16 )&regs.prefetch) + 1) << 16) \| do_get_mem_word ((uae_u16 )(regs.pc_p + 4));
136			}
137	gbeauche	1.8	#endif
138	cebix	1.1
139			#define m68k_incpc(o) (regs.pc_p += (o))
140
141			static __inline__ void fill_prefetch_0 (void)
142			{
143	gbeauche	1.4	#if USE_PREFETCH_BUFFER
144	cebix	1.1	uae_u32 r;
145			#ifdef UNALIGNED_PROFITABLE
146			r = (uae_u32 )regs.pc_p;
147			regs.prefetch = r;
148			#else
149			r = do_get_mem_long ((uae_u32 *)regs.pc_p);
150			do_put_mem_long (&regs.prefetch, r);
151			#endif
152	gbeauche	1.4	#endif
153	cebix	1.1	}
154
155			#if 0
156			static __inline__ void fill_prefetch_2 (void)
157			{
158			uae_u32 r = do_get_mem_long (&regs.prefetch) << 16;
159			uae_u32 r2 = do_get_mem_word (((uae_u16 *)regs.pc_p) + 1);
160			r \|= r2;
161			do_put_mem_long (&regs.prefetch, r);
162			}
163			#else
164			#define fill_prefetch_2 fill_prefetch_0
165			#endif
166
167			/* These are only used by the 68020/68881 code, and therefore don't
168			* need to handle prefetch. */
169			static __inline__ uae_u32 next_ibyte (void)
170			{
171			uae_u32 r = get_ibyte (0);
172			m68k_incpc (2);
173			return r;
174			}
175
176			static __inline__ uae_u32 next_iword (void)
177			{
178			uae_u32 r = get_iword (0);
179			m68k_incpc (2);
180			return r;
181			}
182
183			static __inline__ uae_u32 next_ilong (void)
184			{
185			uae_u32 r = get_ilong (0);
186			m68k_incpc (4);
187			return r;
188			}
189
190			static __inline__ void m68k_setpc (uaecptr newpc)
191			{
192	gbeauche	1.4	#if REAL_ADDRESSING \|\| DIRECT_ADDRESSING
193			regs.pc_p = get_real_address(newpc);
194			#else
195	cebix	1.1	regs.pc_p = regs.pc_oldp = get_real_address(newpc);
196			regs.pc = newpc;
197	gbeauche	1.4	#endif
198	cebix	1.1	}
199
200			static __inline__ uaecptr m68k_getpc (void)
201			{
202	gbeauche	1.4	#if REAL_ADDRESSING \|\| DIRECT_ADDRESSING
203			return get_virtual_address(regs.pc_p);
204			#else
205	cebix	1.1	return regs.pc + ((char )regs.pc_p - (char )regs.pc_oldp);
206	gbeauche	1.4	#endif
207	cebix	1.1	}
208
209			#define m68k_setpc_fast m68k_setpc
210			#define m68k_setpc_bcc m68k_setpc
211			#define m68k_setpc_rte m68k_setpc
212
213	gbeauche	1.5	static __inline__ void m68k_do_rts(void)
214			{
215			m68k_setpc(get_long(m68k_areg(regs, 7)));
216			m68k_areg(regs, 7) += 4;
217			}
218
219			static __inline__ void m68k_do_bsr(uaecptr oldpc, uae_s32 offset)
220			{
221			m68k_areg(regs, 7) -= 4;
222			put_long(m68k_areg(regs, 7), oldpc);
223			m68k_incpc(offset);
224			}
225
226			static __inline__ void m68k_do_jsr(uaecptr oldpc, uaecptr dest)
227			{
228			m68k_areg(regs, 7) -= 4;
229			put_long(m68k_areg(regs, 7), oldpc);
230			m68k_setpc(dest);
231			}
232
233	cebix	1.1	static __inline__ void m68k_setstopped (int stop)
234			{
235			regs.stopped = stop;
236	gbeauche	1.7	/* A traced STOP instruction drops through immediately without
237			actually stopping. */
238			if (stop && (regs.spcflags & SPCFLAG_DOTRACE) == 0)
239	gbeauche	1.8	SPCFLAGS_SET( SPCFLAG_STOP );
240	cebix	1.1	}
241
242			extern uae_u32 get_disp_ea_020 (uae_u32 base, uae_u32 dp);
243			extern uae_u32 get_disp_ea_000 (uae_u32 base, uae_u32 dp);
244
245			extern uae_s32 ShowEA (int reg, amodes mode, wordsizes size, char *buf);
246
247			extern void MakeSR (void);
248			extern void MakeFromSR (void);
249			extern void Exception (int, uaecptr);
250			extern void dump_counts (void);
251	gbeauche	1.6	extern int m68k_move2c (int, uae_u32 *);
252			extern int m68k_movec2 (int, uae_u32 *);
253	cebix	1.1	extern void m68k_divl (uae_u32, uae_u32, uae_u16, uaecptr);
254			extern void m68k_mull (uae_u32, uae_u32, uae_u16);
255	gbeauche	1.8	extern void m68k_emulop (uae_u32);
256			extern void m68k_emulop_return (void);
257	cebix	1.1	extern void init_m68k (void);
258	gbeauche	1.3	extern void exit_m68k (void);
259	cebix	1.1	extern void m68k_dumpstate (uaecptr *);
260			extern void m68k_disasm (uaecptr, uaecptr *, int);
261			extern void m68k_reset (void);
262			extern void m68k_enter_debugger(void);
263	gbeauche	1.8	extern int m68k_do_specialties(void);
264	cebix	1.1
265			extern void mmu_op (uae_u32, uae_u16);
266
267			extern void fpp_opp (uae_u32, uae_u16);
268			extern void fdbcc_opp (uae_u32, uae_u16);
269			extern void fscc_opp (uae_u32, uae_u16);
270			extern void ftrapcc_opp (uae_u32,uaecptr);
271			extern void fbcc_opp (uae_u32, uaecptr, uae_u32);
272			extern void fsave_opp (uae_u32);
273			extern void frestore_opp (uae_u32);
274	gbeauche	1.3
275			extern void fpu_set_integral_fpu (bool is_integral);
276			extern void fpu_init (void);
277			extern void fpu_exit (void);
278			extern void fpu_reset (void);
279	cebix	1.1
280			/* Opcode of faulting instruction */
281			extern uae_u16 last_op_for_exception_3;
282			/* PC at fault time */
283			extern uaecptr last_addr_for_exception_3;
284			/* Address that generated the exception */
285			extern uaecptr last_fault_for_exception_3;
286
287			#define CPU_OP_NAME(a) op ## a
288
289			/* 68020 + 68881 */
290	gbeauche	1.8	extern struct cputbl op_smalltbl_0_ff[];
291	cebix	1.1	/* 68020 */
292	gbeauche	1.8	extern struct cputbl op_smalltbl_1_ff[];
293	cebix	1.1	/* 68010 */
294	gbeauche	1.8	extern struct cputbl op_smalltbl_2_ff[];
295	cebix	1.1	/* 68000 */
296	gbeauche	1.8	extern struct cputbl op_smalltbl_3_ff[];
297	cebix	1.1	/* 68000 slow but compatible. */
298	gbeauche	1.8	extern struct cputbl op_smalltbl_4_ff[];
299	cebix	1.1
300	gbeauche	1.8	extern void m68k_do_execute(void);
301			extern void m68k_execute(void);
302
303	gbeauche	1.4	#endif /* NEWCPU_H */